6c63e84d23
Added PANIC assertion of 32-bit physical address in PAE mode cleanup
144 lines
4.0 KiB
C++
144 lines
4.0 KiB
C++
/////////////////////////////////////////////////////////////////////////
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// $Id: flag_ctrl_pro.cc,v 1.25 2006-10-04 19:08:40 sshwarts Exp $
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/////////////////////////////////////////////////////////////////////////
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//
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// Copyright (C) 2001 MandrakeSoft S.A.
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//
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// MandrakeSoft S.A.
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// 43, rue d'Aboukir
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// 75002 Paris - France
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// http://www.linux-mandrake.com/
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// http://www.mandrakesoft.com/
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//
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// This library is free software; you can redistribute it and/or
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// modify it under the terms of the GNU Lesser General Public
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// License as published by the Free Software Foundation; either
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// version 2 of the License, or (at your option) any later version.
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//
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// This library is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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// Lesser General Public License for more details.
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//
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// You should have received a copy of the GNU Lesser General Public
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// License along with this library; if not, write to the Free Software
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// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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#define NEED_CPU_REG_SHORTCUTS 1
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#include "bochs.h"
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#include "cpu.h"
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#define LOG_THIS BX_CPU_THIS_PTR
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void BX_CPP_AttrRegparmN(1) BX_CPU_C::setEFlags(Bit32u val)
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{
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// VM flag could not be set from long mode
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#if BX_SUPPORT_X86_64
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if (long_mode()) {
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if (BX_CPU_THIS_PTR get_VM()) BX_PANIC(("VM is set in long mode !"));
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val &= ~EFlagsVMMask;
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}
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#endif
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BX_CPU_THIS_PTR eflags.val32 = val;
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BX_CPU_THIS_PTR lf_flags_status = 0; // OSZAPC flags are known.
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BX_CPU_THIS_PTR set_VM(val & EFlagsVMMask);
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}
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void BX_CPP_AttrRegparmN(2)
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BX_CPU_C::writeEFlags(Bit32u flags, Bit32u changeMask)
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{
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Bit32u supportMask, newEFlags;
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// Build a mask of the non-reserved bits:
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// ID,VIP,VIF,AC,VM,RF,x,NT,IOPL,OF,DF,IF,TF,SF,ZF,x,AF,x,PF,x,CF
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supportMask = 0x00037fd5;
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#if BX_CPU_LEVEL >= 4
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supportMask |= (EFlagsIDMask | EFlagsACMask); // ID/AC
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#endif
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#if BX_SUPPORT_VME
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supportMask |= (EFlagsVPMask | EFlagsVFMask); // VIP/VIF
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#endif
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// Screen out changing of any unsupported bits.
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changeMask &= supportMask;
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newEFlags = (BX_CPU_THIS_PTR eflags.val32 & ~changeMask) |
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(flags & changeMask);
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setEFlags(newEFlags);
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// OSZAPC flags are known - done in setEFlags(newEFlags)
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if (newEFlags & EFlagsTFMask) {
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BX_CPU_THIS_PTR async_event = 1; // TF = 1
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}
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}
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void BX_CPP_AttrRegparmN(3)
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BX_CPU_C::write_flags(Bit16u flags, bx_bool change_IOPL, bx_bool change_IF)
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{
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// Build a mask of the following bits:
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// x,NT,IOPL,OF,DF,IF,TF,SF,ZF,x,AF,x,PF,x,CF
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Bit32u changeMask = 0x0dd5;
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#if BX_CPU_LEVEL >= 3
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changeMask |= EFlagsNTMask; // NT is modified as requested.
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if (change_IOPL)
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changeMask |= EFlagsIOPLMask; // IOPL is modified as requested.
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#endif
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if (change_IF)
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changeMask |= EFlagsIFMask;
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writeEFlags(Bit32u(flags), changeMask);
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}
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// Cause arithmetic flags to be in known state and cached in val32.
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Bit32u BX_CPU_C::force_flags(void)
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{
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if (BX_CPU_THIS_PTR lf_flags_status) {
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(void) get_CF();
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(void) get_PF();
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(void) get_AF();
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(void) get_ZF();
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(void) get_SF();
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(void) get_OF();
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}
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return BX_CPU_THIS_PTR eflags.val32;
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}
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Bit16u BX_CPU_C::read_flags(void)
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{
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Bit16u flags16 = (Bit16u) BX_CPU_THIS_PTR force_flags();
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/* 8086: bits 12-15 always set to 1.
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* 286: in real mode, bits 12-15 always cleared.
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* 386+: real-mode: bit15 cleared, bits 14..12 are last loaded value
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* protected-mode: bit 15 clear, bit 14 = last loaded, IOPL?
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*/
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#if BX_CPU_LEVEL < 2
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flags16 |= 0xF000; /* 8086 nature */
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#elif BX_CPU_LEVEL == 2
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if (real_mode()) {
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flags16 &= 0x0FFF; /* 80286 in real mode nature */
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}
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#endif
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return(flags16);
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}
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#if BX_CPU_LEVEL >= 3
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Bit32u BX_CPU_C::read_eflags(void)
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{
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Bit32u flags32 = BX_CPU_THIS_PTR force_flags();
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/*
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* 386+: real-mode: bit15 cleared, bits 14..12 are last loaded value
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* protected-mode: bit 15 clear, bit 14 = last loaded, IOPL?
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*/
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return(flags32);
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}
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#endif
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