491035fcb2
Read-Modify-Write instructions. The first read phase stores the host pointer in the "pages" field if a direct use pointer is available. The Write phase first checks if a pointer was issued and uses it for a direct write if available. I chose the "pages" field since it needs to be checked by the write_RMW_virtual variants anyways and thus needs to be cached anyways. Mostly the mods where to access.cc, but I did also macro-ize the calls to write_RMW_virtual...() in files which use it and cpu.h. Right now, the macro is just a straight pass-through. I tried expanding it to a quick initial check for the pointer availability to do the write in-place, with a function call as a fall-back. That didn't seemed to matter at all. Booting is not helped by this really. The upper bound of the gain is 5 or 6%, and that's only if you have a loop that looks like: label: add [eax], ebx ;; mega read-modify-write instruction jmp label ;; intensive loop.
440 lines
9.7 KiB
C++
440 lines
9.7 KiB
C++
/////////////////////////////////////////////////////////////////////////
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// $Id: logical32.cc,v 1.6 2002-09-06 21:54:58 kevinlawton Exp $
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/////////////////////////////////////////////////////////////////////////
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//
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// Copyright (C) 2001 MandrakeSoft S.A.
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//
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// MandrakeSoft S.A.
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// 43, rue d'Aboukir
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// 75002 Paris - France
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// http://www.linux-mandrake.com/
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// http://www.mandrakesoft.com/
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//
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// This library is free software; you can redistribute it and/or
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// modify it under the terms of the GNU Lesser General Public
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// License as published by the Free Software Foundation; either
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// version 2 of the License, or (at your option) any later version.
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//
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// This library is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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// Lesser General Public License for more details.
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//
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// You should have received a copy of the GNU Lesser General Public
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// License along with this library; if not, write to the Free Software
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// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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#define NEED_CPU_REG_SHORTCUTS 1
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#include "bochs.h"
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#define LOG_THIS BX_CPU_THIS_PTR
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void
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BX_CPU_C::XOR_EdGd(BxInstruction_t *i)
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{
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/* for 32 bit operand size mode */
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Bit32u op2_32, op1_32, result_32;
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/* op2_32 is a register, op2_addr is an index of a register */
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op2_32 = BX_READ_32BIT_REG(i->nnn);
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/* op1_32 is a register or memory reference */
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if (i->mod == 0xc0) {
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op1_32 = BX_READ_32BIT_REG(i->rm);
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}
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else {
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/* pointer, segment address pair */
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read_RMW_virtual_dword(i->seg, i->rm_addr, &op1_32);
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}
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result_32 = op1_32 ^ op2_32;
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/* now write result back to destination */
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if (i->mod == 0xc0) {
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BX_WRITE_32BIT_REG(i->rm, result_32);
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}
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else {
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Write_RMW_virtual_dword(result_32);
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}
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SET_FLAGS_OSZAPC_32(op1_32, op2_32, result_32, BX_INSTR_XOR32);
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}
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void
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BX_CPU_C::XOR_GdEd(BxInstruction_t *i)
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{
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/* for 32 bit operand size mode */
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Bit32u op1_32, op2_32, result_32;
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op1_32 = BX_READ_32BIT_REG(i->nnn);
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/* op2_32 is a register or memory reference */
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if (i->mod == 0xc0) {
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op2_32 = BX_READ_32BIT_REG(i->rm);
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}
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else {
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/* pointer, segment address pair */
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read_virtual_dword(i->seg, i->rm_addr, &op2_32);
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}
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result_32 = op1_32 ^ op2_32;
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/* now write result back to destination */
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BX_WRITE_32BIT_REG(i->nnn, result_32);
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SET_FLAGS_OSZAPC_32(op1_32, op2_32, result_32, BX_INSTR_XOR32);
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}
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void
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BX_CPU_C::XOR_EAXId(BxInstruction_t *i)
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{
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/* for 32 bit operand size mode */
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Bit32u op1_32, op2_32, sum_32;
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op1_32 = EAX;
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op2_32 = i->Id;
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sum_32 = op1_32 ^ op2_32;
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/* now write sum back to destination */
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EAX = sum_32;
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SET_FLAGS_OSZAPC_32(op1_32, op2_32, sum_32, BX_INSTR_XOR32);
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}
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void
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BX_CPU_C::XOR_EdId(BxInstruction_t *i)
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{
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Bit32u op2_32, op1_32, result_32;
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op2_32 = i->Id;
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/* op1_32 is a register or memory reference */
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if (i->mod == 0xc0) {
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op1_32 = BX_READ_32BIT_REG(i->rm);
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}
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else {
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/* pointer, segment address pair */
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read_RMW_virtual_dword(i->seg, i->rm_addr, &op1_32);
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}
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result_32 = op1_32 ^ op2_32;
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/* now write result back to destination */
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if (i->mod == 0xc0) {
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BX_WRITE_32BIT_REG(i->rm, result_32);
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}
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else {
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Write_RMW_virtual_dword(result_32);
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}
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SET_FLAGS_OSZAPC_32(op1_32, op2_32, result_32, BX_INSTR_XOR32);
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}
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void
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BX_CPU_C::OR_EdId(BxInstruction_t *i)
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{
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Bit32u op2_32, op1_32, result_32;
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op2_32 = i->Id;
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/* op1_32 is a register or memory reference */
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if (i->mod == 0xc0) {
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op1_32 = BX_READ_32BIT_REG(i->rm);
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}
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else {
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/* pointer, segment address pair */
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read_RMW_virtual_dword(i->seg, i->rm_addr, &op1_32);
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}
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result_32 = op1_32 | op2_32;
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/* now write result back to destination */
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if (i->mod == 0xc0) {
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BX_WRITE_32BIT_REG(i->rm, result_32);
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}
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else {
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Write_RMW_virtual_dword(result_32);
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}
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SET_FLAGS_OSZAPC_32(op1_32, op2_32, result_32, BX_INSTR_OR32);
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}
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void
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BX_CPU_C::NOT_Ed(BxInstruction_t *i)
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{
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Bit32u op1_32, result_32;
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/* op1 is a register or memory reference */
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if (i->mod == 0xc0) {
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op1_32 = BX_READ_32BIT_REG(i->rm);
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}
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else {
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/* pointer, segment address pair */
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read_RMW_virtual_dword(i->seg, i->rm_addr, &op1_32);
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}
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result_32 = ~op1_32;
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/* now write result back to destination */
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if (i->mod == 0xc0) {
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BX_WRITE_32BIT_REG(i->rm, result_32);
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}
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else {
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Write_RMW_virtual_dword(result_32);
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}
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}
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void
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BX_CPU_C::OR_EdGd(BxInstruction_t *i)
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{
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Bit32u op2_32, op1_32, result_32;
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/* op2_32 is a register, op2_addr is an index of a register */
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op2_32 = BX_READ_32BIT_REG(i->nnn);
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/* op1_32 is a register or memory reference */
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if (i->mod == 0xc0) {
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op1_32 = BX_READ_32BIT_REG(i->rm);
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}
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else {
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/* pointer, segment address pair */
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read_RMW_virtual_dword(i->seg, i->rm_addr, &op1_32);
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}
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result_32 = op1_32 | op2_32;
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/* now write result back to destination */
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if (i->mod == 0xc0) {
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BX_WRITE_32BIT_REG(i->rm, result_32);
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}
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else {
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Write_RMW_virtual_dword(result_32);
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}
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SET_FLAGS_OSZAPC_32(op1_32, op2_32, result_32, BX_INSTR_OR32);
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}
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void
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BX_CPU_C::OR_GdEd(BxInstruction_t *i)
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{
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Bit32u op1_32, op2_32, result_32;
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op1_32 = BX_READ_32BIT_REG(i->nnn);
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/* op2_32 is a register or memory reference */
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if (i->mod == 0xc0) {
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op2_32 = BX_READ_32BIT_REG(i->rm);
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}
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else {
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/* pointer, segment address pair */
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read_virtual_dword(i->seg, i->rm_addr, &op2_32);
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}
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result_32 = op1_32 | op2_32;
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/* now write result back to destination */
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BX_WRITE_32BIT_REG(i->nnn, result_32);
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SET_FLAGS_OSZAPC_32(op1_32, op2_32, result_32, BX_INSTR_OR32);
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}
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void
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BX_CPU_C::OR_EAXId(BxInstruction_t *i)
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{
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Bit32u op1_32, op2_32, sum_32;
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op1_32 = EAX;
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op2_32 = i->Id;
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sum_32 = op1_32 | op2_32;
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/* now write sum back to destination */
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EAX = sum_32;
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SET_FLAGS_OSZAPC_32(op1_32, op2_32, sum_32, BX_INSTR_OR32);
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}
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void
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BX_CPU_C::AND_EdGd(BxInstruction_t *i)
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{
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Bit32u op2_32, op1_32, result_32;
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/* op2_32 is a register, op2_addr is an index of a register */
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op2_32 = BX_READ_32BIT_REG(i->nnn);
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/* op1_32 is a register or memory reference */
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if (i->mod == 0xc0) {
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op1_32 = BX_READ_32BIT_REG(i->rm);
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}
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else {
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/* pointer, segment address pair */
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read_RMW_virtual_dword(i->seg, i->rm_addr, &op1_32);
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}
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result_32 = op1_32 & op2_32;
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/* now write result back to destination */
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if (i->mod == 0xc0) {
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BX_WRITE_32BIT_REG(i->rm, result_32);
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}
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else {
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Write_RMW_virtual_dword(result_32);
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}
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SET_FLAGS_OSZAPC_32(op1_32, op2_32, result_32, BX_INSTR_AND32);
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}
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void
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BX_CPU_C::AND_GdEd(BxInstruction_t *i)
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{
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Bit32u op1_32, op2_32, result_32;
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op1_32 = BX_READ_32BIT_REG(i->nnn);
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/* op2_32 is a register or memory reference */
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if (i->mod == 0xc0) {
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op2_32 = BX_READ_32BIT_REG(i->rm);
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}
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else {
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/* pointer, segment address pair */
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read_virtual_dword(i->seg, i->rm_addr, &op2_32);
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}
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result_32 = op1_32 & op2_32;
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/* now write result back to destination */
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BX_WRITE_32BIT_REG(i->nnn, result_32);
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SET_FLAGS_OSZAPC_32(op1_32, op2_32, result_32, BX_INSTR_AND32);
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}
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void
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BX_CPU_C::AND_EAXId(BxInstruction_t *i)
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{
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Bit32u op1_32, op2_32, sum_32;
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op1_32 = EAX;
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op2_32 = i->Id;
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sum_32 = op1_32 & op2_32;
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/* now write sum back to destination */
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EAX = sum_32;
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SET_FLAGS_OSZAPC_32(op1_32, op2_32, sum_32, BX_INSTR_AND32);
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}
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void
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BX_CPU_C::AND_EdId(BxInstruction_t *i)
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{
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Bit32u op2_32, op1_32, result_32;
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op2_32 = i->Id;
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/* op1_32 is a register or memory reference */
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if (i->mod == 0xc0) {
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op1_32 = BX_READ_32BIT_REG(i->rm);
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}
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else {
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/* pointer, segment address pair */
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read_RMW_virtual_dword(i->seg, i->rm_addr, &op1_32);
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}
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result_32 = op1_32 & op2_32;
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/* now write result back to destination */
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if (i->mod == 0xc0) {
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BX_WRITE_32BIT_REG(i->rm, result_32);
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}
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else {
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Write_RMW_virtual_dword(result_32);
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}
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SET_FLAGS_OSZAPC_32(op1_32, op2_32, result_32, BX_INSTR_AND32);
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}
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void
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BX_CPU_C::TEST_EdGd(BxInstruction_t *i)
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{
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Bit32u op2_32, op1_32, result_32;
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/* op2_32 is a register, op2_addr is an index of a register */
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op2_32 = BX_READ_32BIT_REG(i->nnn);
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/* op1_32 is a register or memory reference */
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if (i->mod == 0xc0) {
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op1_32 = BX_READ_32BIT_REG(i->rm);
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}
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else {
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/* pointer, segment address pair */
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read_virtual_dword(i->seg, i->rm_addr, &op1_32);
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}
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result_32 = op1_32 & op2_32;
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SET_FLAGS_OSZAPC_32(op1_32, op2_32, result_32, BX_INSTR_TEST32);
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}
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void
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BX_CPU_C::TEST_EAXId(BxInstruction_t *i)
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{
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Bit32u op2_32, op1_32, result_32;
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/* op1 is EAX register */
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op1_32 = EAX;
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/* op2 is imm32 */
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op2_32 = i->Id;
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result_32 = op1_32 & op2_32;
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SET_FLAGS_OSZAPC_32(op1_32, op2_32, result_32, BX_INSTR_TEST32);
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}
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void
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BX_CPU_C::TEST_EdId(BxInstruction_t *i)
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{
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Bit32u op2_32, op1_32, result_32;
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/* op2 is imm32 */
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op2_32 = i->Id;
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/* op1_32 is a register or memory reference */
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if (i->mod == 0xc0) {
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op1_32 = BX_READ_32BIT_REG(i->rm);
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}
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else {
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/* pointer, segment address pair */
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read_virtual_dword(i->seg, i->rm_addr, &op1_32);
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}
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result_32 = op1_32 & op2_32;
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SET_FLAGS_OSZAPC_32(op1_32, op2_32, result_32, BX_INSTR_TEST32);
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}
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