6843c3dfe8
Essentially, when I coded a few of the instructions to use asm()s for acceleration of the eflags, I got lazy and only used the asm() to compute eflags and let the normal C operation do the actual operation. Jas's patch, moved the asm()s such that they now do the work of the operation as well. The patches look great. The code reads a lot better as well. Further work can be done to give the compiler more options with register scheduling.
553 lines
12 KiB
C++
553 lines
12 KiB
C++
/////////////////////////////////////////////////////////////////////////
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// $Id: logical16.cc,v 1.12 2002-09-28 01:48:17 kevinlawton Exp $
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/////////////////////////////////////////////////////////////////////////
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//
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// Copyright (C) 2001 MandrakeSoft S.A.
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//
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// MandrakeSoft S.A.
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// 43, rue d'Aboukir
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// 75002 Paris - France
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// http://www.linux-mandrake.com/
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// http://www.mandrakesoft.com/
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//
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// This library is free software; you can redistribute it and/or
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// modify it under the terms of the GNU Lesser General Public
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// License as published by the Free Software Foundation; either
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// version 2 of the License, or (at your option) any later version.
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//
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// This library is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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// Lesser General Public License for more details.
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//
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// You should have received a copy of the GNU Lesser General Public
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// License along with this library; if not, write to the Free Software
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// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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#define NEED_CPU_REG_SHORTCUTS 1
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#include "bochs.h"
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#define LOG_THIS BX_CPU_THIS_PTR
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void
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BX_CPU_C::XOR_EwGw(bxInstruction_c *i)
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{
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Bit16u op2_16, op1_16, result_16;
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/* op2_16 is a register, op2_addr is an index of a register */
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op2_16 = BX_READ_16BIT_REG(i->nnn());
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/* op1_16 is a register or memory reference */
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if (i->modC0()) {
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op1_16 = BX_READ_16BIT_REG(i->rm());
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}
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else {
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/* pointer, segment address pair */
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read_RMW_virtual_word(i->seg(), RMAddr(i), &op1_16);
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}
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result_16 = op1_16 ^ op2_16;
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/* now write result back to destination */
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if (i->modC0()) {
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BX_WRITE_16BIT_REG(i->rm(), result_16);
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}
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else {
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Write_RMW_virtual_word(result_16);
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}
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SET_FLAGS_OSZAPC_16(op1_16, op2_16, result_16, BX_INSTR_XOR16);
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}
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void
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BX_CPU_C::XOR_GwEw(bxInstruction_c *i)
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{
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Bit16u op1_16, op2_16, result_16;
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op1_16 = BX_READ_16BIT_REG(i->nnn());
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/* op2_16 is a register or memory reference */
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if (i->modC0()) {
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op2_16 = BX_READ_16BIT_REG(i->rm());
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}
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else {
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/* pointer, segment address pair */
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read_virtual_word(i->seg(), RMAddr(i), &op2_16);
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}
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result_16 = op1_16 ^ op2_16;
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/* now write result back to destination */
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BX_WRITE_16BIT_REG(i->nnn(), result_16);
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SET_FLAGS_OSZAPC_16(op1_16, op2_16, result_16, BX_INSTR_XOR16);
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}
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void
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BX_CPU_C::XOR_AXIw(bxInstruction_c *i)
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{
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Bit16u op1_16, op2_16, sum_16;
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op1_16 = AX;
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op2_16 = i->Iw();
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sum_16 = op1_16 ^ op2_16;
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/* now write sum back to destination */
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AX = sum_16;
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SET_FLAGS_OSZAPC_16(op1_16, op2_16, sum_16, BX_INSTR_XOR16);
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}
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void
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BX_CPU_C::XOR_EwIw(bxInstruction_c *i)
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{
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Bit16u op2_16, op1_16, result_16;
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op2_16 = i->Iw();
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/* op1_16 is a register or memory reference */
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if (i->modC0()) {
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op1_16 = BX_READ_16BIT_REG(i->rm());
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}
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else {
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/* pointer, segment address pair */
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read_RMW_virtual_word(i->seg(), RMAddr(i), &op1_16);
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}
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result_16 = op1_16 ^ op2_16;
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/* now write result back to destination */
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if (i->modC0()) {
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BX_WRITE_16BIT_REG(i->rm(), result_16);
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}
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else {
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Write_RMW_virtual_word(result_16);
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}
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SET_FLAGS_OSZAPC_16(op1_16, op2_16, result_16, BX_INSTR_XOR16);
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}
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void
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BX_CPU_C::OR_EwIw(bxInstruction_c *i)
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{
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Bit16u op2_16, op1_16, result_16;
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op2_16 = i->Iw();
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/* op1_16 is a register or memory reference */
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if (i->modC0()) {
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op1_16 = BX_READ_16BIT_REG(i->rm());
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}
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else {
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/* pointer, segment address pair */
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read_RMW_virtual_word(i->seg(), RMAddr(i), &op1_16);
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}
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result_16 = op1_16 | op2_16;
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/* now write result back to destination */
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if (i->modC0()) {
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BX_WRITE_16BIT_REG(i->rm(), result_16);
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}
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else {
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Write_RMW_virtual_word(result_16);
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}
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SET_FLAGS_OSZAPC_16(op1_16, op2_16, result_16, BX_INSTR_OR16);
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}
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void
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BX_CPU_C::NOT_Ew(bxInstruction_c *i)
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{
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Bit16u op1_16, result_16;
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/* op1 is a register or memory reference */
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if (i->modC0()) {
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op1_16 = BX_READ_16BIT_REG(i->rm());
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}
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else {
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/* pointer, segment address pair */
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read_RMW_virtual_word(i->seg(), RMAddr(i), &op1_16);
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}
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result_16 = ~op1_16;
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/* now write result back to destination */
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if (i->modC0()) {
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BX_WRITE_16BIT_REG(i->rm(), result_16);
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}
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else {
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Write_RMW_virtual_word(result_16);
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}
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}
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void
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BX_CPU_C::OR_EwGw(bxInstruction_c *i)
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{
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Bit16u op2_16, op1_16, result_16;
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/* op2_16 is a register, op2_addr is an index of a register */
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op2_16 = BX_READ_16BIT_REG(i->nnn());
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/* op1_16 is a register or memory reference */
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if (i->modC0()) {
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op1_16 = BX_READ_16BIT_REG(i->rm());
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}
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else {
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/* pointer, segment address pair */
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read_RMW_virtual_word(i->seg(), RMAddr(i), &op1_16);
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}
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result_16 = op1_16 | op2_16;
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/* now write result back to destination */
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if (i->modC0()) {
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BX_WRITE_16BIT_REG(i->rm(), result_16);
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}
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else {
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Write_RMW_virtual_word(result_16);
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}
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SET_FLAGS_OSZAPC_16(op1_16, op2_16, result_16, BX_INSTR_OR16);
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}
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void
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BX_CPU_C::OR_GwEw(bxInstruction_c *i)
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{
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Bit16u op1_16, op2_16, result_16;
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op1_16 = BX_READ_16BIT_REG(i->nnn());
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/* op2_16 is a register or memory reference */
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if (i->modC0()) {
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op2_16 = BX_READ_16BIT_REG(i->rm());
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}
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else {
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/* pointer, segment address pair */
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read_virtual_word(i->seg(), RMAddr(i), &op2_16);
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}
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result_16 = op1_16 | op2_16;
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/* now write result back to destination */
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BX_WRITE_16BIT_REG(i->nnn(), result_16);
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SET_FLAGS_OSZAPC_16(op1_16, op2_16, result_16, BX_INSTR_OR16);
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}
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void
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BX_CPU_C::OR_AXIw(bxInstruction_c *i)
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{
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Bit16u op1_16, op2_16, sum_16;
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op1_16 = AX;
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op2_16 = i->Iw();
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sum_16 = op1_16 | op2_16;
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/* now write sum back to destination */
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AX = sum_16;
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SET_FLAGS_OSZAPC_16(op1_16, op2_16, sum_16, BX_INSTR_OR16);
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}
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void
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BX_CPU_C::AND_EwGw(bxInstruction_c *i)
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{
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Bit16u op2_16, op1_16, result_16;
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op2_16 = BX_READ_16BIT_REG(i->nnn());
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if (i->modC0()) {
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op1_16 = BX_READ_16BIT_REG(i->rm());
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}
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else {
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read_RMW_virtual_word(i->seg(), RMAddr(i), &op1_16);
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}
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#if (defined(__i386__) && defined(__GNUC__) && BX_SupportHostAsms)
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Bit32u flags32;
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asm (
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"andw %3, %1\n\t"
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"pushfl \n\t"
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"popl %0"
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: "=g" (flags32), "=r" (result_16)
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: "1" (op1_16), "g" (op2_16)
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: "cc"
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);
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BX_CPU_THIS_PTR eflags.val32 =
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(BX_CPU_THIS_PTR eflags.val32 & ~EFlagsOSZAPCMask) |
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(flags32 & EFlagsOSZAPCMask);
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BX_CPU_THIS_PTR lf_flags_status = 0;
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#else
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result_16 = op1_16 & op2_16;
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#endif
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if (i->modC0()) {
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BX_WRITE_16BIT_REG(i->rm(), result_16);
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}
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else {
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Write_RMW_virtual_word(result_16);
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}
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#if !(defined(__i386__) && defined(__GNUC__) && BX_SupportHostAsms)
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SET_FLAGS_OSZAPC_16(op1_16, op2_16, result_16, BX_INSTR_AND16);
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#endif
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}
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void
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BX_CPU_C::AND_GwEw(bxInstruction_c *i)
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{
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Bit16u op1_16, op2_16, result_16;
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op1_16 = BX_READ_16BIT_REG(i->nnn());
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if (i->modC0()) {
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op2_16 = BX_READ_16BIT_REG(i->rm());
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}
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else {
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read_virtual_word(i->seg(), RMAddr(i), &op2_16);
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}
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#if (defined(__i386__) && defined(__GNUC__) && BX_SupportHostAsms)
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Bit32u flags32;
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asm (
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"andw %3, %1\n\t"
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"pushfl \n\t"
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"popl %0"
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: "=g" (flags32), "=r" (result_16)
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: "1" (op1_16), "g" (op2_16)
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: "cc"
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);
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BX_CPU_THIS_PTR eflags.val32 =
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(BX_CPU_THIS_PTR eflags.val32 & ~EFlagsOSZAPCMask) |
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(flags32 & EFlagsOSZAPCMask);
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BX_CPU_THIS_PTR lf_flags_status = 0;
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#else
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result_16 = op1_16 & op2_16;
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#endif
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BX_WRITE_16BIT_REG(i->nnn(), result_16);
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#if !(defined(__i386__) && defined(__GNUC__) && BX_SupportHostAsms)
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SET_FLAGS_OSZAPC_16(op1_16, op2_16, result_16, BX_INSTR_AND16);
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#endif
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}
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void
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BX_CPU_C::AND_AXIw(bxInstruction_c *i)
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{
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Bit16u op1_16, op2_16, result_16;
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op1_16 = AX;
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op2_16 = i->Iw();
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#if (defined(__i386__) && defined(__GNUC__) && BX_SupportHostAsms)
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Bit32u flags32;
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asm (
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"andw %3, %1\n\t"
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"pushfl \n\t"
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"popl %0"
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: "=g" (flags32), "=r" (result_16)
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: "1" (op1_16), "g" (op2_16)
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: "cc"
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);
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BX_CPU_THIS_PTR eflags.val32 =
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(BX_CPU_THIS_PTR eflags.val32 & ~EFlagsOSZAPCMask) |
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(flags32 & EFlagsOSZAPCMask);
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BX_CPU_THIS_PTR lf_flags_status = 0;
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#else
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result_16 = op1_16 & op2_16;
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#endif
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AX = result_16;
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#if !(defined(__i386__) && defined(__GNUC__) && BX_SupportHostAsms)
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SET_FLAGS_OSZAPC_16(op1_16, op2_16, result_16, BX_INSTR_AND16);
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#endif
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}
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void
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BX_CPU_C::AND_EwIw(bxInstruction_c *i)
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{
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Bit16u op2_16, op1_16, result_16;
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op2_16 = i->Iw();
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if (i->modC0()) {
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op1_16 = BX_READ_16BIT_REG(i->rm());
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}
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else {
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read_RMW_virtual_word(i->seg(), RMAddr(i), &op1_16);
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}
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#if (defined(__i386__) && defined(__GNUC__) && BX_SupportHostAsms)
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Bit32u flags32;
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asm (
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"andw %3, %1\n\t"
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"pushfl \n\t"
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"popl %0"
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: "=g" (flags32), "=r" (result_16)
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: "1" (op1_16), "g" (op2_16)
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: "cc"
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);
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BX_CPU_THIS_PTR eflags.val32 =
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(BX_CPU_THIS_PTR eflags.val32 & ~EFlagsOSZAPCMask) |
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(flags32 & EFlagsOSZAPCMask);
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BX_CPU_THIS_PTR lf_flags_status = 0;
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#else
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result_16 = op1_16 & op2_16;
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#endif
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if (i->modC0()) {
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BX_WRITE_16BIT_REG(i->rm(), result_16);
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}
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else {
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Write_RMW_virtual_word(result_16);
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}
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#if !(defined(__i386__) && defined(__GNUC__) && BX_SupportHostAsms)
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SET_FLAGS_OSZAPC_16(op1_16, op2_16, result_16, BX_INSTR_AND16);
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#endif
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}
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void
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BX_CPU_C::TEST_EwGw(bxInstruction_c *i)
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{
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Bit16u op2_16, op1_16;
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/* op2_16 is a register, op2_addr is an index of a register */
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op2_16 = BX_READ_16BIT_REG(i->nnn());
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/* op1_16 is a register or memory reference */
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if (i->modC0()) {
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op1_16 = BX_READ_16BIT_REG(i->rm());
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}
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else {
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/* pointer, segment address pair */
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read_virtual_word(i->seg(), RMAddr(i), &op1_16);
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}
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#if (defined(__i386__) && defined(__GNUC__) && BX_SupportHostAsms)
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Bit32u flags32;
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asm (
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"testw %2, %1\n\t"
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"pushfl \n\t"
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"popl %0"
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: "=g" (flags32)
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: "r" (op1_16), "g" (op2_16)
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: "cc"
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);
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BX_CPU_THIS_PTR eflags.val32 =
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(BX_CPU_THIS_PTR eflags.val32 & ~EFlagsOSZAPCMask) |
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(flags32 & EFlagsOSZAPCMask);
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BX_CPU_THIS_PTR lf_flags_status = 0;
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#else
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Bit16u result_16;
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result_16 = op1_16 & op2_16;
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SET_FLAGS_OSZAPC_16(op1_16, op2_16, result_16, BX_INSTR_TEST16);
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#endif
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}
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void
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BX_CPU_C::TEST_AXIw(bxInstruction_c *i)
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{
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Bit16u op2_16, op1_16;
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op1_16 = AX;
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/* op2_16 is imm16 */
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op2_16 = i->Iw();
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#if (defined(__i386__) && defined(__GNUC__) && BX_SupportHostAsms)
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Bit32u flags32;
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asm (
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"testw %2, %1\n\t"
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"pushfl \n\t"
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"popl %0"
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: "=g" (flags32)
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: "r" (op1_16), "g" (op2_16)
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: "cc"
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);
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BX_CPU_THIS_PTR eflags.val32 =
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(BX_CPU_THIS_PTR eflags.val32 & ~EFlagsOSZAPCMask) |
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(flags32 & EFlagsOSZAPCMask);
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BX_CPU_THIS_PTR lf_flags_status = 0;
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#else
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Bit16u result_16;
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result_16 = op1_16 & op2_16;
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SET_FLAGS_OSZAPC_16(op1_16, op2_16, result_16, BX_INSTR_TEST16);
|
|
#endif
|
|
}
|
|
|
|
|
|
void
|
|
BX_CPU_C::TEST_EwIw(bxInstruction_c *i)
|
|
{
|
|
Bit16u op2_16, op1_16;
|
|
|
|
op2_16 = i->Iw();
|
|
|
|
/* op1_16 is a register or memory reference */
|
|
if (i->modC0()) {
|
|
op1_16 = BX_READ_16BIT_REG(i->rm());
|
|
}
|
|
else {
|
|
/* pointer, segment address pair */
|
|
read_virtual_word(i->seg(), RMAddr(i), &op1_16);
|
|
}
|
|
|
|
#if (defined(__i386__) && defined(__GNUC__) && BX_SupportHostAsms)
|
|
Bit32u flags32;
|
|
asm (
|
|
"testw %2, %1\n\t"
|
|
"pushfl \n\t"
|
|
"popl %0"
|
|
: "=g" (flags32)
|
|
: "r" (op1_16), "g" (op2_16)
|
|
: "cc"
|
|
);
|
|
BX_CPU_THIS_PTR eflags.val32 =
|
|
(BX_CPU_THIS_PTR eflags.val32 & ~EFlagsOSZAPCMask) |
|
|
(flags32 & EFlagsOSZAPCMask);
|
|
BX_CPU_THIS_PTR lf_flags_status = 0;
|
|
#else
|
|
Bit16u result_16;
|
|
result_16 = op1_16 & op2_16;
|
|
|
|
SET_FLAGS_OSZAPC_16(op1_16, op2_16, result_16, BX_INSTR_TEST16);
|
|
#endif
|
|
}
|