6723ca9bf4
with accessors. Had to touch a number of files to update the access using the new accessors. Moved rm_addr to the CPU structure, to slim down bxInstruction_c and to prevent future instruction caching from getting sprayed with writes to individual rm_addr fields. There only needs to be one. Though need to deal with instructions which have static non-modrm addresses, but which are using rm_addr since that will change. bxInstruction_c is down to about 40 bytes now. Trying to get down to 24 bytes.
452 lines
10 KiB
C++
452 lines
10 KiB
C++
/////////////////////////////////////////////////////////////////////////
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// $Id: logical32.cc,v 1.9 2002-09-18 05:36:48 kevinlawton Exp $
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/////////////////////////////////////////////////////////////////////////
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//
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// Copyright (C) 2001 MandrakeSoft S.A.
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//
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// MandrakeSoft S.A.
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// 43, rue d'Aboukir
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// 75002 Paris - France
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// http://www.linux-mandrake.com/
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// http://www.mandrakesoft.com/
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//
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// This library is free software; you can redistribute it and/or
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// modify it under the terms of the GNU Lesser General Public
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// License as published by the Free Software Foundation; either
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// version 2 of the License, or (at your option) any later version.
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//
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// This library is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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// Lesser General Public License for more details.
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//
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// You should have received a copy of the GNU Lesser General Public
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// License along with this library; if not, write to the Free Software
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// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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#define NEED_CPU_REG_SHORTCUTS 1
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#include "bochs.h"
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#define LOG_THIS BX_CPU_THIS_PTR
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void
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BX_CPU_C::XOR_EdGd(bxInstruction_c *i)
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{
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/* for 32 bit operand size mode */
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Bit32u op2_32, op1_32, result_32;
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/* op2_32 is a register, op2_addr is an index of a register */
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op2_32 = BX_READ_32BIT_REG(i->nnn());
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/* op1_32 is a register or memory reference */
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if (i->mod() == 0xc0) {
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op1_32 = BX_READ_32BIT_REG(i->rm());
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}
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else {
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/* pointer, segment address pair */
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read_RMW_virtual_dword(i->seg(), RMAddr(i), &op1_32);
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}
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result_32 = op1_32 ^ op2_32;
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/* now write result back to destination */
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if (i->mod() == 0xc0) {
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BX_WRITE_32BIT_REGZ(i->rm(), result_32);
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}
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else {
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Write_RMW_virtual_dword(result_32);
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}
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SET_FLAGS_OSZAPC_32(op1_32, op2_32, result_32, BX_INSTR_XOR32);
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}
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void
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BX_CPU_C::XOR_GdEd(bxInstruction_c *i)
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{
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/* for 32 bit operand size mode */
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Bit32u op1_32, op2_32, result_32;
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op1_32 = BX_READ_32BIT_REG(i->nnn());
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/* op2_32 is a register or memory reference */
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if (i->mod() == 0xc0) {
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op2_32 = BX_READ_32BIT_REG(i->rm());
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}
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else {
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/* pointer, segment address pair */
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read_virtual_dword(i->seg(), RMAddr(i), &op2_32);
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}
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result_32 = op1_32 ^ op2_32;
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/* now write result back to destination */
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BX_WRITE_32BIT_REGZ(i->nnn(), result_32);
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SET_FLAGS_OSZAPC_32(op1_32, op2_32, result_32, BX_INSTR_XOR32);
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}
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void
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BX_CPU_C::XOR_EAXId(bxInstruction_c *i)
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{
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/* for 32 bit operand size mode */
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Bit32u op1_32, op2_32, sum_32;
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op1_32 = EAX;
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op2_32 = i->Id();
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sum_32 = op1_32 ^ op2_32;
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/* now write sum back to destination */
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#if BX_SUPPORT_X86_64
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RAX = sum_32;
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#else
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EAX = sum_32;
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#endif
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SET_FLAGS_OSZAPC_32(op1_32, op2_32, sum_32, BX_INSTR_XOR32);
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}
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void
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BX_CPU_C::XOR_EdId(bxInstruction_c *i)
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{
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Bit32u op2_32, op1_32, result_32;
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op2_32 = i->Id();
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/* op1_32 is a register or memory reference */
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if (i->mod() == 0xc0) {
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op1_32 = BX_READ_32BIT_REG(i->rm());
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}
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else {
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/* pointer, segment address pair */
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read_RMW_virtual_dword(i->seg(), RMAddr(i), &op1_32);
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}
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result_32 = op1_32 ^ op2_32;
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/* now write result back to destination */
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if (i->mod() == 0xc0) {
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BX_WRITE_32BIT_REGZ(i->rm(), result_32);
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}
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else {
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Write_RMW_virtual_dword(result_32);
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}
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SET_FLAGS_OSZAPC_32(op1_32, op2_32, result_32, BX_INSTR_XOR32);
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}
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void
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BX_CPU_C::OR_EdId(bxInstruction_c *i)
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{
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Bit32u op2_32, op1_32, result_32;
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op2_32 = i->Id();
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/* op1_32 is a register or memory reference */
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if (i->mod() == 0xc0) {
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op1_32 = BX_READ_32BIT_REG(i->rm());
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}
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else {
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/* pointer, segment address pair */
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read_RMW_virtual_dword(i->seg(), RMAddr(i), &op1_32);
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}
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result_32 = op1_32 | op2_32;
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/* now write result back to destination */
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if (i->mod() == 0xc0) {
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BX_WRITE_32BIT_REGZ(i->rm(), result_32);
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}
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else {
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Write_RMW_virtual_dword(result_32);
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}
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SET_FLAGS_OSZAPC_32(op1_32, op2_32, result_32, BX_INSTR_OR32);
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}
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void
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BX_CPU_C::NOT_Ed(bxInstruction_c *i)
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{
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Bit32u op1_32, result_32;
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/* op1 is a register or memory reference */
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if (i->mod() == 0xc0) {
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op1_32 = BX_READ_32BIT_REG(i->rm());
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}
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else {
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/* pointer, segment address pair */
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read_RMW_virtual_dword(i->seg(), RMAddr(i), &op1_32);
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}
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result_32 = ~op1_32;
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/* now write result back to destination */
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if (i->mod() == 0xc0) {
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BX_WRITE_32BIT_REGZ(i->rm(), result_32);
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}
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else {
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Write_RMW_virtual_dword(result_32);
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}
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}
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void
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BX_CPU_C::OR_EdGd(bxInstruction_c *i)
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{
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Bit32u op2_32, op1_32, result_32;
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/* op2_32 is a register, op2_addr is an index of a register */
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op2_32 = BX_READ_32BIT_REG(i->nnn());
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/* op1_32 is a register or memory reference */
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if (i->mod() == 0xc0) {
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op1_32 = BX_READ_32BIT_REG(i->rm());
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}
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else {
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/* pointer, segment address pair */
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read_RMW_virtual_dword(i->seg(), RMAddr(i), &op1_32);
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}
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result_32 = op1_32 | op2_32;
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/* now write result back to destination */
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if (i->mod() == 0xc0) {
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BX_WRITE_32BIT_REGZ(i->rm(), result_32);
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}
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else {
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Write_RMW_virtual_dword(result_32);
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}
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SET_FLAGS_OSZAPC_32(op1_32, op2_32, result_32, BX_INSTR_OR32);
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}
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void
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BX_CPU_C::OR_GdEd(bxInstruction_c *i)
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{
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Bit32u op1_32, op2_32, result_32;
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op1_32 = BX_READ_32BIT_REG(i->nnn());
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/* op2_32 is a register or memory reference */
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if (i->mod() == 0xc0) {
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op2_32 = BX_READ_32BIT_REG(i->rm());
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}
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else {
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/* pointer, segment address pair */
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read_virtual_dword(i->seg(), RMAddr(i), &op2_32);
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}
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result_32 = op1_32 | op2_32;
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/* now write result back to destination */
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BX_WRITE_32BIT_REGZ(i->nnn(), result_32);
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SET_FLAGS_OSZAPC_32(op1_32, op2_32, result_32, BX_INSTR_OR32);
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}
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void
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BX_CPU_C::OR_EAXId(bxInstruction_c *i)
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{
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Bit32u op1_32, op2_32, sum_32;
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op1_32 = EAX;
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op2_32 = i->Id();
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sum_32 = op1_32 | op2_32;
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/* now write sum back to destination */
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#if BX_SUPPORT_X86_64
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RAX = sum_32;
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#else
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EAX = sum_32;
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#endif
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SET_FLAGS_OSZAPC_32(op1_32, op2_32, sum_32, BX_INSTR_OR32);
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}
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void
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BX_CPU_C::AND_EdGd(bxInstruction_c *i)
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{
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Bit32u op2_32, op1_32, result_32;
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/* op2_32 is a register, op2_addr is an index of a register */
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op2_32 = BX_READ_32BIT_REG(i->nnn());
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/* op1_32 is a register or memory reference */
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if (i->mod() == 0xc0) {
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op1_32 = BX_READ_32BIT_REG(i->rm());
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}
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else {
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/* pointer, segment address pair */
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read_RMW_virtual_dword(i->seg(), RMAddr(i), &op1_32);
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}
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result_32 = op1_32 & op2_32;
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/* now write result back to destination */
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if (i->mod() == 0xc0) {
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BX_WRITE_32BIT_REGZ(i->rm(), result_32);
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}
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else {
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Write_RMW_virtual_dword(result_32);
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}
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SET_FLAGS_OSZAPC_32(op1_32, op2_32, result_32, BX_INSTR_AND32);
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}
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void
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BX_CPU_C::AND_GdEd(bxInstruction_c *i)
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{
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Bit32u op1_32, op2_32, result_32;
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op1_32 = BX_READ_32BIT_REG(i->nnn());
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/* op2_32 is a register or memory reference */
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if (i->mod() == 0xc0) {
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op2_32 = BX_READ_32BIT_REG(i->rm());
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}
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else {
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/* pointer, segment address pair */
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read_virtual_dword(i->seg(), RMAddr(i), &op2_32);
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}
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result_32 = op1_32 & op2_32;
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/* now write result back to destination */
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BX_WRITE_32BIT_REGZ(i->nnn(), result_32);
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SET_FLAGS_OSZAPC_32(op1_32, op2_32, result_32, BX_INSTR_AND32);
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}
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void
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BX_CPU_C::AND_EAXId(bxInstruction_c *i)
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{
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Bit32u op1_32, op2_32, sum_32;
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op1_32 = EAX;
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op2_32 = i->Id();
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sum_32 = op1_32 & op2_32;
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/* now write sum back to destination */
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#if BX_SUPPORT_X86_64
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RAX = sum_32;
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#else
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EAX = sum_32;
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#endif
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SET_FLAGS_OSZAPC_32(op1_32, op2_32, sum_32, BX_INSTR_AND32);
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}
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void
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BX_CPU_C::AND_EdId(bxInstruction_c *i)
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{
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Bit32u op2_32, op1_32, result_32;
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op2_32 = i->Id();
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/* op1_32 is a register or memory reference */
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if (i->mod() == 0xc0) {
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op1_32 = BX_READ_32BIT_REG(i->rm());
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}
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else {
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/* pointer, segment address pair */
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read_RMW_virtual_dword(i->seg(), RMAddr(i), &op1_32);
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}
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result_32 = op1_32 & op2_32;
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/* now write result back to destination */
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if (i->mod() == 0xc0) {
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BX_WRITE_32BIT_REGZ(i->rm(), result_32);
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}
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else {
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Write_RMW_virtual_dword(result_32);
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}
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SET_FLAGS_OSZAPC_32(op1_32, op2_32, result_32, BX_INSTR_AND32);
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}
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void
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BX_CPU_C::TEST_EdGd(bxInstruction_c *i)
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{
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Bit32u op2_32, op1_32, result_32;
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/* op2_32 is a register, op2_addr is an index of a register */
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op2_32 = BX_READ_32BIT_REG(i->nnn());
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/* op1_32 is a register or memory reference */
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if (i->mod() == 0xc0) {
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op1_32 = BX_READ_32BIT_REG(i->rm());
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}
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else {
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/* pointer, segment address pair */
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read_virtual_dword(i->seg(), RMAddr(i), &op1_32);
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}
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result_32 = op1_32 & op2_32;
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SET_FLAGS_OSZAPC_32(op1_32, op2_32, result_32, BX_INSTR_TEST32);
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}
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void
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BX_CPU_C::TEST_EAXId(bxInstruction_c *i)
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{
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Bit32u op2_32, op1_32, result_32;
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/* op1 is EAX register */
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op1_32 = EAX;
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/* op2 is imm32 */
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op2_32 = i->Id();
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result_32 = op1_32 & op2_32;
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SET_FLAGS_OSZAPC_32(op1_32, op2_32, result_32, BX_INSTR_TEST32);
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}
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void
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BX_CPU_C::TEST_EdId(bxInstruction_c *i)
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{
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Bit32u op2_32, op1_32, result_32;
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/* op2 is imm32 */
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op2_32 = i->Id();
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/* op1_32 is a register or memory reference */
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if (i->mod() == 0xc0) {
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op1_32 = BX_READ_32BIT_REG(i->rm());
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}
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else {
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/* pointer, segment address pair */
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read_virtual_dword(i->seg(), RMAddr(i), &op1_32);
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}
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result_32 = op1_32 & op2_32;
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SET_FLAGS_OSZAPC_32(op1_32, op2_32, result_32, BX_INSTR_TEST32);
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}
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