436 lines
13 KiB
C++
436 lines
13 KiB
C++
/////////////////////////////////////////////////////////////////////////
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// $Id$
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/////////////////////////////////////////////////////////////////////////
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//
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// Copyright (C) 2002-2013 The Bochs Project
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//
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// This library is free software; you can redistribute it and/or
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// modify it under the terms of the GNU Lesser General Public
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// License as published by the Free Software Foundation; either
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// version 2 of the License, or (at your option) any later version.
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//
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// This library is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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// Lesser General Public License for more details.
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//
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// You should have received a copy of the GNU Lesser General Public
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// License along with this library; if not, write to the Free Software
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// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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// PCI host bridge support
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// i430FX - TSC/TDP
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// i440FX - PMC/DBX
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// Define BX_PLUGGABLE in files that can be compiled into plugins. For
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// platforms that require a special tag on exported symbols, BX_PLUGGABLE
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// is used to know when we are exporting symbols and when we are importing.
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#define BX_PLUGGABLE
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#include "iodev.h"
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#if BX_SUPPORT_PCI
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#include "pci.h"
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#define LOG_THIS thePciBridge->
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const char csname[2][20] = {"i430FX TSC", "i440FX PMC"};
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bx_pci_bridge_c *thePciBridge = NULL;
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int libpci_LTX_plugin_init(plugin_t *plugin, plugintype_t type, int argc, char *argv[])
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{
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if (type == PLUGTYPE_CORE) {
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thePciBridge = new bx_pci_bridge_c();
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BX_REGISTER_DEVICE_DEVMODEL(plugin, type, thePciBridge, BX_PLUGIN_PCI);
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return 0; // Success
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} else {
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return -1;
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}
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}
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void libpci_LTX_plugin_fini(void)
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{
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delete thePciBridge;
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}
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bx_pci_bridge_c::bx_pci_bridge_c()
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{
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put("PCI");
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}
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bx_pci_bridge_c::~bx_pci_bridge_c()
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{
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SIM->get_bochs_root()->remove("pci_bridge");
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BX_DEBUG(("Exit"));
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}
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void bx_pci_bridge_c::init(void)
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{
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// called once when bochs initializes
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unsigned i;
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Bit32u ramsize;
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Bit8u devfunc = BX_PCI_DEVICE(0,0);
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BX_PCI_THIS chipset = SIM->get_param_enum(BXPN_PCI_CHIPSET)->get();
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DEV_register_pci_handlers(this, &devfunc, BX_PLUGIN_PCI, csname[BX_PCI_THIS chipset]);
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// initialize readonly registers
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if (BX_PCI_THIS chipset == BX_PCI_CHIPSET_I440FX) {
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init_pci_conf(0x8086, 0x1237, 0x00, 0x060000, 0x00);
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} else {
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init_pci_conf(0x8086, 0x0122, 0x02, 0x060000, 0x00);
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}
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// DRAM module setup
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for (i = 0; i < 8; i++)
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BX_PCI_THIS DRBA[i] = 0x0;
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ramsize = SIM->get_param_num(BXPN_MEM_SIZE)->get();
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if ((ramsize & 0x07) != 0) {
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ramsize = (ramsize & ~0x07) + 8;
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}
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if (BX_PCI_THIS chipset == BX_PCI_CHIPSET_I430FX) {
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if (ramsize > 128) ramsize = 128;
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if (ramsize == 8) {
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for (i = 0; i < 5; i++) {
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BX_PCI_THIS DRBA[i] = 0x02;
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}
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} else if (ramsize == 16) {
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BX_PCI_THIS DRBA[0] = 0x02;
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for (i = 1; i < 5; i++) {
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BX_PCI_THIS DRBA[i] = 0x04;
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}
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} else if (ramsize == 24) {
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BX_PCI_THIS DRBA[0] = 0x02;
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BX_PCI_THIS DRBA[1] = 0x04;
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for (i = 2; i < 5; i++) {
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BX_PCI_THIS DRBA[i] = 0x06;
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}
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} else if (ramsize == 32) {
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BX_PCI_THIS DRBA[0] = 0x04;
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for (i = 1; i < 5; i++) {
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BX_PCI_THIS DRBA[i] = 0x08;
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}
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} else if (ramsize <= 48) {
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BX_PCI_THIS DRBA[0] = 0x04;
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BX_PCI_THIS DRBA[1] = 0x08;
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for (i = 2; i < 5; i++) {
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BX_PCI_THIS DRBA[i] = 0x0c;
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}
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} else if (ramsize <= 64) {
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BX_PCI_THIS DRBA[0] = 0x08;
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for (i = 1; i < 5; i++) {
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BX_PCI_THIS DRBA[i] = 0x10;
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}
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} else if (ramsize <= 96) {
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BX_PCI_THIS DRBA[0] = 0x04;
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BX_PCI_THIS DRBA[1] = 0x08;
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BX_PCI_THIS DRBA[2] = 0x10;
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BX_PCI_THIS DRBA[3] = 0x18;
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BX_PCI_THIS DRBA[4] = 0x18;
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} else if (ramsize <= 128) {
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BX_PCI_THIS DRBA[0] = 0x10;
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for (i = 1; i < 5; i++) {
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BX_PCI_THIS DRBA[i] = 0x20;
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}
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}
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} else if (BX_PCI_THIS chipset == BX_PCI_CHIPSET_I440FX) {
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const Bit8u type[3] = {128, 32, 8};
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if (ramsize > 1024) ramsize = 1024;
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Bit8u drbval = 0;
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unsigned row = 0;
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unsigned ti = 0;
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while ((ramsize > 0) && (row < 8) && (ti < 3)) {
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unsigned mc = ramsize / type[ti];
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ramsize = ramsize % type[ti];
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for (i = 0; i < mc; i++) {
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drbval += (type[ti] >> 3);
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BX_PCI_THIS DRBA[row++] = drbval;
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if (row == 8) break;
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}
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ti++;
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}
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while (row < 8) {
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BX_PCI_THIS DRBA[row++] = drbval;
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}
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}
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for (i = 0; i < 8; i++)
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BX_PCI_THIS pci_conf[0x60 + i] = BX_PCI_THIS DRBA[i];
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dram_detect = 0;
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#if BX_DEBUGGER
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// register device for the 'info device' command (calls debug_dump())
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bx_dbg_register_debug_info("pci", this);
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#endif
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}
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void
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bx_pci_bridge_c::reset(unsigned type)
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{
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unsigned i;
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BX_PCI_THIS pci_conf[0x04] = 0x06;
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BX_PCI_THIS pci_conf[0x05] = 0x00;
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BX_PCI_THIS pci_conf[0x07] = 0x02;
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BX_PCI_THIS pci_conf[0x0d] = 0x00;
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BX_PCI_THIS pci_conf[0x0f] = 0x00;
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BX_PCI_THIS pci_conf[0x50] = 0x00;
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BX_PCI_THIS pci_conf[0x52] = 0x00;
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BX_PCI_THIS pci_conf[0x53] = 0x80;
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BX_PCI_THIS pci_conf[0x54] = 0x00;
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BX_PCI_THIS pci_conf[0x55] = 0x00;
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BX_PCI_THIS pci_conf[0x56] = 0x00;
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BX_PCI_THIS pci_conf[0x57] = 0x01;
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if (BX_PCI_THIS chipset == BX_PCI_CHIPSET_I440FX) {
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BX_PCI_THIS pci_conf[0x06] = 0x80;
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BX_PCI_THIS pci_conf[0x51] = 0x01;
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BX_PCI_THIS pci_conf[0x58] = 0x10;
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} else {
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BX_PCI_THIS pci_conf[0x06] = 0x00;
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BX_PCI_THIS pci_conf[0x58] = 0x00;
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}
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for (i=0x59; i<0x60; i++)
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BX_PCI_THIS pci_conf[i] = 0x00;
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BX_PCI_THIS pci_conf[0x72] = 0x02;
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}
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void bx_pci_bridge_c::register_state(void)
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{
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bx_list_c *list = new bx_list_c(SIM->get_bochs_root(), "pci_bridge", "PCI Bridge State");
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register_pci_state(list);
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}
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void bx_pci_bridge_c::after_restore_state(void)
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{
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BX_PCI_THIS smram_control(BX_PCI_THIS pci_conf[0x72]);
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}
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// pci configuration space read callback handler
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Bit32u bx_pci_bridge_c::pci_read_handler(Bit8u address, unsigned io_len)
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{
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Bit32u value = 0;
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for (unsigned i=0; i<io_len; i++) {
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value |= (BX_PCI_THIS pci_conf[address+i] << (i*8));
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}
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BX_DEBUG(("%s read register 0x%02x value 0x%08x", csname[BX_PCI_THIS chipset], address, value));
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return value;
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}
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// pci configuration space write callback handler
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void bx_pci_bridge_c::pci_write_handler(Bit8u address, Bit32u value, unsigned io_len)
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{
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Bit8u value8, oldval;
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unsigned area;
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Bit8u drba_reg, old_dram_detect;
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bx_bool drba_changed;
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old_dram_detect = BX_PCI_THIS dram_detect;
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if ((address >= 0x10) && (address < 0x34))
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return;
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for (unsigned i=0; i<io_len; i++) {
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value8 = (value >> (i*8)) & 0xFF;
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oldval = BX_PCI_THIS pci_conf[address+i];
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switch (address+i) {
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case 0x04:
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if (BX_PCI_THIS chipset == BX_PCI_CHIPSET_I440FX) {
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BX_PCI_THIS pci_conf[address+i] = (value8 & 0x40) | 0x06;
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} else {
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BX_PCI_THIS pci_conf[address+i] = (value8 & 0x02) | 0x04;
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}
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break;
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case 0x05:
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if (BX_PCI_THIS chipset == BX_PCI_CHIPSET_I440FX) {
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BX_PCI_THIS pci_conf[address+i] = (value8 & 0x01);
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}
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break;
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case 0x07:
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if (BX_PCI_THIS chipset == BX_PCI_CHIPSET_I440FX) {
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value8 &= 0xf9;
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} else {
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value8 &= 0x30;
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}
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BX_PCI_THIS pci_conf[address+i] &= ~value8;
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break;
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case 0x0d:
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BX_PCI_THIS pci_conf[address+i] = (value8 & 0xf8);
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break;
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case 0x06:
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case 0x0c:
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case 0x0f:
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break;
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case 0x50:
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if (BX_PCI_THIS chipset == BX_PCI_CHIPSET_I440FX) {
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BX_PCI_THIS pci_conf[address+i] = (value8 & 0x70);
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} else {
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BX_PCI_THIS pci_conf[address+i] = (value8 & 0xef);
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}
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break;
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case 0x51:
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if (BX_PCI_THIS chipset == BX_PCI_CHIPSET_I440FX) {
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BX_PCI_THIS pci_conf[address+i] = (value8 & 0x80) | 0x01;
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}
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break;
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case 0x59:
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case 0x5A:
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case 0x5B:
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case 0x5C:
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case 0x5D:
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case 0x5E:
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case 0x5F:
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if (value != oldval) {
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BX_PCI_THIS pci_conf[address+i] = value8;
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if ((address+i) == 0x59) {
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area = BX_MEM_AREA_F0000;
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DEV_mem_set_memory_type(area, 0, (value >> 4) & 0x1);
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DEV_mem_set_memory_type(area, 1, (value >> 5) & 0x1);
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} else {
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area = ((address+i) - 0x5a) << 1;
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DEV_mem_set_memory_type(area, 0, (value >> 0) & 0x1);
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DEV_mem_set_memory_type(area, 1, (value >> 1) & 0x1);
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area++;
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DEV_mem_set_memory_type(area, 0, (value >> 4) & 0x1);
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DEV_mem_set_memory_type(area, 1, (value >> 5) & 0x1);
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}
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BX_INFO(("%s write to PAM register %x (TLB Flush)", csname[BX_PCI_THIS chipset], address+i));
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bx_pc_system.MemoryMappingChanged();
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}
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break;
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case 0x60:
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case 0x61:
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case 0x62:
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case 0x63:
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case 0x64:
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case 0x65:
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case 0x66:
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case 0x67:
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BX_PCI_THIS pci_conf[address+i] = value8;
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drba_reg = (address + i) & 0x07;
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drba_changed = (BX_PCI_THIS pci_conf[0x60 + drba_reg] != BX_PCI_THIS DRBA[drba_reg]);
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if ((BX_PCI_THIS chipset == BX_PCI_CHIPSET_I430FX) ||
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(BX_PCI_THIS chipset == BX_PCI_CHIPSET_I440FX)) {
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if (drba_changed) {
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BX_PCI_THIS dram_detect |= (1 << drba_reg);
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} else if (!drba_changed && dram_detect) {
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BX_PCI_THIS dram_detect &= ~(1 << drba_reg);
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}
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}
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break;
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case 0x72:
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smram_control(value); // SMRAM conrol register
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break;
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default:
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BX_PCI_THIS pci_conf[address+i] = value8;
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BX_DEBUG(("%s write register 0x%02x value 0x%02x", csname[BX_PCI_THIS chipset], address+i, value8));
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}
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}
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if ((BX_PCI_THIS chipset == BX_PCI_CHIPSET_I430FX) ||
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(BX_PCI_THIS chipset == BX_PCI_CHIPSET_I440FX)) {
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if ((BX_PCI_THIS dram_detect > 0) && (old_dram_detect == 0)) {
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// TODO
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BX_ERROR(("FIXME: DRAM module detection"));
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} else if ((BX_PCI_THIS dram_detect == 0) && (old_dram_detect > 0)) {
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// TODO
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BX_INFO(("normal memory access mode"));
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}
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}
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}
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void bx_pci_bridge_c::smram_control(Bit8u value8)
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{
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//
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// From i440FX chipset manual:
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//
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// [7:7] Reserved.
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// [6:6] SMM Space Open (DOPEN), when DOPEN=1 and DLCK=0, SMM space DRAM
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// became visible even CPU not indicte SMM mode access. This is
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// indended to help BIOS to initialize SMM space.
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// [5:5] SMM Space Closed (DCLS), when DCLS=1, SMM space is not accessible
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// for data references, even if CPU indicates SMM mode access. Code
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// references may still access SMM space DRAM.
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// [4:4] SMM Space Locked (DLCK), when DLCK=1, DOPEN is set to 0 and
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// both DLCK and DOPEN became R/O. DLCK can only be cleared by
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// a power-on reset.
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// [3:3] SMRAM Enable (SMRAME)
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// [2:0] SMM space base segment, program the location of SMM space
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// reserved.
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//
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// SMRAM space access cycles:
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// | SMRAME | DLCK | DCLS | DOPEN | CPU_SMM | | Code | Data |
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// ------------------------------------------ ---------------
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// | 0 | X | X | X | X | -> | PCI | PCI |
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// | 1 | 0 | X | 0 | 0 | -> | PCI | PCI |
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// | 1 | 0 | 0 | 0 | 1 | -> | DRAM | DRAM |
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// | 1 | 0 | 0 | 1 | X | -> | DRAM | DRAM |
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// | 1 | 1 | 0 | X | 1 | -> | DRAM | DRAM |
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// | 1 | 0 | 1 | 0 | 1 | -> | DRAM | PCI |
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// | 1 | 0 | 1 | 1 | X | -> | ---- | ---- |
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// | 1 | 1 | X | X | 0 | -> | PCI | PCI |
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// | 1 | 1 | 1 | X | 1 | -> | DRAM | PCI |
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// ------------------------------------------ ---------------
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value8 = (value8 & 0x78) | 0x2; // ignore reserved bits
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if (BX_PCI_THIS pci_conf[0x72] & 0x10)
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{
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value8 &= 0xbf; // set DOPEN=0, DLCK=1
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value8 |= 0x10;
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}
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if ((value8 & 0x08) == 0) {
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bx_devices.mem->disable_smram();
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}
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else {
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bx_bool DOPEN = (value8 & 0x40) > 0, DCLS = (value8 & 0x20) > 0;
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if(DOPEN && DCLS) BX_PANIC(("SMRAM control: DOPEN not mutually exclusive with DCLS !"));
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bx_devices.mem->enable_smram(DOPEN, DCLS);
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}
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BX_INFO(("setting SMRAM control register to 0x%02x", value8));
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BX_PCI_THIS pci_conf[0x72] = value8;
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}
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#if BX_DEBUGGER
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void bx_pci_bridge_c::debug_dump(int argc, char **argv)
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{
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int arg, i, j, r;
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if (BX_PCI_THIS chipset == BX_PCI_CHIPSET_I440FX) {
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dbg_printf("i440FX PMC/DBX\n\n");
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} else {
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dbg_printf("i430FX TSC/TDP\n\n");
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}
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dbg_printf("confAddr = 0x%08x\n\n", DEV_pci_get_confAddr());
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if (argc == 0) {
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for (i = 0x59; i < 0x60; i++) {
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dbg_printf("PAM reg 0x%02x = 0x%02x\n", i, BX_PCI_THIS pci_conf[i]);
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}
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dbg_printf("SMRAM control = 0x%02x\n", BX_PCI_THIS pci_conf[0x72]);
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dbg_printf("\nSupported options:\n");
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dbg_printf("info device 'pci' 'dump=full' - show PCI config space\n");
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} else {
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for (arg = 0; arg < argc; arg++) {
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if (!strcmp(argv[arg], "dump=full")) {
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dbg_printf("\nPCI config space\n\n");
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r = 0;
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for (i=0; i<16; i++) {
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dbg_printf("%04x ", r);
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for (j=0; j<16; j++) {
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dbg_printf(" %02x", BX_PCI_THIS pci_conf[r++]);
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}
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dbg_printf("\n");
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}
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} else {
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dbg_printf("\nUnknown option: '%s'\n", argv[arg]);
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}
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}
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}
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}
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#endif
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#endif /* BX_SUPPORT_PCI */
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