Bochs/bochs/cpu/decoder
2017-03-16 16:20:58 +00:00
..
decoder.h imvent a bochs feature for AMD TCE and enable EFER.TCE bit 2017-03-15 22:52:08 +00:00
disasm.cc simplify disasm code by splitting it into functions 2017-01-22 19:53:42 +00:00
fetchdecode32.cc add vex.w into bxInstruction to be used in disasm 2017-01-28 19:25:30 +00:00
fetchdecode64.cc update (c) 2017-01-11 20:54:09 +00:00
fetchdecode_avx.h step 1 of rewrite Bochs decoder: legacy decoder tables done. TODO: avx/evex decoder tables, merge decoder and disasm together 2017-01-10 20:15:17 +00:00
fetchdecode_evex.h step 1 of rewrite Bochs decoder: legacy decoder tables done. TODO: avx/evex decoder tables, merge decoder and disasm together 2017-01-10 20:15:17 +00:00
fetchdecode_opmap_0f3a.h add SVN header to newly added files 2017-01-10 20:16:24 +00:00
fetchdecode_opmap_0f38.h add SVN header to newly added files 2017-01-10 20:16:24 +00:00
fetchdecode_opmap.h SMAP opcodes are No-SSE-Prefix 2017-03-16 16:20:58 +00:00
fetchdecode_x87.h fetchdecode rework step 0.1, no impact on correctness, small speedup 2016-12-09 12:34:37 +00:00
fetchdecode_xop.h step 1 of rewrite Bochs decoder: legacy decoder tables done. TODO: avx/evex decoder tables, merge decoder and disasm together 2017-01-10 20:15:17 +00:00
fetchdecode.h implemented xsaves/xrstors extensions (supported by Intel Skylake core and AMD Ryzen) 2017-03-15 21:44:15 +00:00
ia_opcodes.h implemented xsaves/xrstors extensions (supported by Intel Skylake core and AMD Ryzen) 2017-03-15 21:44:15 +00:00
instr.h add vex.w into bxInstruction to be used in disasm 2017-01-28 19:25:30 +00:00