ff79cbd596
The end goal will be also merging of disasm and cpu decoder to one module and remove the disasm. Two bug fixes on the way: TBM: fixed 64-bit TBM instructions with memory access (did 32-bit load instead of 64-bit) BMI2: fixed operands order for PEXT/PDEP instructions AVX2: fixed gather instruction decoding bug from decoder alias commit
125 lines
3.5 KiB
C++
125 lines
3.5 KiB
C++
/////////////////////////////////////////////////////////////////////////
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// $Id$
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/////////////////////////////////////////////////////////////////////////
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//
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// Copyright (C) 2001-2012 The Bochs Project
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//
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// This library is free software; you can redistribute it and/or
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// modify it under the terms of the GNU Lesser General Public
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// License as published by the Free Software Foundation; either
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// version 2 of the License, or (at your option) any later version.
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//
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// This library is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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// Lesser General Public License for more details.
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//
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// You should have received a copy of the GNU Lesser General Public
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// License along with this library; if not, write to the Free Software
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// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA B 02110-1301 USA
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/////////////////////////////////////////////////////////////////////////
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#define NEED_CPU_REG_SHORTCUTS 1
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#include "bochs.h"
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#include "cpu.h"
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#define LOG_THIS BX_CPU_THIS_PTR
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BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::MOV_EbIbR(bxInstruction_c *i)
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{
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BX_WRITE_8BIT_REGx(i->dst(), i->extend8bitL(), i->Ib());
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BX_NEXT_INSTR(i);
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}
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BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::MOV_EbGbM(bxInstruction_c *i)
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{
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bx_address eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
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write_virtual_byte(i->seg(), eaddr, BX_READ_8BIT_REGx(i->src(), i->extend8bitL()));
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BX_NEXT_INSTR(i);
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}
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BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::MOV_GbEbM(bxInstruction_c *i)
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{
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bx_address eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
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Bit8u val8 = read_virtual_byte(i->seg(), eaddr);
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BX_WRITE_8BIT_REGx(i->dst(), i->extend8bitL(), val8);
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BX_NEXT_INSTR(i);
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}
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BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::MOV_GbEbR(bxInstruction_c *i)
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{
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Bit8u op2 = BX_READ_8BIT_REGx(i->src(), i->extend8bitL());
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BX_WRITE_8BIT_REGx(i->dst(), i->extend8bitL(), op2);
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BX_NEXT_INSTR(i);
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}
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BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::MOV_ALOd(bxInstruction_c *i)
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{
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AL = read_virtual_byte_32(i->seg(), i->Id());
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BX_NEXT_INSTR(i);
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}
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BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::MOV_OdAL(bxInstruction_c *i)
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{
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write_virtual_byte_32(i->seg(), i->Id(), AL);
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BX_NEXT_INSTR(i);
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}
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BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::MOV_EbIbM(bxInstruction_c *i)
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{
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bx_address eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
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write_virtual_byte(i->seg(), eaddr, i->Ib());
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BX_NEXT_INSTR(i);
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}
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BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::XLAT(bxInstruction_c *i)
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{
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#if BX_SUPPORT_X86_64
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if (i->as64L()) {
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AL = read_virtual_byte_64(i->seg(), RBX + AL);
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}
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else
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#endif
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if (i->as32L()) {
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AL = read_virtual_byte(i->seg(), (Bit32u) (EBX + AL));
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}
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else {
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AL = read_virtual_byte_32(i->seg(), (Bit16u) (BX + AL));
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}
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BX_NEXT_INSTR(i);
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}
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BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::XCHG_EbGbM(bxInstruction_c *i)
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{
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bx_address eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
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Bit8u op1 = read_RMW_virtual_byte(i->seg(), eaddr);
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Bit8u op2 = BX_READ_8BIT_REGx(i->src(), i->extend8bitL());
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write_RMW_virtual_byte(op2);
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BX_WRITE_8BIT_REGx(i->src(), i->extend8bitL(), op1);
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BX_NEXT_INSTR(i);
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}
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BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::XCHG_EbGbR(bxInstruction_c *i)
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{
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Bit8u op1 = BX_READ_8BIT_REGx(i->dst(), i->extend8bitL());
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Bit8u op2 = BX_READ_8BIT_REGx(i->src(), i->extend8bitL());
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BX_WRITE_8BIT_REGx(i->src(), i->extend8bitL(), op1);
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BX_WRITE_8BIT_REGx(i->dst(), i->extend8bitL(), op2);
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BX_NEXT_INSTR(i);
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}
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