240 lines
6.0 KiB
C++
240 lines
6.0 KiB
C++
/////////////////////////////////////////////////////////////////////////
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// $Id$
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/////////////////////////////////////////////////////////////////////////
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//
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// Copyright (C) 2001-2009 The Bochs Project
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//
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// This library is free software; you can redistribute it and/or
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// modify it under the terms of the GNU Lesser General Public
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// License as published by the Free Software Foundation; either
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// version 2 of the License, or (at your option) any later version.
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//
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// This library is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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// Lesser General Public License for more details.
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//
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// You should have received a copy of the GNU Lesser General Public
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// License along with this library; if not, write to the Free Software
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// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA B 02110-1301 USA
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/////////////////////////////////////////////////////////////////////////
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#define NEED_CPU_REG_SHORTCUTS 1
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#include "bochs.h"
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#include "cpu.h"
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#define LOG_THIS BX_CPU_THIS_PTR
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#if BX_SUPPORT_X86_64==0
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// Make life easier for merging cpu64 and cpu32 code.
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#define RAX EAX
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#endif
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void BX_CPP_AttrRegparmN(1) BX_CPU_C::XOR_EdGdM(bxInstruction_c *i)
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{
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Bit32u op1_32, op2_32;
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bx_address eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
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op1_32 = read_RMW_virtual_dword(i->seg(), eaddr);
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op2_32 = BX_READ_32BIT_REG(i->nnn());
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op1_32 ^= op2_32;
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write_RMW_virtual_dword(op1_32);
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SET_FLAGS_OSZAPC_LOGIC_32(op1_32);
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}
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void BX_CPP_AttrRegparmN(1) BX_CPU_C::XOR_GdEdR(bxInstruction_c *i)
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{
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Bit32u op1_32, op2_32;
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op1_32 = BX_READ_32BIT_REG(i->nnn());
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op2_32 = BX_READ_32BIT_REG(i->rm());
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op1_32 ^= op2_32;
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BX_WRITE_32BIT_REGZ(i->nnn(), op1_32);
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SET_FLAGS_OSZAPC_LOGIC_32(op1_32);
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}
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void BX_CPP_AttrRegparmN(1) BX_CPU_C::XOR_EAXId(bxInstruction_c *i)
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{
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Bit32u op_32 = EAX ^ i->Id();
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RAX = op_32;
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SET_FLAGS_OSZAPC_LOGIC_32(op_32);
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}
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void BX_CPP_AttrRegparmN(1) BX_CPU_C::XOR_EdIdM(bxInstruction_c *i)
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{
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Bit32u op1_32;
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bx_address eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
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op1_32 = read_RMW_virtual_dword(i->seg(), eaddr);
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op1_32 ^= i->Id();
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write_RMW_virtual_dword(op1_32);
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SET_FLAGS_OSZAPC_LOGIC_32(op1_32);
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}
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void BX_CPP_AttrRegparmN(1) BX_CPU_C::XOR_EdIdR(bxInstruction_c *i)
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{
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Bit32u op1_32 = BX_READ_32BIT_REG(i->rm());
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op1_32 ^= i->Id();
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BX_WRITE_32BIT_REGZ(i->rm(), op1_32);
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SET_FLAGS_OSZAPC_LOGIC_32(op1_32);
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}
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void BX_CPP_AttrRegparmN(1) BX_CPU_C::OR_EdIdM(bxInstruction_c *i)
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{
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Bit32u op1_32;
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bx_address eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
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op1_32 = read_RMW_virtual_dword(i->seg(), eaddr);
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op1_32 |= i->Id();
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write_RMW_virtual_dword(op1_32);
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SET_FLAGS_OSZAPC_LOGIC_32(op1_32);
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}
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void BX_CPP_AttrRegparmN(1) BX_CPU_C::OR_EdIdR(bxInstruction_c *i)
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{
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Bit32u op1_32 = BX_READ_32BIT_REG(i->rm());
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op1_32 |= i->Id();
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BX_WRITE_32BIT_REGZ(i->rm(), op1_32);
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SET_FLAGS_OSZAPC_LOGIC_32(op1_32);
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}
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void BX_CPP_AttrRegparmN(1) BX_CPU_C::NOT_EdM(bxInstruction_c *i)
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{
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bx_address eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
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Bit32u op1_32 = read_RMW_virtual_dword(i->seg(), eaddr);
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op1_32 = ~op1_32;
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write_RMW_virtual_dword(op1_32);
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}
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void BX_CPP_AttrRegparmN(1) BX_CPU_C::NOT_EdR(bxInstruction_c *i)
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{
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Bit32u op1_32 = BX_READ_32BIT_REG(i->rm());
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op1_32 = ~op1_32;
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BX_WRITE_32BIT_REGZ(i->rm(), op1_32);
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}
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void BX_CPP_AttrRegparmN(1) BX_CPU_C::OR_EdGdM(bxInstruction_c *i)
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{
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Bit32u op1_32, op2_32;
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bx_address eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
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op1_32 = read_RMW_virtual_dword(i->seg(), eaddr);
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op2_32 = BX_READ_32BIT_REG(i->nnn());
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op1_32 |= op2_32;
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write_RMW_virtual_dword(op1_32);
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SET_FLAGS_OSZAPC_LOGIC_32(op1_32);
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}
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void BX_CPP_AttrRegparmN(1) BX_CPU_C::OR_GdEdR(bxInstruction_c *i)
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{
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Bit32u op1_32, op2_32;
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op1_32 = BX_READ_32BIT_REG(i->nnn());
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op2_32 = BX_READ_32BIT_REG(i->rm());
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op1_32 |= op2_32;
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BX_WRITE_32BIT_REGZ(i->nnn(), op1_32);
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SET_FLAGS_OSZAPC_LOGIC_32(op1_32);
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}
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void BX_CPP_AttrRegparmN(1) BX_CPU_C::OR_EAXId(bxInstruction_c *i)
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{
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Bit32u op_32 = EAX | i->Id();
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RAX = op_32;
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SET_FLAGS_OSZAPC_LOGIC_32(op_32);
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}
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void BX_CPP_AttrRegparmN(1) BX_CPU_C::AND_EdGdM(bxInstruction_c *i)
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{
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Bit32u op1_32, op2_32;
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bx_address eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
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op1_32 = read_RMW_virtual_dword(i->seg(), eaddr);
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op2_32 = BX_READ_32BIT_REG(i->nnn());
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op1_32 &= op2_32;
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write_RMW_virtual_dword(op1_32);
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SET_FLAGS_OSZAPC_LOGIC_32(op1_32);
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}
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void BX_CPP_AttrRegparmN(1) BX_CPU_C::AND_GdEdR(bxInstruction_c *i)
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{
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Bit32u op1_32, op2_32;
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op1_32 = BX_READ_32BIT_REG(i->nnn());
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op2_32 = BX_READ_32BIT_REG(i->rm());
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op1_32 &= op2_32;
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BX_WRITE_32BIT_REGZ(i->nnn(), op1_32);
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SET_FLAGS_OSZAPC_LOGIC_32(op1_32);
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}
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void BX_CPP_AttrRegparmN(1) BX_CPU_C::AND_EAXId(bxInstruction_c *i)
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{
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Bit32u op_32 = EAX & i->Id();
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RAX = op_32;
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SET_FLAGS_OSZAPC_LOGIC_32(op_32);
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}
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void BX_CPP_AttrRegparmN(1) BX_CPU_C::AND_EdIdM(bxInstruction_c *i)
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{
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Bit32u op1_32;
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bx_address eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
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op1_32 = read_RMW_virtual_dword(i->seg(), eaddr);
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op1_32 &= i->Id();
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write_RMW_virtual_dword(op1_32);
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SET_FLAGS_OSZAPC_LOGIC_32(op1_32);
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}
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void BX_CPP_AttrRegparmN(1) BX_CPU_C::AND_EdIdR(bxInstruction_c *i)
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{
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Bit32u op1_32 = BX_READ_32BIT_REG(i->rm());
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op1_32 &= i->Id();
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BX_WRITE_32BIT_REGZ(i->rm(), op1_32);
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SET_FLAGS_OSZAPC_LOGIC_32(op1_32);
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}
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void BX_CPP_AttrRegparmN(1) BX_CPU_C::TEST_EdGdR(bxInstruction_c *i)
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{
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Bit32u op1_32, op2_32;
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op1_32 = BX_READ_32BIT_REG(i->rm());
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op2_32 = BX_READ_32BIT_REG(i->nnn());
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op1_32 &= op2_32;
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SET_FLAGS_OSZAPC_LOGIC_32(op1_32);
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}
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void BX_CPP_AttrRegparmN(1) BX_CPU_C::TEST_EAXId(bxInstruction_c *i)
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{
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Bit32u op_32 = EAX & i->Id();
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SET_FLAGS_OSZAPC_LOGIC_32(op_32);
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}
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void BX_CPP_AttrRegparmN(1) BX_CPU_C::TEST_EdIdR(bxInstruction_c *i)
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{
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Bit32u op1_32 = BX_READ_32BIT_REG(i->rm());
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op1_32 &= i->Id();
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SET_FLAGS_OSZAPC_LOGIC_32(op1_32);
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}
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