e61d00351f
in BRANCH-smp-bochs revisions. - The general task was to make multiple CPU's which communicate through their APICs. So instead of BX_CPU and BX_MEM, we now have BX_CPU(x) and BX_MEM(y). For an SMP simulation you have several processors in a shared memory space, so there might be processors BX_CPU(0..3) but only one memory space BX_MEM(0). For cosimulation, you could have BX_CPU(0) with BX_MEM(0), then BX_CPU(1) with BX_MEM(1). WARNING: Cosimulation is almost certainly broken by the SMP changes. - to simulate multiple CPUs, you have to give each CPU time to execute in turn. This is currently implemented using debugger guards. The cpu loop steps one CPU for a few instructions, then steps the next CPU for a few instructions, etc. - there is some limited support in the debugger for two CPUs, for example printing information from each CPU when single stepping. |
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| .. | ||
| dis_decode.cc | ||
| dis_groups.cc | ||
| disasm.h | ||
| Makefile.in | ||