1546 lines
35 KiB
C++
1546 lines
35 KiB
C++
/////////////////////////////////////////////////////////////////////////
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// $Id: bit.cc,v 1.22 2004-09-17 20:47:17 sshwarts Exp $
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/////////////////////////////////////////////////////////////////////////
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//
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// Copyright (C) 2001 MandrakeSoft S.A.
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//
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// MandrakeSoft S.A.
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// 43, rue d'Aboukir
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// 75002 Paris - France
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// http://www.linux-mandrake.com/
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// http://www.mandrakesoft.com/
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//
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// This library is free software; you can redistribute it and/or
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// modify it under the terms of the GNU Lesser General Public
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// License as published by the Free Software Foundation; either
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// version 2 of the License, or (at your option) any later version.
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//
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// This library is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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// Lesser General Public License for more details.
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//
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// You should have received a copy of the GNU Lesser General Public
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// License along with this library; if not, write to the Free Software
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// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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#define NEED_CPU_REG_SHORTCUTS 1
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#include "bochs.h"
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#define LOG_THIS BX_CPU_THIS_PTR
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#if BX_CPU_LEVEL >= 3
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#if BX_SUPPORT_X86_64==0
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// Make life easier merging cpu64 and cpu code.
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#define RAX EAX
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#define RBX EBX
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#define RCX ECX
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#define RDX EDX
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#define RSP ESP
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#define RSI ESI
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#define RDI EDI
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#define RBP EBP
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#endif
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void BX_CPU_C::SETO_Eb(bxInstruction_c *i)
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{
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Bit8u result_8;
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if (get_OF())
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result_8 = 1;
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else
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result_8 = 0;
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/* now write result back to destination */
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if (i->modC0()) {
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BX_WRITE_8BIT_REGx(i->rm(), i->extend8bitL(), result_8);
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}
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else {
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write_virtual_byte(i->seg(), RMAddr(i), &result_8);
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}
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}
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void BX_CPU_C::SETNO_Eb(bxInstruction_c *i)
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{
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Bit8u result_8;
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if (get_OF()==0)
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result_8 = 1;
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else
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result_8 = 0;
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/* now write result back to destination */
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if (i->modC0()) {
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BX_WRITE_8BIT_REGx(i->rm(), i->extend8bitL(), result_8);
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}
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else {
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write_virtual_byte(i->seg(), RMAddr(i), &result_8);
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}
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}
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void BX_CPU_C::SETB_Eb(bxInstruction_c *i)
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{
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Bit8u result_8;
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if (get_CF())
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result_8 = 1;
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else
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result_8 = 0;
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/* now write result back to destination */
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if (i->modC0()) {
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BX_WRITE_8BIT_REGx(i->rm(), i->extend8bitL(), result_8);
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}
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else {
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write_virtual_byte(i->seg(), RMAddr(i), &result_8);
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}
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}
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void BX_CPU_C::SETNB_Eb(bxInstruction_c *i)
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{
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Bit8u result_8;
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if (get_CF()==0)
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result_8 = 1;
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else
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result_8 = 0;
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/* now write result back to destination */
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if (i->modC0()) {
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BX_WRITE_8BIT_REGx(i->rm(), i->extend8bitL(), result_8);
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}
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else {
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write_virtual_byte(i->seg(), RMAddr(i), &result_8);
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}
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}
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void BX_CPU_C::SETZ_Eb(bxInstruction_c *i)
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{
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Bit8u result_8;
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if (get_ZF())
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result_8 = 1;
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else
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result_8 = 0;
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/* now write result back to destination */
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if (i->modC0()) {
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BX_WRITE_8BIT_REGx(i->rm(), i->extend8bitL(), result_8);
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}
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else {
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write_virtual_byte(i->seg(), RMAddr(i), &result_8);
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}
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}
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void BX_CPU_C::SETNZ_Eb(bxInstruction_c *i)
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{
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Bit8u result_8;
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if (get_ZF()==0)
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result_8 = 1;
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else
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result_8 = 0;
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/* now write result back to destination */
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if (i->modC0()) {
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BX_WRITE_8BIT_REGx(i->rm(), i->extend8bitL(), result_8);
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}
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else {
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write_virtual_byte(i->seg(), RMAddr(i), &result_8);
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}
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}
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void BX_CPU_C::SETBE_Eb(bxInstruction_c *i)
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{
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Bit8u result_8;
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if (get_CF() || get_ZF())
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result_8 = 1;
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else
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result_8 = 0;
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/* now write result back to destination */
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if (i->modC0()) {
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BX_WRITE_8BIT_REGx(i->rm(), i->extend8bitL(), result_8);
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}
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else {
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write_virtual_byte(i->seg(), RMAddr(i), &result_8);
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}
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}
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void BX_CPU_C::SETNBE_Eb(bxInstruction_c *i)
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{
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Bit8u result_8;
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if ((get_CF()==0) && (get_ZF()==0))
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result_8 = 1;
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else
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result_8 = 0;
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/* now write result back to destination */
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if (i->modC0()) {
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BX_WRITE_8BIT_REGx(i->rm(), i->extend8bitL(), result_8);
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}
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else {
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write_virtual_byte(i->seg(), RMAddr(i), &result_8);
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}
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}
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void BX_CPU_C::SETS_Eb(bxInstruction_c *i)
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{
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Bit8u result_8;
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if (get_SF())
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result_8 = 1;
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else
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result_8 = 0;
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/* now write result back to destination */
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if (i->modC0()) {
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BX_WRITE_8BIT_REGx(i->rm(), i->extend8bitL(), result_8);
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}
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else {
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write_virtual_byte(i->seg(), RMAddr(i), &result_8);
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}
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}
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void BX_CPU_C::SETNS_Eb(bxInstruction_c *i)
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{
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Bit8u result_8;
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if (get_SF()==0)
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result_8 = 1;
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else
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result_8 = 0;
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/* now write result back to destination */
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if (i->modC0()) {
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BX_WRITE_8BIT_REGx(i->rm(), i->extend8bitL(), result_8);
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}
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else {
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write_virtual_byte(i->seg(), RMAddr(i), &result_8);
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}
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}
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void BX_CPU_C::SETP_Eb(bxInstruction_c *i)
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{
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Bit8u result_8;
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if (get_PF())
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result_8 = 1;
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else
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result_8 = 0;
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/* now write result back to destination */
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if (i->modC0()) {
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BX_WRITE_8BIT_REGx(i->rm(), i->extend8bitL(), result_8);
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}
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else {
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write_virtual_byte(i->seg(), RMAddr(i), &result_8);
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}
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}
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void BX_CPU_C::SETNP_Eb(bxInstruction_c *i)
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{
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Bit8u result_8;
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if (get_PF() == 0)
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result_8 = 1;
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else
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result_8 = 0;
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/* now write result back to destination */
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if (i->modC0()) {
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BX_WRITE_8BIT_REGx(i->rm(), i->extend8bitL(), result_8);
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}
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else {
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write_virtual_byte(i->seg(), RMAddr(i), &result_8);
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}
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}
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void BX_CPU_C::SETL_Eb(bxInstruction_c *i)
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{
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Bit8u result_8;
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if (getB_SF() != getB_OF())
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result_8 = 1;
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else
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result_8 = 0;
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/* now write result back to destination */
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if (i->modC0()) {
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BX_WRITE_8BIT_REGx(i->rm(), i->extend8bitL(), result_8);
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}
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else {
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write_virtual_byte(i->seg(), RMAddr(i), &result_8);
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}
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}
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void BX_CPU_C::SETNL_Eb(bxInstruction_c *i)
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{
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Bit8u result_8;
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if (getB_SF() == getB_OF())
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result_8 = 1;
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else
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result_8 = 0;
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/* now write result back to destination */
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if (i->modC0()) {
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BX_WRITE_8BIT_REGx(i->rm(), i->extend8bitL(), result_8);
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}
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else {
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write_virtual_byte(i->seg(), RMAddr(i), &result_8);
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}
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}
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void BX_CPU_C::SETLE_Eb(bxInstruction_c *i)
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{
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Bit8u result_8;
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if (get_ZF() || (getB_SF()!=getB_OF()))
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result_8 = 1;
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else
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result_8 = 0;
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/* now write result back to destination */
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if (i->modC0()) {
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BX_WRITE_8BIT_REGx(i->rm(), i->extend8bitL(), result_8);
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}
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else {
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write_virtual_byte(i->seg(), RMAddr(i), &result_8);
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}
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}
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void BX_CPU_C::SETNLE_Eb(bxInstruction_c *i)
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{
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Bit8u result_8;
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if ((get_ZF()==0) && (getB_SF()==getB_OF()))
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result_8 = 1;
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else
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result_8 = 0;
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/* now write result back to destination */
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if (i->modC0()) {
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BX_WRITE_8BIT_REGx(i->rm(), i->extend8bitL(), result_8);
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}
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else {
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write_virtual_byte(i->seg(), RMAddr(i), &result_8);
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}
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}
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void BX_CPU_C::BSF_GwEw(bxInstruction_c *i)
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{
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Bit16u op1_16, op2_16;
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/* op2_16 is a register or memory reference */
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if (i->modC0()) {
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op2_16 = BX_READ_16BIT_REG(i->rm());
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}
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else {
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/* pointer, segment address pair */
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read_virtual_word(i->seg(), RMAddr(i), &op2_16);
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}
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if (op2_16 == 0) {
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set_ZF(1); /* op1_16 undefined */
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return;
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}
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op1_16 = 0;
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while ( (op2_16 & 0x01) == 0 ) {
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op1_16++;
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op2_16 >>= 1;
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}
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SET_FLAGS_OSZAPC_RESULT_16(op1_16, BX_INSTR_BITSCAN16);
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/* now write result back to destination */
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BX_WRITE_16BIT_REG(i->nnn(), op1_16);
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}
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void BX_CPU_C::BSF_GdEd(bxInstruction_c *i)
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{
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/* for 32 bit operand size mode */
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Bit32u op1_32, op2_32;
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/* op2_32 is a register or memory reference */
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if (i->modC0()) {
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op2_32 = BX_READ_32BIT_REG(i->rm());
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}
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else {
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/* pointer, segment address pair */
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read_virtual_dword(i->seg(), RMAddr(i), &op2_32);
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}
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if (op2_32 == 0) {
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set_ZF(1); /* op1_32 undefined */
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return;
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}
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op1_32 = 0;
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while ( (op2_32 & 0x01) == 0 ) {
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op1_32++;
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op2_32 >>= 1;
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}
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SET_FLAGS_OSZAPC_RESULT_32(op1_32, BX_INSTR_BITSCAN32);
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/* now write result back to destination */
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BX_WRITE_32BIT_REGZ(i->nnn(), op1_32);
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}
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#if BX_SUPPORT_X86_64
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void BX_CPU_C::BSF_GqEq(bxInstruction_c *i)
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{
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/* for 64 bit operand size mode */
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Bit64u op1_64, op2_64;
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/* op2_64 is a register or memory reference */
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if (i->modC0()) {
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op2_64 = BX_READ_64BIT_REG(i->rm());
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}
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else {
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/* pointer, segment address pair */
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read_virtual_qword(i->seg(), RMAddr(i), &op2_64);
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}
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if (op2_64 == 0) {
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set_ZF(1); /* op1_64 undefined */
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return;
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}
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op1_64 = 0;
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while ( (op2_64 & 0x01) == 0 ) {
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op1_64++;
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op2_64 >>= 1;
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}
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SET_FLAGS_OSZAPC_RESULT_64(op1_64, BX_INSTR_BITSCAN64);
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/* now write result back to destination */
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BX_WRITE_64BIT_REG(i->nnn(), op1_64);
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}
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#endif // #if BX_SUPPORT_X86_64
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void BX_CPU_C::BSR_GwEw(bxInstruction_c *i)
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{
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Bit16u op1_16, op2_16;
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/* op2_16 is a register or memory reference */
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if (i->modC0()) {
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op2_16 = BX_READ_16BIT_REG(i->rm());
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}
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else {
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/* pointer, segment address pair */
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read_virtual_word(i->seg(), RMAddr(i), &op2_16);
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}
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if (op2_16 == 0) {
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set_ZF(1); /* op1_16 undefined */
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return;
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}
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op1_16 = 15;
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while ( (op2_16 & 0x8000) == 0 ) {
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op1_16--;
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op2_16 <<= 1;
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}
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SET_FLAGS_OSZAPC_RESULT_16(op1_16, BX_INSTR_BITSCAN16);
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/* now write result back to destination */
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BX_WRITE_16BIT_REG(i->nnn(), op1_16);
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}
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void BX_CPU_C::BSR_GdEd(bxInstruction_c *i)
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{
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/* for 32 bit operand size mode */
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Bit32u op1_32, op2_32;
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/* op2_32 is a register or memory reference */
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if (i->modC0()) {
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op2_32 = BX_READ_32BIT_REG(i->rm());
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}
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else {
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/* pointer, segment address pair */
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read_virtual_dword(i->seg(), RMAddr(i), &op2_32);
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}
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if (op2_32 == 0) {
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set_ZF(1); /* op1_32 undefined */
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return;
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}
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op1_32 = 31;
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while ( (op2_32 & 0x80000000) == 0 ) {
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op1_32--;
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op2_32 <<= 1;
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}
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SET_FLAGS_OSZAPC_RESULT_32(op1_32, BX_INSTR_BITSCAN32);
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/* now write result back to destination */
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BX_WRITE_32BIT_REGZ(i->nnn(), op1_32);
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}
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#if BX_SUPPORT_X86_64
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void BX_CPU_C::BSR_GqEq(bxInstruction_c *i)
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{
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/* for 64 bit operand size mode */
|
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Bit64u op1_64, op2_64;
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/* op2_64 is a register or memory reference */
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if (i->modC0()) {
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op2_64 = BX_READ_64BIT_REG(i->rm());
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}
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else {
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/* pointer, segment address pair */
|
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read_virtual_qword(i->seg(), RMAddr(i), &op2_64);
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}
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|
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if (op2_64 == 0) {
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set_ZF(1); /* op1_64 undefined */
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return;
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}
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|
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op1_64 = 63;
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while ( (op2_64 & BX_CONST64(0x8000000000000000)) == 0 ) {
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op1_64--;
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op2_64 <<= 1;
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}
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SET_FLAGS_OSZAPC_RESULT_64(op1_64, BX_INSTR_BITSCAN64);
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|
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/* now write result back to destination */
|
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BX_WRITE_64BIT_REG(i->nnn(), op1_64);
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}
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#endif
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void BX_CPU_C::BSWAP_EAX(bxInstruction_c *i)
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{
|
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#if (BX_CPU_LEVEL >= 4) || (BX_CPU_LEVEL_HACKED >= 4)
|
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Bit32u eax, b0, b1, b2, b3;
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|
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eax = EAX;
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b0 = eax & 0xff; eax >>= 8;
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b1 = eax & 0xff; eax >>= 8;
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b2 = eax & 0xff; eax >>= 8;
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b3 = eax;
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RAX = (b0<<24) | (b1<<16) | (b2<<8) | b3; // zero extended
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#else
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BX_INFO(("BSWAP_EAX: not implemented CPU <= 3"));
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UndefinedOpcode(i);
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#endif
|
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}
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|
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void BX_CPU_C::BSWAP_ECX(bxInstruction_c *i)
|
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{
|
|
#if (BX_CPU_LEVEL >= 4) || (BX_CPU_LEVEL_HACKED >= 4)
|
|
Bit32u ecx, b0, b1, b2, b3;
|
|
|
|
ecx = ECX;
|
|
b0 = ecx & 0xff; ecx >>= 8;
|
|
b1 = ecx & 0xff; ecx >>= 8;
|
|
b2 = ecx & 0xff; ecx >>= 8;
|
|
b3 = ecx;
|
|
|
|
RCX = (b0<<24) | (b1<<16) | (b2<<8) | b3;
|
|
#else
|
|
BX_INFO(("BSWAP_ECX: not implemented CPU <= 3"));
|
|
UndefinedOpcode(i);
|
|
#endif
|
|
}
|
|
|
|
void BX_CPU_C::BSWAP_EDX(bxInstruction_c *i)
|
|
{
|
|
#if (BX_CPU_LEVEL >= 4) || (BX_CPU_LEVEL_HACKED >= 4)
|
|
Bit32u edx, b0, b1, b2, b3;
|
|
|
|
edx = EDX;
|
|
b0 = edx & 0xff; edx >>= 8;
|
|
b1 = edx & 0xff; edx >>= 8;
|
|
b2 = edx & 0xff; edx >>= 8;
|
|
b3 = edx;
|
|
|
|
RDX = (b0<<24) | (b1<<16) | (b2<<8) | b3;
|
|
#else
|
|
BX_INFO(("BSWAP_EDX: not implemented CPU <= 3"));
|
|
UndefinedOpcode(i);
|
|
#endif
|
|
}
|
|
|
|
void BX_CPU_C::BSWAP_EBX(bxInstruction_c *i)
|
|
{
|
|
#if (BX_CPU_LEVEL >= 4) || (BX_CPU_LEVEL_HACKED >= 4)
|
|
Bit32u ebx, b0, b1, b2, b3;
|
|
|
|
ebx = EBX;
|
|
b0 = ebx & 0xff; ebx >>= 8;
|
|
b1 = ebx & 0xff; ebx >>= 8;
|
|
b2 = ebx & 0xff; ebx >>= 8;
|
|
b3 = ebx;
|
|
|
|
RBX = (b0<<24) | (b1<<16) | (b2<<8) | b3;
|
|
#else
|
|
BX_INFO(("BSWAP_EBX: not implemented CPU <= 3"));
|
|
UndefinedOpcode(i);
|
|
#endif
|
|
}
|
|
|
|
void BX_CPU_C::BSWAP_ESP(bxInstruction_c *i)
|
|
{
|
|
#if (BX_CPU_LEVEL >= 4) || (BX_CPU_LEVEL_HACKED >= 4)
|
|
|
|
Bit32u esp, b0, b1, b2, b3;
|
|
|
|
esp = ESP;
|
|
b0 = esp & 0xff; esp >>= 8;
|
|
b1 = esp & 0xff; esp >>= 8;
|
|
b2 = esp & 0xff; esp >>= 8;
|
|
b3 = esp;
|
|
|
|
RSP = (b0<<24) | (b1<<16) | (b2<<8) | b3;
|
|
#else
|
|
BX_INFO(("BSWAP_ESP: not implemented CPU <= 3"));
|
|
UndefinedOpcode(i);
|
|
#endif
|
|
}
|
|
|
|
void BX_CPU_C::BSWAP_EBP(bxInstruction_c *i)
|
|
{
|
|
#if (BX_CPU_LEVEL >= 4) || (BX_CPU_LEVEL_HACKED >= 4)
|
|
|
|
Bit32u ebp, b0, b1, b2, b3;
|
|
|
|
ebp = EBP;
|
|
b0 = ebp & 0xff; ebp >>= 8;
|
|
b1 = ebp & 0xff; ebp >>= 8;
|
|
b2 = ebp & 0xff; ebp >>= 8;
|
|
b3 = ebp;
|
|
|
|
RBP = (b0<<24) | (b1<<16) | (b2<<8) | b3;
|
|
#else
|
|
BX_INFO(("BSWAP_EBP: not implemented CPU <= 3"));
|
|
UndefinedOpcode(i);
|
|
#endif
|
|
}
|
|
|
|
void BX_CPU_C::BSWAP_ESI(bxInstruction_c *i)
|
|
{
|
|
#if (BX_CPU_LEVEL >= 4) || (BX_CPU_LEVEL_HACKED >= 4)
|
|
|
|
Bit32u esi, b0, b1, b2, b3;
|
|
|
|
esi = ESI;
|
|
b0 = esi & 0xff; esi >>= 8;
|
|
b1 = esi & 0xff; esi >>= 8;
|
|
b2 = esi & 0xff; esi >>= 8;
|
|
b3 = esi;
|
|
|
|
RSI = (b0<<24) | (b1<<16) | (b2<<8) | b3;
|
|
#else
|
|
BX_INFO(("BSWAP_ESI: not implemented CPU <= 3"));
|
|
UndefinedOpcode(i);
|
|
#endif
|
|
}
|
|
|
|
void BX_CPU_C::BSWAP_EDI(bxInstruction_c *i)
|
|
{
|
|
#if (BX_CPU_LEVEL >= 4) || (BX_CPU_LEVEL_HACKED >= 4)
|
|
|
|
Bit32u edi, b0, b1, b2, b3;
|
|
|
|
edi = EDI;
|
|
b0 = edi & 0xff; edi >>= 8;
|
|
b1 = edi & 0xff; edi >>= 8;
|
|
b2 = edi & 0xff; edi >>= 8;
|
|
b3 = edi;
|
|
|
|
RDI = (b0<<24) | (b1<<16) | (b2<<8) | b3;
|
|
#else
|
|
BX_INFO(("BSWAP_EDI: not implemented CPU <= 3"));
|
|
UndefinedOpcode(i);
|
|
#endif
|
|
}
|
|
|
|
#if BX_SUPPORT_X86_64
|
|
void BX_CPU_C::BSWAP_RAX(bxInstruction_c *i)
|
|
{
|
|
Bit64u rax, b0, b1, b2, b3, b4, b5, b6, b7;
|
|
|
|
rax = RAX;
|
|
b0 = rax & 0xff; rax >>= 8;
|
|
b1 = rax & 0xff; rax >>= 8;
|
|
b2 = rax & 0xff; rax >>= 8;
|
|
b3 = rax & 0xff; rax >>= 8;
|
|
b4 = rax & 0xff; rax >>= 8;
|
|
b5 = rax & 0xff; rax >>= 8;
|
|
b6 = rax & 0xff; rax >>= 8;
|
|
b7 = rax;
|
|
|
|
RAX = (b0<<56) | (b1<<48) | (b2<<40) | (b3<<32) | (b4<<24) | (b4<<16) | (b4<<8) | b7;
|
|
}
|
|
|
|
void BX_CPU_C::BSWAP_RCX(bxInstruction_c *i)
|
|
{
|
|
Bit64u rcx, b0, b1, b2, b3, b4, b5, b6, b7;
|
|
|
|
rcx = RCX;
|
|
b0 = rcx & 0xff; rcx >>= 8;
|
|
b1 = rcx & 0xff; rcx >>= 8;
|
|
b2 = rcx & 0xff; rcx >>= 8;
|
|
b3 = rcx & 0xff; rcx >>= 8;
|
|
b4 = rcx & 0xff; rcx >>= 8;
|
|
b5 = rcx & 0xff; rcx >>= 8;
|
|
b6 = rcx & 0xff; rcx >>= 8;
|
|
b7 = rcx;
|
|
|
|
RCX = (b0<<56) | (b1<<48) | (b2<<40) | (b3<<32) | (b4<<24) | (b5<<16) | (b6<<8) | b7;
|
|
}
|
|
|
|
void BX_CPU_C::BSWAP_RDX(bxInstruction_c *i)
|
|
{
|
|
Bit64u rdx, b0, b1, b2, b3, b4, b5, b6, b7;
|
|
|
|
rdx = RDX;
|
|
b0 = rdx & 0xff; rdx >>= 8;
|
|
b1 = rdx & 0xff; rdx >>= 8;
|
|
b2 = rdx & 0xff; rdx >>= 8;
|
|
b3 = rdx & 0xff; rdx >>= 8;
|
|
b4 = rdx & 0xff; rdx >>= 8;
|
|
b5 = rdx & 0xff; rdx >>= 8;
|
|
b6 = rdx & 0xff; rdx >>= 8;
|
|
b7 = rdx;
|
|
|
|
RDX = (b0<<56) | (b1<<48) | (b2<<40) | (b3<<32) | (b4<<24) | (b5<<16) | (b6<<8) | b7;
|
|
}
|
|
|
|
void BX_CPU_C::BSWAP_RBX(bxInstruction_c *i)
|
|
{
|
|
Bit64u rbx, b0, b1, b2, b3, b4, b5, b6, b7;
|
|
|
|
rbx = RBX;
|
|
b0 = rbx & 0xff; rbx >>= 8;
|
|
b1 = rbx & 0xff; rbx >>= 8;
|
|
b2 = rbx & 0xff; rbx >>= 8;
|
|
b3 = rbx & 0xff; rbx >>= 8;
|
|
b4 = rbx & 0xff; rbx >>= 8;
|
|
b5 = rbx & 0xff; rbx >>= 8;
|
|
b6 = rbx & 0xff; rbx >>= 8;
|
|
b7 = rbx;
|
|
|
|
RBX = (b0<<56) | (b1<<48) | (b2<<40) | (b3<<32) | (b4<<24) | (b5<<16) | (b6<<8) | b7;
|
|
}
|
|
|
|
void BX_CPU_C::BSWAP_RSP(bxInstruction_c *i)
|
|
{
|
|
Bit64u rsp, b0, b1, b2, b3, b4, b5, b6, b7;
|
|
|
|
rsp = RSP;
|
|
b0 = rsp & 0xff; rsp >>= 8;
|
|
b1 = rsp & 0xff; rsp >>= 8;
|
|
b2 = rsp & 0xff; rsp >>= 8;
|
|
b3 = rsp & 0xff; rsp >>= 8;
|
|
b4 = rsp & 0xff; rsp >>= 8;
|
|
b5 = rsp & 0xff; rsp >>= 8;
|
|
b6 = rsp & 0xff; rsp >>= 8;
|
|
b7 = rsp;
|
|
|
|
RSP = (b0<<56) | (b1<<48) | (b2<<40) | (b3<<32) | (b4<<24) | (b5<<16) | (b6<<8) | b7;
|
|
}
|
|
|
|
void BX_CPU_C::BSWAP_RBP(bxInstruction_c *i)
|
|
{
|
|
Bit64u rbp, b0, b1, b2, b3, b4, b5, b6, b7;
|
|
|
|
rbp = RBP;
|
|
b0 = rbp & 0xff; rbp >>= 8;
|
|
b1 = rbp & 0xff; rbp >>= 8;
|
|
b2 = rbp & 0xff; rbp >>= 8;
|
|
b3 = rbp & 0xff; rbp >>= 8;
|
|
b4 = rbp & 0xff; rbp >>= 8;
|
|
b5 = rbp & 0xff; rbp >>= 8;
|
|
b6 = rbp & 0xff; rbp >>= 8;
|
|
b7 = rbp;
|
|
|
|
RBP = (b0<<56) | (b1<<48) | (b2<<40) | (b3<<32) | (b4<<24) | (b5<<16) | (b6<<8) | b7;
|
|
}
|
|
|
|
void BX_CPU_C::BSWAP_RSI(bxInstruction_c *i)
|
|
{
|
|
Bit64u rsi, b0, b1, b2, b3, b4, b5, b6, b7;
|
|
|
|
rsi = RSI;
|
|
b0 = rsi & 0xff; rsi >>= 8;
|
|
b1 = rsi & 0xff; rsi >>= 8;
|
|
b2 = rsi & 0xff; rsi >>= 8;
|
|
b3 = rsi & 0xff; rsi >>= 8;
|
|
b4 = rsi & 0xff; rsi >>= 8;
|
|
b5 = rsi & 0xff; rsi >>= 8;
|
|
b6 = rsi & 0xff; rsi >>= 8;
|
|
b7 = rsi;
|
|
|
|
RSI = (b0<<56) | (b1<<48) | (b2<<40) | (b3<<32) | (b4<<24) | (b5<<16) | (b6<<8) | b7;
|
|
}
|
|
|
|
void BX_CPU_C::BSWAP_RDI(bxInstruction_c *i)
|
|
{
|
|
Bit64u rdi, b0, b1, b2, b3, b4, b5, b6, b7;
|
|
|
|
rdi = RDI;
|
|
b0 = rdi & 0xff; rdi >>= 8;
|
|
b1 = rdi & 0xff; rdi >>= 8;
|
|
b2 = rdi & 0xff; rdi >>= 8;
|
|
b3 = rdi & 0xff; rdi >>= 8;
|
|
b4 = rdi & 0xff; rdi >>= 8;
|
|
b5 = rdi & 0xff; rdi >>= 8;
|
|
b6 = rdi & 0xff; rdi >>= 8;
|
|
b7 = rdi;
|
|
|
|
RDI = (b0<<56) | (b1<<48) | (b2<<40) | (b3<<32) | (b4<<24) | (b5<<16) | (b6<<8) | b7;
|
|
}
|
|
#endif // #if BX_SUPPORT_X86_64
|
|
|
|
void BX_CPU_C::BT_EwGw(bxInstruction_c *i)
|
|
{
|
|
bx_address op1_addr;
|
|
Bit16u op1_16, op2_16, index;
|
|
Bit32s displacement32;
|
|
|
|
/* op2_16 is a register, op2_addr is an index of a register */
|
|
op2_16 = BX_READ_16BIT_REG(i->nnn());
|
|
|
|
/* op1_16 is a register or memory reference */
|
|
if (i->modC0()) {
|
|
op1_16 = BX_READ_16BIT_REG(i->rm());
|
|
op2_16 &= 0x0f;
|
|
set_CF((op1_16 >> op2_16) & 0x01);
|
|
return;
|
|
}
|
|
|
|
index = op2_16 & 0x0f;
|
|
displacement32 = ((Bit16s) (op2_16&0xfff0)) / 16;
|
|
op1_addr = RMAddr(i) + 2 * displacement32;
|
|
|
|
/* pointer, segment address pair */
|
|
read_virtual_word(i->seg(), op1_addr, &op1_16);
|
|
|
|
set_CF((op1_16 >> index) & 0x01);
|
|
}
|
|
|
|
void BX_CPU_C::BT_EdGd(bxInstruction_c *i)
|
|
{
|
|
bx_address op1_addr;
|
|
Bit32u op1_32, op2_32, index;
|
|
Bit32s displacement32;
|
|
|
|
/* op2_32 is a register, op2_addr is an index of a register */
|
|
op2_32 = BX_READ_32BIT_REG(i->nnn());
|
|
|
|
/* op1_32 is a register or memory reference */
|
|
if (i->modC0()) {
|
|
op1_32 = BX_READ_32BIT_REG(i->rm());
|
|
op2_32 &= 0x1f;
|
|
set_CF((op1_32 >> op2_32) & 0x01);
|
|
return;
|
|
}
|
|
|
|
index = op2_32 & 0x1f;
|
|
displacement32 = ((Bit32s) (op2_32&0xffffffe0)) / 32;
|
|
op1_addr = RMAddr(i) + 4 * displacement32;
|
|
|
|
/* pointer, segment address pair */
|
|
read_virtual_dword(i->seg(), op1_addr, &op1_32);
|
|
|
|
set_CF((op1_32 >> index) & 0x01);
|
|
}
|
|
|
|
#if BX_SUPPORT_X86_64
|
|
void BX_CPU_C::BT_EqGq(bxInstruction_c *i)
|
|
{
|
|
bx_address op1_addr;
|
|
Bit64u op1_64, op2_64;
|
|
Bit64s displacement64;
|
|
Bit64u index;
|
|
|
|
/* op2_64 is a register, op2_addr is an index of a register */
|
|
op2_64 = BX_READ_64BIT_REG(i->nnn());
|
|
|
|
/* op1_64 is a register or memory reference */
|
|
if (i->modC0()) {
|
|
op1_64 = BX_READ_64BIT_REG(i->rm());
|
|
op2_64 &= 0x3f;
|
|
set_CF((op1_64 >> op2_64) & 0x01);
|
|
return;
|
|
}
|
|
|
|
index = op2_64 & 0x3f;
|
|
displacement64 = ((Bit64s) (op2_64 & BX_CONST64(0xffffffffffffffc0))) / 64;
|
|
op1_addr = RMAddr(i) + 8 * displacement64;
|
|
|
|
/* pointer, segment address pair */
|
|
read_virtual_qword(i->seg(), op1_addr, &op1_64);
|
|
|
|
set_CF((op1_64 >> index) & 0x01);
|
|
}
|
|
#endif
|
|
|
|
void BX_CPU_C::BTS_EwGw(bxInstruction_c *i)
|
|
{
|
|
bx_address op1_addr;
|
|
Bit16u op1_16, op2_16, bit_i, index;
|
|
Bit32s displacement32;
|
|
|
|
/* op2_16 is a register, op2_addr is an index of a register */
|
|
op2_16 = BX_READ_16BIT_REG(i->nnn());
|
|
|
|
/* op1_16 is a register or memory reference */
|
|
if (i->modC0()) {
|
|
op1_16 = BX_READ_16BIT_REG(i->rm());
|
|
op2_16 &= 0x0f;
|
|
set_CF((op1_16 >> op2_16) & 0x01);
|
|
op1_16 |= (((Bit16u) 1) << op2_16);
|
|
|
|
/* now write diff back to destination */
|
|
BX_WRITE_16BIT_REG(i->rm(), op1_16);
|
|
return;
|
|
}
|
|
|
|
index = op2_16 & 0x0f;
|
|
displacement32 = ((Bit16s) (op2_16 & 0xfff0)) / 16;
|
|
op1_addr = RMAddr(i) + 2 * displacement32;
|
|
|
|
/* pointer, segment address pair */
|
|
read_RMW_virtual_word(i->seg(), op1_addr, &op1_16);
|
|
|
|
bit_i = (op1_16 >> index) & 0x01;
|
|
op1_16 |= (((Bit16u) 1) << index);
|
|
|
|
Write_RMW_virtual_word(op1_16);
|
|
|
|
set_CF(bit_i);
|
|
}
|
|
|
|
void BX_CPU_C::BTS_EdGd(bxInstruction_c *i)
|
|
{
|
|
bx_address op1_addr;
|
|
Bit32u op1_32, op2_32, bit_i, index;
|
|
Bit32s displacement32;
|
|
|
|
/* op2_32 is a register, op2_addr is an index of a register */
|
|
op2_32 = BX_READ_32BIT_REG(i->nnn());
|
|
|
|
/* op1_32 is a register or memory reference */
|
|
if (i->modC0()) {
|
|
op1_32 = BX_READ_32BIT_REG(i->rm());
|
|
op2_32 &= 0x1f;
|
|
set_CF((op1_32 >> op2_32) & 0x01);
|
|
op1_32 |= (((Bit32u) 1) << op2_32);
|
|
|
|
/* now write diff back to destination */
|
|
BX_WRITE_32BIT_REGZ(i->rm(), op1_32);
|
|
return;
|
|
}
|
|
|
|
index = op2_32 & 0x1f;
|
|
displacement32 = ((Bit32s) (op2_32&0xffffffe0)) / 32;
|
|
op1_addr = RMAddr(i) + 4 * displacement32;
|
|
|
|
/* pointer, segment address pair */
|
|
read_RMW_virtual_dword(i->seg(), op1_addr, &op1_32);
|
|
|
|
bit_i = (op1_32 >> index) & 0x01;
|
|
op1_32 |= (((Bit32u) 1) << index);
|
|
|
|
Write_RMW_virtual_dword(op1_32);
|
|
|
|
set_CF(bit_i);
|
|
}
|
|
|
|
#if BX_SUPPORT_X86_64
|
|
void BX_CPU_C::BTS_EqGq(bxInstruction_c *i)
|
|
{
|
|
bx_address op1_addr;
|
|
Bit64u op1_64, op2_64, index;
|
|
Bit64s displacement64;
|
|
Bit64u bit_i;
|
|
|
|
/* op2_64 is a register, op2_addr is an index of a register */
|
|
op2_64 = BX_READ_64BIT_REG(i->nnn());
|
|
|
|
/* op1_64 is a register or memory reference */
|
|
if (i->modC0()) {
|
|
op1_64 = BX_READ_64BIT_REG(i->rm());
|
|
op2_64 &= 0x3f;
|
|
set_CF((op1_64 >> op2_64) & 0x01);
|
|
op1_64 |= (((Bit64u) 1) << op2_64);
|
|
|
|
/* now write diff back to destination */
|
|
BX_WRITE_64BIT_REG(i->rm(), op1_64);
|
|
return;
|
|
}
|
|
|
|
index = op2_64 & 0x3f;
|
|
displacement64 = ((Bit64s) (op2_64 & BX_CONST64(0xffffffffffffffc0))) / 64;
|
|
op1_addr = RMAddr(i) + 8 * displacement64;
|
|
|
|
/* pointer, segment address pair */
|
|
read_RMW_virtual_qword(i->seg(), op1_addr, &op1_64);
|
|
|
|
bit_i = (op1_64 >> index) & 0x01;
|
|
op1_64 |= (((Bit64u) 1) << index);
|
|
|
|
Write_RMW_virtual_qword(op1_64);
|
|
|
|
set_CF(bit_i);
|
|
}
|
|
#endif
|
|
|
|
void BX_CPU_C::BTR_EwGw(bxInstruction_c *i)
|
|
{
|
|
bx_address op1_addr;
|
|
Bit16u op1_16, op2_16, index;
|
|
Bit32s displacement32;
|
|
|
|
/* op2_16 is a register, op2_addr is an index of a register */
|
|
op2_16 = BX_READ_16BIT_REG(i->nnn());
|
|
|
|
/* op1_16 is a register or memory reference */
|
|
if (i->modC0()) {
|
|
op1_16 = BX_READ_16BIT_REG(i->rm());
|
|
op2_16 &= 0x0f;
|
|
set_CF((op1_16 >> op2_16) & 0x01);
|
|
op1_16 &= ~(((Bit16u) 1) << op2_16);
|
|
|
|
/* now write diff back to destination */
|
|
BX_WRITE_16BIT_REG(i->rm(), op1_16);
|
|
return;
|
|
}
|
|
|
|
index = op2_16 & 0x0f;
|
|
displacement32 = ((Bit16s) (op2_16&0xfff0)) / 16;
|
|
op1_addr = RMAddr(i) + 2 * displacement32;
|
|
|
|
/* pointer, segment address pair */
|
|
read_RMW_virtual_word(i->seg(), op1_addr, &op1_16);
|
|
|
|
bx_bool temp_cf = (op1_16 >> index) & 0x01;
|
|
op1_16 &= ~(((Bit16u) 1) << index);
|
|
|
|
/* now write back to destination */
|
|
Write_RMW_virtual_word(op1_16);
|
|
|
|
set_CF(temp_cf);
|
|
}
|
|
|
|
void BX_CPU_C::BTR_EdGd(bxInstruction_c *i)
|
|
{
|
|
bx_address op1_addr;
|
|
Bit32u op1_32, op2_32, index;
|
|
Bit32s displacement32;
|
|
|
|
/* op2_32 is a register, op2_addr is an index of a register */
|
|
op2_32 = BX_READ_32BIT_REG(i->nnn());
|
|
|
|
/* op1_32 is a register or memory reference */
|
|
if (i->modC0()) {
|
|
op1_32 = BX_READ_32BIT_REG(i->rm());
|
|
op2_32 &= 0x1f;
|
|
set_CF((op1_32 >> op2_32) & 0x01);
|
|
op1_32 &= ~(((Bit32u) 1) << op2_32);
|
|
|
|
/* now write diff back to destination */
|
|
BX_WRITE_32BIT_REGZ(i->rm(), op1_32);
|
|
return;
|
|
}
|
|
|
|
index = op2_32 & 0x1f;
|
|
displacement32 = ((Bit32s) (op2_32&0xffffffe0)) / 32;
|
|
op1_addr = RMAddr(i) + 4 * displacement32;
|
|
|
|
/* pointer, segment address pair */
|
|
read_RMW_virtual_dword(i->seg(), op1_addr, &op1_32);
|
|
|
|
bx_bool temp_cf = (op1_32 >> index) & 0x01;
|
|
op1_32 &= ~(((Bit32u) 1) << index);
|
|
|
|
/* now write back to destination */
|
|
Write_RMW_virtual_dword(op1_32);
|
|
|
|
set_CF(temp_cf);
|
|
}
|
|
|
|
#if BX_SUPPORT_X86_64
|
|
void BX_CPU_C::BTR_EqGq(bxInstruction_c *i)
|
|
{
|
|
bx_address op1_addr;
|
|
Bit64u op1_64, op2_64, index;
|
|
Bit64s displacement64;
|
|
|
|
/* op2_64 is a register, op2_addr is an index of a register */
|
|
op2_64 = BX_READ_64BIT_REG(i->nnn());
|
|
|
|
/* op1_64 is a register or memory reference */
|
|
if (i->modC0()) {
|
|
op1_64 = BX_READ_64BIT_REG(i->rm());
|
|
op2_64 &= 0x3f;
|
|
set_CF((op1_64 >> op2_64) & 0x01);
|
|
op1_64 &= ~(((Bit64u) 1) << op2_64);
|
|
|
|
/* now write diff back to destination */
|
|
BX_WRITE_64BIT_REG(i->rm(), op1_64);
|
|
return;
|
|
}
|
|
|
|
index = op2_64 & 0x3f;
|
|
displacement64 = ((Bit64s) (op2_64 & BX_CONST64(0xffffffffffffffc0))) / 64;
|
|
op1_addr = RMAddr(i) + 8 * displacement64;
|
|
|
|
/* pointer, segment address pair */
|
|
read_RMW_virtual_qword(i->seg(), op1_addr, &op1_64);
|
|
|
|
bx_bool temp_cf = (op1_64 >> index) & 0x01;
|
|
op1_64 &= ~(((Bit64u) 1) << index);
|
|
|
|
/* now write back to destination */
|
|
Write_RMW_virtual_qword(op1_64);
|
|
|
|
set_CF(temp_cf);
|
|
}
|
|
#endif
|
|
|
|
void BX_CPU_C::BTC_EwGw(bxInstruction_c *i)
|
|
{
|
|
bx_address op1_addr;
|
|
Bit16u op1_16, op2_16, index_16;
|
|
Bit16s displacement16;
|
|
|
|
op2_16 = BX_READ_16BIT_REG(i->nnn());
|
|
index_16 = op2_16 & 0x0f;
|
|
|
|
/* op1_16 is a register or memory reference */
|
|
if (i->modC0()) {
|
|
op1_16 = BX_READ_16BIT_REG(i->rm());
|
|
op1_addr = 0; // keep compiler happy
|
|
}
|
|
else {
|
|
displacement16 = ((Bit16s) (op2_16 & 0xfff0)) / 16;
|
|
op1_addr = RMAddr(i) + 2 * displacement16;
|
|
read_RMW_virtual_word(i->seg(), op1_addr, &op1_16);
|
|
}
|
|
|
|
bx_bool temp_CF = (op1_16 >> index_16) & 0x01;
|
|
op1_16 ^= (((Bit16u) 1) << index_16); /* toggle bit */
|
|
set_CF(temp_CF);
|
|
|
|
/* now write diff back to destination */
|
|
if (i->modC0()) {
|
|
BX_WRITE_16BIT_REG(i->rm(), op1_16);
|
|
}
|
|
else {
|
|
Write_RMW_virtual_word(op1_16);
|
|
}
|
|
|
|
set_CF(temp_CF);
|
|
}
|
|
|
|
void BX_CPU_C::BTC_EdGd(bxInstruction_c *i)
|
|
{
|
|
bx_address op1_addr;
|
|
Bit32u op1_32, op2_32, index_32;
|
|
Bit32s displacement32;
|
|
|
|
op2_32 = BX_READ_32BIT_REG(i->nnn());
|
|
index_32 = op2_32 & 0x1f;
|
|
|
|
/* op1_32 is a register or memory reference */
|
|
if (i->modC0()) {
|
|
op1_32 = BX_READ_32BIT_REG(i->rm());
|
|
op1_addr = 0; // keep compiler happy
|
|
}
|
|
else {
|
|
displacement32 = ((Bit32s) (op2_32 & 0xffffffe0)) / 32;
|
|
op1_addr = RMAddr(i) + 4 * displacement32;
|
|
read_RMW_virtual_dword(i->seg(), op1_addr, &op1_32);
|
|
}
|
|
|
|
bx_bool temp_CF = (op1_32 >> index_32) & 0x01;
|
|
op1_32 ^= (((Bit32u) 1) << index_32); /* toggle bit */
|
|
set_CF(temp_CF);
|
|
|
|
/* now write diff back to destination */
|
|
if (i->modC0()) {
|
|
BX_WRITE_32BIT_REGZ(i->rm(), op1_32);
|
|
}
|
|
else {
|
|
Write_RMW_virtual_dword(op1_32);
|
|
}
|
|
}
|
|
|
|
#if BX_SUPPORT_X86_64
|
|
void BX_CPU_C::BTC_EqGq(bxInstruction_c *i)
|
|
{
|
|
bx_address op1_addr;
|
|
Bit64u op1_64, op2_64;
|
|
Bit64s displacement64;
|
|
Bit64u index;
|
|
|
|
op2_64 = BX_READ_64BIT_REG(i->nnn());
|
|
index = op2_64 & 0x3f;
|
|
|
|
/* op1_64 is a register or memory reference */
|
|
if (i->modC0()) {
|
|
op1_64 = BX_READ_64BIT_REG(i->rm());
|
|
op1_addr = 0; // keep compiler happy
|
|
}
|
|
else {
|
|
displacement64 = ((Bit64s) (op2_64 & BX_CONST64(0xffffffffffffffc0))) / 64;
|
|
op1_addr = RMAddr(i) + 8 * displacement64;
|
|
read_RMW_virtual_qword(i->seg(), op1_addr, &op1_64);
|
|
}
|
|
|
|
bx_bool temp_CF = (op1_64 >> index) & 0x01;
|
|
op1_64 ^= (((Bit64u) 1) << index); /* toggle bit */
|
|
set_CF(temp_CF);
|
|
|
|
/* now write diff back to destination */
|
|
if (i->modC0()) {
|
|
BX_WRITE_64BIT_REG(i->rm(), op1_64);
|
|
}
|
|
else {
|
|
Write_RMW_virtual_qword(op1_64);
|
|
}
|
|
}
|
|
#endif
|
|
|
|
void BX_CPU_C::BT_EvIb(bxInstruction_c *i)
|
|
{
|
|
#if BX_SUPPORT_X86_64
|
|
if (i->os64L()) { /* 64 bit operand size mode */
|
|
/* for 64 bit operand size mode */
|
|
Bit64u op1_64;
|
|
|
|
Bit8u op2_8 = i->Ib() & 0x3f;
|
|
|
|
/* op1_64 is a register or memory reference */
|
|
if (i->modC0()) {
|
|
op1_64 = BX_READ_64BIT_REG(i->rm());
|
|
}
|
|
else {
|
|
/* pointer, segment address pair */
|
|
read_virtual_qword(i->seg(), RMAddr(i), &op1_64);
|
|
}
|
|
|
|
set_CF((op1_64 >> op2_8) & 0x01);
|
|
}
|
|
else
|
|
#endif // #if BX_SUPPORT_X86_64
|
|
if (i->os32L()) { /* 32 bit operand size mode */
|
|
/* for 32 bit operand size mode */
|
|
Bit32u op1_32;
|
|
|
|
Bit8u op2_8 = i->Ib() & 0x1f;
|
|
|
|
/* op1_32 is a register or memory reference */
|
|
if (i->modC0()) {
|
|
op1_32 = BX_READ_32BIT_REG(i->rm());
|
|
}
|
|
else {
|
|
/* pointer, segment address pair */
|
|
read_virtual_dword(i->seg(), RMAddr(i), &op1_32);
|
|
}
|
|
|
|
set_CF((op1_32 >> op2_8) & 0x01);
|
|
}
|
|
else { /* 16 bit operand size mode */
|
|
Bit16u op1_16;
|
|
|
|
Bit8u op2_8 = i->Ib() & 0xf;
|
|
|
|
/* op1_16 is a register or memory reference */
|
|
if (i->modC0()) {
|
|
op1_16 = BX_READ_16BIT_REG(i->rm());
|
|
}
|
|
else {
|
|
/* pointer, segment address pair */
|
|
read_virtual_word(i->seg(), RMAddr(i), &op1_16);
|
|
}
|
|
|
|
set_CF((op1_16 >> op2_8) & 0x01);
|
|
}
|
|
}
|
|
|
|
void BX_CPU_C::BTS_EvIb(bxInstruction_c *i)
|
|
{
|
|
#if BX_SUPPORT_X86_64
|
|
if (i->os64L()) { /* 64 bit operand size mode */
|
|
/* for 64 bit operand size mode */
|
|
Bit64u op1_64;
|
|
|
|
Bit8u op2_8 = i->Ib() & 0x3f;
|
|
|
|
/* op1_64 is a register or memory reference */
|
|
if (i->modC0()) {
|
|
op1_64 = BX_READ_64BIT_REG(i->rm());
|
|
}
|
|
else {
|
|
/* pointer, segment address pair */
|
|
read_RMW_virtual_qword(i->seg(), RMAddr(i), &op1_64);
|
|
}
|
|
|
|
bx_bool temp_CF = (op1_64 >> op2_8) & 0x01;
|
|
op1_64 |= (((Bit64u) 1) << op2_8);
|
|
|
|
/* now write diff back to destination */
|
|
if (i->modC0()) {
|
|
BX_WRITE_64BIT_REG(i->rm(), op1_64);
|
|
}
|
|
else {
|
|
Write_RMW_virtual_qword(op1_64);
|
|
}
|
|
|
|
set_CF(temp_CF);
|
|
}
|
|
else
|
|
#endif // #if BX_SUPPORT_X86_64
|
|
if (i->os32L()) { /* 32 bit operand size mode */
|
|
/* for 32 bit operand size mode */
|
|
Bit32u op1_32;
|
|
|
|
Bit8u op2_8 = i->Ib() & 0x1f;
|
|
|
|
/* op1_32 is a register or memory reference */
|
|
if (i->modC0()) {
|
|
op1_32 = BX_READ_32BIT_REG(i->rm());
|
|
}
|
|
else {
|
|
/* pointer, segment address pair */
|
|
read_RMW_virtual_dword(i->seg(), RMAddr(i), &op1_32);
|
|
}
|
|
|
|
bx_bool temp_CF = (op1_32 >> op2_8) & 0x01;
|
|
op1_32 |= (((Bit32u) 1) << op2_8);
|
|
|
|
/* now write diff back to destination */
|
|
if (i->modC0()) {
|
|
BX_WRITE_32BIT_REGZ(i->rm(), op1_32);
|
|
}
|
|
else {
|
|
Write_RMW_virtual_dword(op1_32);
|
|
}
|
|
|
|
set_CF(temp_CF);
|
|
}
|
|
else { /* 16 bit operand size mode */
|
|
Bit16u op1_16;
|
|
|
|
Bit8u op2_8 = i->Ib() & 0xf;
|
|
|
|
/* op1_16 is a register or memory reference */
|
|
if (i->modC0()) {
|
|
op1_16 = BX_READ_16BIT_REG(i->rm());
|
|
}
|
|
else {
|
|
/* pointer, segment address pair */
|
|
read_RMW_virtual_word(i->seg(), RMAddr(i), &op1_16);
|
|
}
|
|
|
|
bx_bool temp_CF = (op1_16 >> op2_8) & 0x01;
|
|
op1_16 |= (((Bit16u) 1) << op2_8);
|
|
|
|
/* now write diff back to destination */
|
|
if (i->modC0()) {
|
|
BX_WRITE_16BIT_REG(i->rm(), op1_16);
|
|
}
|
|
else {
|
|
Write_RMW_virtual_word(op1_16);
|
|
}
|
|
|
|
set_CF(temp_CF);
|
|
}
|
|
}
|
|
|
|
void BX_CPU_C::BTC_EvIb(bxInstruction_c *i)
|
|
{
|
|
#if BX_SUPPORT_X86_64
|
|
if (i->os64L()) { /* 64 bit operand size mode */
|
|
/* for 64 bit operand size mode */
|
|
Bit64u op1_64;
|
|
|
|
Bit8u op2_8 = i->Ib() & 0x3f;
|
|
|
|
/* op1_64 is a register or memory reference */
|
|
if (i->modC0()) {
|
|
op1_64 = BX_READ_64BIT_REG(i->rm());
|
|
}
|
|
else {
|
|
/* pointer, segment address pair */
|
|
read_RMW_virtual_qword(i->seg(), RMAddr(i), &op1_64);
|
|
}
|
|
|
|
bx_bool temp_CF = (op1_64 >> op2_8) & 0x01;
|
|
op1_64 ^= (((Bit64u) 1) << op2_8); /* toggle bit */
|
|
set_CF(temp_CF);
|
|
|
|
/* now write diff back to destination */
|
|
if (i->modC0()) {
|
|
BX_WRITE_64BIT_REG(i->rm(), op1_64);
|
|
}
|
|
else {
|
|
Write_RMW_virtual_qword(op1_64);
|
|
}
|
|
}
|
|
else
|
|
#endif // #if BX_SUPPORT_X86_64
|
|
if (i->os32L()) { /* 32 bit operand size mode */
|
|
/* for 32 bit operand size mode */
|
|
Bit32u op1_32;
|
|
|
|
Bit8u op2_8 = i->Ib() & 0x1f;
|
|
|
|
/* op1_32 is a register or memory reference */
|
|
if (i->modC0()) {
|
|
op1_32 = BX_READ_32BIT_REG(i->rm());
|
|
}
|
|
else {
|
|
/* pointer, segment address pair */
|
|
read_RMW_virtual_dword(i->seg(), RMAddr(i), &op1_32);
|
|
}
|
|
|
|
bx_bool temp_CF = (op1_32 >> op2_8) & 0x01;
|
|
op1_32 ^= (((Bit32u) 1) << op2_8); /* toggle bit */
|
|
set_CF(temp_CF);
|
|
|
|
/* now write diff back to destination */
|
|
if (i->modC0()) {
|
|
BX_WRITE_32BIT_REGZ(i->rm(), op1_32);
|
|
}
|
|
else {
|
|
Write_RMW_virtual_dword(op1_32);
|
|
}
|
|
}
|
|
else { /* 16 bit operand size mode */
|
|
Bit16u op1_16;
|
|
|
|
Bit8u op2_8 = i->Ib() & 0xf;
|
|
|
|
/* op1_16 is a register or memory reference */
|
|
if (i->modC0()) {
|
|
op1_16 = BX_READ_16BIT_REG(i->rm());
|
|
}
|
|
else {
|
|
/* pointer, segment address pair */
|
|
read_RMW_virtual_word(i->seg(), RMAddr(i), &op1_16);
|
|
}
|
|
|
|
bx_bool temp_CF = (op1_16 >> op2_8) & 0x01;
|
|
op1_16 ^= (((Bit16u) 1) << op2_8); /* toggle bit */
|
|
set_CF(temp_CF);
|
|
|
|
/* now write diff back to destination */
|
|
if (i->modC0()) {
|
|
BX_WRITE_16BIT_REG(i->rm(), op1_16);
|
|
}
|
|
else {
|
|
Write_RMW_virtual_word(op1_16);
|
|
}
|
|
}
|
|
}
|
|
|
|
void BX_CPU_C::BTR_EvIb(bxInstruction_c *i)
|
|
{
|
|
#if BX_SUPPORT_X86_64
|
|
if (i->os64L()) { /* 64 bit operand size mode */
|
|
/* for 64 bit operand size mode */
|
|
Bit64u op1_64;
|
|
|
|
Bit8u op2_8 = i->Ib() & 0x3f;
|
|
|
|
/* op1_64 is a register or memory reference */
|
|
if (i->modC0()) {
|
|
op1_64 = BX_READ_64BIT_REG(i->rm());
|
|
}
|
|
else {
|
|
/* pointer, segment address pair */
|
|
read_RMW_virtual_qword(i->seg(), RMAddr(i), &op1_64);
|
|
}
|
|
|
|
bx_bool temp_CF = (op1_64 >> op2_8) & 0x01;
|
|
op1_64 &= ~(((Bit64u) 1) << op2_8);
|
|
|
|
/* now write diff back to destination */
|
|
if (i->modC0()) {
|
|
BX_WRITE_64BIT_REG(i->rm(), op1_64);
|
|
}
|
|
else {
|
|
Write_RMW_virtual_qword(op1_64);
|
|
}
|
|
|
|
set_CF(temp_CF);
|
|
}
|
|
else
|
|
#endif // #if BX_SUPPORT_X86_64
|
|
if (i->os32L()) { /* 32 bit operand size mode */
|
|
/* for 32 bit operand size mode */
|
|
Bit32u op1_32;
|
|
|
|
Bit8u op2_8 = i->Ib() & 0x1f;
|
|
|
|
/* op1_32 is a register or memory reference */
|
|
if (i->modC0()) {
|
|
op1_32 = BX_READ_32BIT_REG(i->rm());
|
|
}
|
|
else {
|
|
/* pointer, segment address pair */
|
|
read_RMW_virtual_dword(i->seg(), RMAddr(i), &op1_32);
|
|
}
|
|
|
|
bx_bool temp_CF = (op1_32 >> op2_8) & 0x01;
|
|
op1_32 &= ~(((Bit32u) 1) << op2_8);
|
|
|
|
/* now write diff back to destination */
|
|
if (i->modC0()) {
|
|
BX_WRITE_32BIT_REGZ(i->rm(), op1_32);
|
|
}
|
|
else {
|
|
Write_RMW_virtual_dword(op1_32);
|
|
}
|
|
|
|
set_CF(temp_CF);
|
|
}
|
|
else { /* 16 bit operand size mode */
|
|
Bit16u op1_16;
|
|
|
|
Bit8u op2_8 = i->Ib() & 0xf;
|
|
|
|
/* op1_16 is a register or memory reference */
|
|
if (i->modC0()) {
|
|
op1_16 = BX_READ_16BIT_REG(i->rm());
|
|
}
|
|
else {
|
|
/* pointer, segment address pair */
|
|
read_RMW_virtual_word(i->seg(), RMAddr(i), &op1_16);
|
|
}
|
|
|
|
bx_bool temp_CF = (op1_16 >> op2_8) & 0x01;
|
|
op1_16 &= ~(((Bit16u) 1) << op2_8);
|
|
|
|
/* now write diff back to destination */
|
|
if (i->modC0()) {
|
|
BX_WRITE_16BIT_REG(i->rm(), op1_16);
|
|
}
|
|
else {
|
|
Write_RMW_virtual_word(op1_16);
|
|
}
|
|
|
|
set_CF(temp_CF);
|
|
}
|
|
}
|
|
|
|
#endif /* BX_CPU_LEVEL >= 3 */
|