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Bochs/bochs/cpu/decoder
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Stanislav Shwartsman 0e4524f38f Implemented CMPccXADD instructions
2022-10-08 20:04:22 +03:00
..
decoder.h Implemented CMPccXADD instructions 2022-10-08 20:04:22 +03:00
disasm.cc remove trailing whitespace from source files 2022-08-23 21:46:04 +03:00
fetchdecode32.cc remove trailing whitespace from source files 2022-08-23 21:46:04 +03:00
fetchdecode64.cc remove trailing whitespace from source files 2022-08-23 21:46:04 +03:00
fetchdecode_avx.h Implemented CMPccXADD instructions 2022-10-08 20:04:22 +03:00
fetchdecode_evex.h remove trailing whitespace from source files 2022-08-23 21:46:04 +03:00
fetchdecode_opmap_0f3a.h fix decoder: SHA1RNDS4 instruction should be with no SSE prefix 2019-12-27 13:08:20 +00:00
fetchdecode_opmap_0f38.h Add initial implementation of the CET (Control Flow Enforcement Technology) emulation according to SDM071 2019-12-20 07:42:07 +00:00
fetchdecode_opmap.h implemented WRMSRNS extension - Non Serializing version of WRMSR opcode 2022-10-02 22:16:02 +03:00
fetchdecode_x87.h remove trailing whitespace from source files 2022-08-23 21:46:04 +03:00
fetchdecode_xop.h remove trailing whitespace from source files 2022-08-23 21:46:04 +03:00
fetchdecode.h remove trailing whitespace from source files 2022-08-23 21:46:04 +03:00
ia_opcodes.def Implemented CMPccXADD instructions 2022-10-08 20:04:22 +03:00
ia_opcodes.h add into ia_opcodes.def disasm field for every instruction 2020-03-28 14:23:54 +00:00
instr.h remove trailing whitespace from source files 2022-08-23 21:46:04 +03:00