367 lines
12 KiB
C++
367 lines
12 KiB
C++
/////////////////////////////////////////////////////////////////////////
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// $Id$
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/////////////////////////////////////////////////////////////////////////
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//
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// Copyright (c) 2022 Stanislav Shwartsman
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// Written by Stanislav Shwartsman [sshwarts at sourceforge net]
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//
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// This library is free software; you can redistribute it and/or
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// modify it under the terms of the GNU Lesser General Public
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// License as published by the Free Software Foundation; either
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// version 2 of the License, or (at your option) any later version.
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//
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// This library is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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// Lesser General Public License for more details.
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//
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// You should have received a copy of the GNU Lesser General Public
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// License along with this library; if not, write to the Free Software
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// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA B 02110-1301 USA
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/////////////////////////////////////////////////////////////////////////
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#define NEED_CPU_REG_SHORTCUTS 1
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#include "bochs.h"
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#include "cpu.h"
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#define LOG_THIS BX_CPU_THIS_PTR
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#if BX_SUPPORT_AVX
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void BX_CPP_AttrRegparmN(1) BX_CPU_C::CMPBEXADD_EdGdBd(bxInstruction_c *i)
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{
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Bit32u op2_32 = BX_READ_32BIT_REG(i->src1());
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Bit32u op3_32 = BX_READ_32BIT_REG(i->src2());
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bx_address eaddr = BX_CPU_RESOLVE_ADDR(i), laddr = get_laddr(i->seg(), eaddr);
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if (laddr & 3) {
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BX_ERROR(("%s: #GP misaligned access", i->getIaOpcodeNameShort()));
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exception(BX_GP_EXCEPTION, 0);
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}
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Bit32u op1_32 = read_RMW_linear_dword(i->seg(), laddr);
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Bit32u diff_32 = op1_32 - op2_32;
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SET_FLAGS_OSZAPC_SUB_32(op1_32, op2_32, diff_32);
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write_RMW_linear_dword((get_CF() || get_ZF()) ? op1_32 + op3_32 : op1_32);
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BX_WRITE_32BIT_REGZ(i->src1(), op1_32);
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BX_NEXT_INSTR(i);
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}
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void BX_CPP_AttrRegparmN(1) BX_CPU_C::CMPBXADD_EdGdBd(bxInstruction_c *i)
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{
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Bit32u op2_32 = BX_READ_32BIT_REG(i->src1());
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Bit32u op3_32 = BX_READ_32BIT_REG(i->src2());
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bx_address eaddr = BX_CPU_RESOLVE_ADDR(i), laddr = get_laddr(i->seg(), eaddr);
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if (laddr & 3) {
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BX_ERROR(("%s: #GP misaligned access", i->getIaOpcodeNameShort()));
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exception(BX_GP_EXCEPTION, 0);
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}
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Bit32u op1_32 = read_RMW_linear_dword(i->seg(), laddr);
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Bit32u diff_32 = op1_32 - op2_32;
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SET_FLAGS_OSZAPC_SUB_32(op1_32, op2_32, diff_32);
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write_RMW_linear_dword(get_CF() ? op1_32 + op3_32 : op1_32);
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BX_WRITE_32BIT_REGZ(i->src1(), op1_32);
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BX_NEXT_INSTR(i);
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}
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void BX_CPP_AttrRegparmN(1) BX_CPU_C::CMPLEXADD_EdGdBd(bxInstruction_c *i)
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{
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Bit32u op2_32 = BX_READ_32BIT_REG(i->src1());
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Bit32u op3_32 = BX_READ_32BIT_REG(i->src2());
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bx_address eaddr = BX_CPU_RESOLVE_ADDR(i), laddr = get_laddr(i->seg(), eaddr);
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if (laddr & 3) {
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BX_ERROR(("%s: #GP misaligned access", i->getIaOpcodeNameShort()));
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exception(BX_GP_EXCEPTION, 0);
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}
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Bit32u op1_32 = read_RMW_linear_dword(i->seg(), laddr);
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Bit32u diff_32 = op1_32 - op2_32;
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SET_FLAGS_OSZAPC_SUB_32(op1_32, op2_32, diff_32);
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write_RMW_linear_dword((get_ZF() || getB_SF() != getB_OF()) ? op1_32 + op3_32 : op1_32);
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BX_WRITE_32BIT_REGZ(i->src1(), op1_32);
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BX_NEXT_INSTR(i);
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}
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void BX_CPP_AttrRegparmN(1) BX_CPU_C::CMPLXADD_EdGdBd(bxInstruction_c *i)
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{
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Bit32u op2_32 = BX_READ_32BIT_REG(i->src1());
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Bit32u op3_32 = BX_READ_32BIT_REG(i->src2());
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bx_address eaddr = BX_CPU_RESOLVE_ADDR(i), laddr = get_laddr(i->seg(), eaddr);
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if (laddr & 3) {
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BX_ERROR(("%s: #GP misaligned access", i->getIaOpcodeNameShort()));
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exception(BX_GP_EXCEPTION, 0);
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}
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Bit32u op1_32 = read_RMW_linear_dword(i->seg(), laddr);
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Bit32u diff_32 = op1_32 - op2_32;
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SET_FLAGS_OSZAPC_SUB_32(op1_32, op2_32, diff_32);
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write_RMW_linear_dword((getB_SF() != getB_OF()) ? op1_32 + op3_32 : op1_32);
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BX_WRITE_32BIT_REGZ(i->src1(), op1_32);
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BX_NEXT_INSTR(i);
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}
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void BX_CPP_AttrRegparmN(1) BX_CPU_C::CMPNBEXADD_EdGdBd(bxInstruction_c *i)
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{
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Bit32u op2_32 = BX_READ_32BIT_REG(i->src1());
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Bit32u op3_32 = BX_READ_32BIT_REG(i->src2());
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bx_address eaddr = BX_CPU_RESOLVE_ADDR(i), laddr = get_laddr(i->seg(), eaddr);
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if (laddr & 3) {
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BX_ERROR(("%s: #GP misaligned access", i->getIaOpcodeNameShort()));
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exception(BX_GP_EXCEPTION, 0);
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}
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Bit32u op1_32 = read_RMW_linear_dword(i->seg(), laddr);
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Bit32u diff_32 = op1_32 - op2_32;
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SET_FLAGS_OSZAPC_SUB_32(op1_32, op2_32, diff_32);
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write_RMW_linear_dword((!get_CF() && !get_ZF()) ? op1_32 + op3_32 : op1_32);
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BX_WRITE_32BIT_REGZ(i->src1(), op1_32);
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BX_NEXT_INSTR(i);
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}
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void BX_CPP_AttrRegparmN(1) BX_CPU_C::CMPNBXADD_EdGdBd(bxInstruction_c *i)
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{
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Bit32u op2_32 = BX_READ_32BIT_REG(i->src1());
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Bit32u op3_32 = BX_READ_32BIT_REG(i->src2());
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bx_address eaddr = BX_CPU_RESOLVE_ADDR(i), laddr = get_laddr(i->seg(), eaddr);
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if (laddr & 3) {
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BX_ERROR(("%s: #GP misaligned access", i->getIaOpcodeNameShort()));
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exception(BX_GP_EXCEPTION, 0);
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}
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Bit32u op1_32 = read_RMW_linear_dword(i->seg(), laddr);
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Bit32u diff_32 = op1_32 - op2_32;
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SET_FLAGS_OSZAPC_SUB_32(op1_32, op2_32, diff_32);
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write_RMW_linear_dword(!get_CF() ? op1_32 + op3_32 : op1_32);
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BX_WRITE_32BIT_REGZ(i->src1(), op1_32);
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BX_NEXT_INSTR(i);
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}
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void BX_CPP_AttrRegparmN(1) BX_CPU_C::CMPNLEXADD_EdGdBd(bxInstruction_c *i)
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{
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Bit32u op2_32 = BX_READ_32BIT_REG(i->src1());
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Bit32u op3_32 = BX_READ_32BIT_REG(i->src2());
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bx_address eaddr = BX_CPU_RESOLVE_ADDR(i), laddr = get_laddr(i->seg(), eaddr);
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if (laddr & 3) {
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BX_ERROR(("%s: #GP misaligned access", i->getIaOpcodeNameShort()));
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exception(BX_GP_EXCEPTION, 0);
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}
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Bit32u op1_32 = read_RMW_linear_dword(i->seg(), laddr);
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Bit32u diff_32 = op1_32 - op2_32;
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SET_FLAGS_OSZAPC_SUB_32(op1_32, op2_32, diff_32);
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write_RMW_linear_dword((!get_ZF() && getB_SF() == getB_OF()) ? op1_32 + op3_32 : op1_32);
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BX_WRITE_32BIT_REGZ(i->src1(), op1_32);
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BX_NEXT_INSTR(i);
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}
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void BX_CPP_AttrRegparmN(1) BX_CPU_C::CMPNLXADD_EdGdBd(bxInstruction_c *i)
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{
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Bit32u op2_32 = BX_READ_32BIT_REG(i->src1());
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Bit32u op3_32 = BX_READ_32BIT_REG(i->src2());
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bx_address eaddr = BX_CPU_RESOLVE_ADDR(i), laddr = get_laddr(i->seg(), eaddr);
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if (laddr & 3) {
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BX_ERROR(("%s: #GP misaligned access", i->getIaOpcodeNameShort()));
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exception(BX_GP_EXCEPTION, 0);
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}
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Bit32u op1_32 = read_RMW_linear_dword(i->seg(), laddr);
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Bit32u diff_32 = op1_32 - op2_32;
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SET_FLAGS_OSZAPC_SUB_32(op1_32, op2_32, diff_32);
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write_RMW_linear_dword((getB_SF() == getB_OF()) ? op1_32 + op3_32 : op1_32);
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BX_WRITE_32BIT_REGZ(i->src1(), op1_32);
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BX_NEXT_INSTR(i);
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}
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void BX_CPP_AttrRegparmN(1) BX_CPU_C::CMPNOXADD_EdGdBd(bxInstruction_c *i)
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{
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Bit32u op2_32 = BX_READ_32BIT_REG(i->src1());
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Bit32u op3_32 = BX_READ_32BIT_REG(i->src2());
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bx_address eaddr = BX_CPU_RESOLVE_ADDR(i), laddr = get_laddr(i->seg(), eaddr);
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if (laddr & 3) {
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BX_ERROR(("%s: #GP misaligned access", i->getIaOpcodeNameShort()));
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exception(BX_GP_EXCEPTION, 0);
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}
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Bit32u op1_32 = read_RMW_linear_dword(i->seg(), laddr);
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Bit32u diff_32 = op1_32 - op2_32;
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SET_FLAGS_OSZAPC_SUB_32(op1_32, op2_32, diff_32);
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write_RMW_linear_dword(!get_OF() ? op1_32 + op3_32 : op1_32);
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BX_WRITE_32BIT_REGZ(i->src1(), op1_32);
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BX_NEXT_INSTR(i);
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}
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void BX_CPP_AttrRegparmN(1) BX_CPU_C::CMPNPXADD_EdGdBd(bxInstruction_c *i)
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{
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Bit32u op2_32 = BX_READ_32BIT_REG(i->src1());
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Bit32u op3_32 = BX_READ_32BIT_REG(i->src2());
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bx_address eaddr = BX_CPU_RESOLVE_ADDR(i), laddr = get_laddr(i->seg(), eaddr);
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if (laddr & 3) {
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BX_ERROR(("%s: #GP misaligned access", i->getIaOpcodeNameShort()));
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exception(BX_GP_EXCEPTION, 0);
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}
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Bit32u op1_32 = read_RMW_linear_dword(i->seg(), laddr);
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Bit32u diff_32 = op1_32 - op2_32;
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SET_FLAGS_OSZAPC_SUB_32(op1_32, op2_32, diff_32);
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write_RMW_linear_dword(!get_PF() ? op1_32 + op3_32 : op1_32);
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BX_WRITE_32BIT_REGZ(i->src1(), op1_32);
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BX_NEXT_INSTR(i);
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}
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void BX_CPP_AttrRegparmN(1) BX_CPU_C::CMPNSXADD_EdGdBd(bxInstruction_c *i)
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{
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Bit32u op2_32 = BX_READ_32BIT_REG(i->src1());
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Bit32u op3_32 = BX_READ_32BIT_REG(i->src2());
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bx_address eaddr = BX_CPU_RESOLVE_ADDR(i), laddr = get_laddr(i->seg(), eaddr);
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if (laddr & 3) {
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BX_ERROR(("%s: #GP misaligned access", i->getIaOpcodeNameShort()));
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exception(BX_GP_EXCEPTION, 0);
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}
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Bit32u op1_32 = read_RMW_linear_dword(i->seg(), laddr);
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Bit32u diff_32 = op1_32 - op2_32;
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SET_FLAGS_OSZAPC_SUB_32(op1_32, op2_32, diff_32);
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write_RMW_linear_dword(!get_SF() ? op1_32 + op3_32 : op1_32);
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BX_WRITE_32BIT_REGZ(i->src1(), op1_32);
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BX_NEXT_INSTR(i);
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}
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void BX_CPP_AttrRegparmN(1) BX_CPU_C::CMPNZXADD_EdGdBd(bxInstruction_c *i)
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{
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Bit32u op2_32 = BX_READ_32BIT_REG(i->src1());
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Bit32u op3_32 = BX_READ_32BIT_REG(i->src2());
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bx_address eaddr = BX_CPU_RESOLVE_ADDR(i), laddr = get_laddr(i->seg(), eaddr);
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if (laddr & 3) {
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BX_ERROR(("%s: #GP misaligned access", i->getIaOpcodeNameShort()));
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exception(BX_GP_EXCEPTION, 0);
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}
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Bit32u op1_32 = read_RMW_linear_dword(i->seg(), laddr);
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Bit32u diff_32 = op1_32 - op2_32;
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SET_FLAGS_OSZAPC_SUB_32(op1_32, op2_32, diff_32);
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write_RMW_linear_dword((!get_ZF()) ? op1_32 + op3_32 : op1_32);
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BX_WRITE_32BIT_REGZ(i->src1(), op1_32);
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BX_NEXT_INSTR(i);
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}
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void BX_CPP_AttrRegparmN(1) BX_CPU_C::CMPOXADD_EdGdBd(bxInstruction_c *i)
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{
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Bit32u op2_32 = BX_READ_32BIT_REG(i->src1());
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Bit32u op3_32 = BX_READ_32BIT_REG(i->src2());
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bx_address eaddr = BX_CPU_RESOLVE_ADDR(i), laddr = get_laddr(i->seg(), eaddr);
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if (laddr & 3) {
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BX_ERROR(("%s: #GP misaligned access", i->getIaOpcodeNameShort()));
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exception(BX_GP_EXCEPTION, 0);
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}
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Bit32u op1_32 = read_RMW_linear_dword(i->seg(), laddr);
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Bit32u diff_32 = op1_32 - op2_32;
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SET_FLAGS_OSZAPC_SUB_32(op1_32, op2_32, diff_32);
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write_RMW_linear_dword(get_OF() ? op1_32 + op3_32 : op1_32);
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BX_WRITE_32BIT_REGZ(i->src1(), op1_32);
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BX_NEXT_INSTR(i);
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}
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void BX_CPP_AttrRegparmN(1) BX_CPU_C::CMPPXADD_EdGdBd(bxInstruction_c *i)
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{
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Bit32u op2_32 = BX_READ_32BIT_REG(i->src1());
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Bit32u op3_32 = BX_READ_32BIT_REG(i->src2());
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bx_address eaddr = BX_CPU_RESOLVE_ADDR(i), laddr = get_laddr(i->seg(), eaddr);
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if (laddr & 3) {
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BX_ERROR(("%s: #GP misaligned access", i->getIaOpcodeNameShort()));
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exception(BX_GP_EXCEPTION, 0);
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}
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Bit32u op1_32 = read_RMW_linear_dword(i->seg(), laddr);
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Bit32u diff_32 = op1_32 - op2_32;
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SET_FLAGS_OSZAPC_SUB_32(op1_32, op2_32, diff_32);
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write_RMW_linear_dword(get_PF() ? op1_32 + op3_32 : op1_32);
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BX_WRITE_32BIT_REGZ(i->src1(), op1_32);
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BX_NEXT_INSTR(i);
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}
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void BX_CPP_AttrRegparmN(1) BX_CPU_C::CMPSXADD_EdGdBd(bxInstruction_c *i)
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{
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Bit32u op2_32 = BX_READ_32BIT_REG(i->src1());
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Bit32u op3_32 = BX_READ_32BIT_REG(i->src2());
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bx_address eaddr = BX_CPU_RESOLVE_ADDR(i), laddr = get_laddr(i->seg(), eaddr);
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if (laddr & 3) {
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BX_ERROR(("%s: #GP misaligned access", i->getIaOpcodeNameShort()));
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exception(BX_GP_EXCEPTION, 0);
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}
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Bit32u op1_32 = read_RMW_linear_dword(i->seg(), laddr);
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Bit32u diff_32 = op1_32 - op2_32;
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SET_FLAGS_OSZAPC_SUB_32(op1_32, op2_32, diff_32);
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write_RMW_linear_dword(get_SF() ? op1_32 + op3_32 : op1_32);
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BX_WRITE_32BIT_REGZ(i->src1(), op1_32);
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BX_NEXT_INSTR(i);
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}
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void BX_CPP_AttrRegparmN(1) BX_CPU_C::CMPZXADD_EdGdBd(bxInstruction_c *i)
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{
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Bit32u op2_32 = BX_READ_32BIT_REG(i->src1());
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Bit32u op3_32 = BX_READ_32BIT_REG(i->src2());
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bx_address eaddr = BX_CPU_RESOLVE_ADDR(i), laddr = get_laddr(i->seg(), eaddr);
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if (laddr & 3) {
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BX_ERROR(("%s: #GP misaligned access", i->getIaOpcodeNameShort()));
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exception(BX_GP_EXCEPTION, 0);
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}
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Bit32u op1_32 = read_RMW_linear_dword(i->seg(), laddr);
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Bit32u diff_32 = op1_32 - op2_32;
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SET_FLAGS_OSZAPC_SUB_32(op1_32, op2_32, diff_32);
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write_RMW_linear_dword(get_ZF() ? op1_32 + op3_32 : op1_32);
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BX_WRITE_32BIT_REGZ(i->src1(), op1_32);
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BX_NEXT_INSTR(i);
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}
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#endif
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