80dd7a07ec
be used at all, and Peter didn't want it. "extdb.o" is compiled into libcpu.a, if configured for it. Removed a few #warnings for x86-64 compile, based on Peter's line-item comments regarding the warnings I inserted during the port/merge.
460 lines
10 KiB
C++
460 lines
10 KiB
C++
/////////////////////////////////////////////////////////////////////////
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// $Id: ctrl_xfer64.cc,v 1.2 2002-09-15 15:10:21 kevinlawton Exp $
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/////////////////////////////////////////////////////////////////////////
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//
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// Copyright (C) 2001 MandrakeSoft S.A.
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//
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// MandrakeSoft S.A.
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// 43, rue d'Aboukir
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// 75002 Paris - France
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// http://www.linux-mandrake.com/
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// http://www.mandrakesoft.com/
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//
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// This library is free software; you can redistribute it and/or
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// modify it under the terms of the GNU Lesser General Public
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// License as published by the Free Software Foundation; either
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// version 2 of the License, or (at your option) any later version.
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//
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// This library is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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// Lesser General Public License for more details.
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//
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// You should have received a copy of the GNU Lesser General Public
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// License along with this library; if not, write to the Free Software
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// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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#define NEED_CPU_REG_SHORTCUTS 1
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#include "bochs.h"
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#define LOG_THIS BX_CPU_THIS_PTR
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void
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BX_CPU_C::RETnear64_Iw(BxInstruction_t *i)
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{
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Bit16u imm16;
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Bit64u temp_RSP;
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Bit64u return_RIP;
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#if BX_DEBUGGER
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BX_CPU_THIS_PTR show_flag |= Flag_ret;
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#endif
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temp_RSP = RSP;
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imm16 = i->Iw;
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invalidate_prefetch_q();
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//if ( !can_pop(8) ) {
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// BX_PANIC(("retnear_iw: can't pop RIP"));
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// /* ??? #SS(0) -or #GP(0) */
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// }
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access_linear(BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].cache.u.segment.base + temp_RSP + 0,
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8, CPL==3, BX_READ, &return_RIP);
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/* Pentium book says imm16 is number of words ??? */
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//if ( !can_pop(8 + imm16) ) {
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// BX_PANIC(("retnear_iw: can't release bytes from stack"));
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// /* #GP(0) -or #SS(0) ??? */
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// }
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RIP = return_RIP;
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RSP += 8 + imm16; /* ??? should it be 2*imm16 ? */
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BX_INSTR_UCNEAR_BRANCH(BX_INSTR_IS_RET, BX_CPU_THIS_PTR rip);
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}
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void
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BX_CPU_C::RETnear64(BxInstruction_t *i)
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{
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Bit64u temp_RSP;
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Bit64u return_RIP;
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#if BX_DEBUGGER
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BX_CPU_THIS_PTR show_flag |= Flag_ret;
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#endif
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invalidate_prefetch_q();
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temp_RSP = RSP;
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//if ( !can_pop(8) ) {
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// BX_PANIC(("retnear: can't pop RIP"));
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// /* ??? #SS(0) -or #GP(0) */
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// }
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access_linear(BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].cache.u.segment.base + temp_RSP + 0,
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8, CPL==3, BX_READ, &return_RIP);
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RIP = return_RIP;
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RSP += 8;
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BX_INSTR_UCNEAR_BRANCH(BX_INSTR_IS_RET, BX_CPU_THIS_PTR rip);
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}
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void
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BX_CPU_C::RETfar64_Iw(BxInstruction_t *i)
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{
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Bit64u rip, rcs_raw;
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Bit16s imm16;
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#if BX_DEBUGGER
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BX_CPU_THIS_PTR show_flag |= Flag_ret;
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#endif
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/* ??? is imm16, number of bytes/words depending on operandsize ? */
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imm16 = i->Iw;
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invalidate_prefetch_q();
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#if BX_CPU_LEVEL >= 2
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if (protected_mode()) {
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BX_CPU_THIS_PTR return_protected(i, imm16);
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goto done;
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}
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#endif
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pop_64(&rip);
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pop_64(&rcs_raw);
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RIP = rip;
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load_seg_reg(&BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS], (Bit16u) rcs_raw);
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RSP += imm16;
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done:
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BX_INSTR_FAR_BRANCH(BX_INSTR_IS_RET,
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BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].selector.value, BX_CPU_THIS_PTR rip);
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return;
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}
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void
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BX_CPU_C::RETfar64(BxInstruction_t *i)
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{
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Bit64u rip, rcs_raw;
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#if BX_DEBUGGER
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BX_CPU_THIS_PTR show_flag |= Flag_ret;
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#endif
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invalidate_prefetch_q();
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#if BX_CPU_LEVEL >= 2
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if ( protected_mode() ) {
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BX_CPU_THIS_PTR return_protected(i, 0);
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goto done;
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}
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#endif
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pop_64(&rip);
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pop_64(&rcs_raw); /* 64bit pop, upper 48 bits discarded */
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RIP = rip;
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load_seg_reg(&BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS], (Bit16u) rcs_raw);
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done:
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BX_INSTR_FAR_BRANCH(BX_INSTR_IS_RET,
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BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].selector.value, BX_CPU_THIS_PTR rip);
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return;
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}
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void
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BX_CPU_C::CALL_Aq(BxInstruction_t *i)
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{
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Bit64u new_RIP;
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Bit32s disp32;
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#if BX_DEBUGGER
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BX_CPU_THIS_PTR show_flag |= Flag_call;
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#endif
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disp32 = i->Id;
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invalidate_prefetch_q();
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new_RIP = RIP + disp32;
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/* push 64 bit EA of next instruction */
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push_64(BX_CPU_THIS_PTR rip);
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RIP = new_RIP;
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BX_INSTR_UCNEAR_BRANCH(BX_INSTR_IS_CALL, BX_CPU_THIS_PTR rip);
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}
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void
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BX_CPU_C::CALL64_Ap(BxInstruction_t *i)
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{
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Bit16u cs_raw;
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Bit32u disp32;
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#if BX_DEBUGGER
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BX_CPU_THIS_PTR show_flag |= Flag_call;
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#endif
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disp32 = i->Id;
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cs_raw = i->Iw2;
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invalidate_prefetch_q();
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if (protected_mode()) {
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BX_CPU_THIS_PTR call_protected(i, cs_raw, disp32);
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goto done;
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}
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push_64(BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].selector.value);
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push_64(BX_CPU_THIS_PTR rip);
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RIP = disp32;
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load_seg_reg(&BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS], cs_raw);
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done:
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BX_INSTR_FAR_BRANCH(BX_INSTR_IS_CALL,
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BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].selector.value, BX_CPU_THIS_PTR rip);
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return;
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}
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void
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BX_CPU_C::CALL_Eq(BxInstruction_t *i)
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{
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Bit64u temp_RSP;
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Bit64u op1_64;
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#if BX_DEBUGGER
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BX_CPU_THIS_PTR show_flag |= Flag_call;
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#endif
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temp_RSP = RSP;
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/* op1_64 is a register or memory reference */
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if (i->mod == 0xc0) {
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op1_64 = BX_READ_64BIT_REG(i->rm);
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}
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else {
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read_virtual_qword(i->seg, i->rm_addr, &op1_64);
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}
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invalidate_prefetch_q();
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if ( !can_push(&BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].cache, temp_RSP, 8) ) {
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BX_PANIC(("call_ev: can't push RIP"));
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}
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push_64(BX_CPU_THIS_PTR rip);
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RIP = op1_64;
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BX_INSTR_UCNEAR_BRANCH(BX_INSTR_IS_CALL, BX_CPU_THIS_PTR rip);
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}
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void
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BX_CPU_C::CALL64_Ep(BxInstruction_t *i)
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{
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Bit16u cs_raw;
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Bit64u op1_64;
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#if BX_DEBUGGER
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BX_CPU_THIS_PTR show_flag |= Flag_call;
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#endif
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/* op1_64 is a register or memory reference */
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if (i->mod == 0xc0) {
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BX_PANIC(("CALL_Ep: op1 is a register"));
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}
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/* pointer, segment address pair */
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read_virtual_qword(i->seg, i->rm_addr, &op1_64);
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read_virtual_word(i->seg, i->rm_addr+8, &cs_raw);
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invalidate_prefetch_q();
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if ( protected_mode() ) {
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BX_CPU_THIS_PTR call_protected(i, cs_raw, op1_64);
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goto done;
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}
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push_64(BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].selector.value);
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push_64(BX_CPU_THIS_PTR rip);
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RIP = op1_64;
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load_seg_reg(&BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS], cs_raw);
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done:
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BX_INSTR_FAR_BRANCH(BX_INSTR_IS_CALL,
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BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].selector.value, BX_CPU_THIS_PTR rip);
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return;
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}
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void
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BX_CPU_C::JMP_Jq(BxInstruction_t *i)
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{
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Bit64u new_RIP;
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invalidate_prefetch_q();
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RIP += (Bit32s) i->Id;
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BX_INSTR_UCNEAR_BRANCH(BX_INSTR_IS_JMP, new_RIP);
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}
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void
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BX_CPU_C::JCC_Jq(BxInstruction_t *i)
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{
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Boolean condition = 0;
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switch (i->b1 & 0x0f) {
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case 0x00: /* JO */ condition = get_OF(); break;
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case 0x01: /* JNO */ condition = !get_OF(); break;
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case 0x02: /* JB */ condition = get_CF(); break;
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case 0x03: /* JNB */ condition = !get_CF(); break;
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case 0x04: /* JZ */ condition = get_ZF(); break;
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case 0x05: /* JNZ */ condition = !get_ZF(); break;
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case 0x06: /* JBE */ condition = get_CF() || get_ZF(); break;
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case 0x07: /* JNBE */ condition = !get_CF() && !get_ZF(); break;
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case 0x08: /* JS */ condition = get_SF(); break;
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case 0x09: /* JNS */ condition = !get_SF(); break;
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case 0x0A: /* JP */ condition = get_PF(); break;
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case 0x0B: /* JNP */ condition = !get_PF(); break;
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case 0x0C: /* JL */ condition = get_SF() != get_OF(); break;
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case 0x0D: /* JNL */ condition = get_SF() == get_OF(); break;
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case 0x0E: /* JLE */ condition = get_ZF() || (get_SF() != get_OF());
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break;
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case 0x0F: /* JNLE */ condition = (get_SF() == get_OF()) &&
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!get_ZF();
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break;
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}
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if (condition) {
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RIP += (Bit32s) i->Id;
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BX_INSTR_CNEAR_BRANCH_TAKEN(RIP);
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revalidate_prefetch_q();
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}
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#if BX_INSTRUMENTATION
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else {
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BX_INSTR_CNEAR_BRANCH_NOT_TAKEN();
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}
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#endif
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}
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#ifdef ignore
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void
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BX_CPU_C::JMP64_Ap(BxInstruction_t *i)
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{
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Bit64u disp64;
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Bit16u cs_raw;
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invalidate_prefetch_q();
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if (i->os_32) {
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disp64 = (Bit32s) i->Id;
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}
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else {
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disp64 = (Bit16s) i->Iw;
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}
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cs_raw = i->Iw2;
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#if BX_CPU_LEVEL >= 2
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if (protected_mode()) {
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BX_CPU_THIS_PTR jump_protected(i, cs_raw, disp32);
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goto done;
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}
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#endif
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load_seg_reg(&BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS], cs_raw);
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RIP = disp64;
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done:
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BX_INSTR_FAR_BRANCH(BX_INSTR_IS_JMP,
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BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].selector.value, BX_CPU_THIS_PTR rip);
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return;
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}
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#endif
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void
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BX_CPU_C::JMP_Eq(BxInstruction_t *i)
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{
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Bit64u new_RIP;
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Bit64u op1_64;
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/* op1_64 is a register or memory reference */
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if (i->mod == 0xc0) {
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op1_64 = BX_READ_64BIT_REG(i->rm);
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}
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else {
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/* pointer, segment address pair */
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read_virtual_qword(i->seg, i->rm_addr, &op1_64);
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}
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invalidate_prefetch_q();
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RIP = op1_64;
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BX_INSTR_UCNEAR_BRANCH(BX_INSTR_IS_JMP, new_RIP);
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}
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/* Far indirect jump */
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void
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BX_CPU_C::JMP64_Ep(BxInstruction_t *i)
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{
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Bit16u cs_raw;
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Bit64u op1_64;
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/* op1_32 is a register or memory reference */
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if (i->mod == 0xc0) {
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/* far indirect must specify a memory address */
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BX_PANIC(("JMP_Ep(): op1 is a register"));
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}
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/* pointer, segment address pair */
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read_virtual_qword(i->seg, i->rm_addr, &op1_64);
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read_virtual_word(i->seg, i->rm_addr+8, &cs_raw);
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invalidate_prefetch_q();
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if ( protected_mode() ) {
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BX_CPU_THIS_PTR jump_protected(i, cs_raw, op1_64);
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goto done;
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}
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RIP = op1_64;
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load_seg_reg(&BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS], cs_raw);
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done:
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BX_INSTR_FAR_BRANCH(BX_INSTR_IS_JMP,
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BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].selector.value, RIP);
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return;
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}
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void
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BX_CPU_C::IRET64(BxInstruction_t *i)
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{
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Bit32u rip, ecs_raw, eflags;
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#if BX_DEBUGGER
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BX_CPU_THIS_PTR show_flag |= Flag_iret;
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BX_CPU_THIS_PTR show_eip = BX_CPU_THIS_PTR rip;
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#endif
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invalidate_prefetch_q();
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#if BX_CPU_LEVEL >= 2
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if (BX_CPU_THIS_PTR cr0.pe) {
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iret_protected(i);
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goto done;
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}
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#endif
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done:
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BX_INSTR_FAR_BRANCH(BX_INSTR_IS_IRET,
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BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].selector.value, BX_CPU_THIS_PTR rip);
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return;
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}
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