657 lines
16 KiB
C++
657 lines
16 KiB
C++
/////////////////////////////////////////////////////////////////////////
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// $Id: arith64.cc,v 1.30 2006-06-09 22:29:06 sshwarts Exp $
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/////////////////////////////////////////////////////////////////////////
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//
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// Copyright (C) 2001 MandrakeSoft S.A.
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//
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// MandrakeSoft S.A.
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// 43, rue d'Aboukir
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// 75002 Paris - France
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// http://www.linux-mandrake.com/
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// http://www.mandrakesoft.com/
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//
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// This library is free software; you can redistribute it and/or
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// modify it under the terms of the GNU Lesser General Public
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// License as published by the Free Software Foundation; either
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// version 2 of the License, or (at your option) any later version.
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//
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// This library is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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// Lesser General Public License for more details.
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//
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// You should have received a copy of the GNU Lesser General Public
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// License along with this library; if not, write to the Free Software
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// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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#define NEED_CPU_REG_SHORTCUTS 1
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#include "bochs.h"
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#include "cpu.h"
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#define LOG_THIS BX_CPU_THIS_PTR
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#if BX_SUPPORT_X86_64
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void BX_CPU_C::ADD_EqGq(bxInstruction_c *i)
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{
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/* for 64 bit operand size mode */
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Bit64u op2_64, op1_64, sum_64;
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op2_64 = BX_READ_64BIT_REG(i->nnn());
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/* op1_64 is a register or memory reference */
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if (i->modC0()) {
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op1_64 = BX_READ_64BIT_REG(i->rm());
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sum_64 = op1_64 + op2_64;
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BX_WRITE_64BIT_REG(i->rm(), sum_64);
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}
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else {
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/* pointer, segment address pair */
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read_RMW_virtual_qword(i->seg(), RMAddr(i), &op1_64);
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sum_64 = op1_64 + op2_64;
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write_RMW_virtual_qword(sum_64);
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}
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SET_FLAGS_OSZAPC_64(op1_64, op2_64, sum_64, BX_INSTR_ADD64);
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}
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void BX_CPU_C::ADD_GqEq(bxInstruction_c *i)
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{
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/* for 64 bit operand size mode */
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Bit64u op1_64, op2_64, sum_64;
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op1_64 = BX_READ_64BIT_REG(i->nnn());
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/* op2_64 is a register or memory reference */
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if (i->modC0()) {
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op2_64 = BX_READ_64BIT_REG(i->rm());
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}
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else {
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/* pointer, segment address pair */
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read_virtual_qword(i->seg(), RMAddr(i), &op2_64);
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}
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sum_64 = op1_64 + op2_64;
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/* now write sum back to destination */
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BX_WRITE_64BIT_REG(i->nnn(), sum_64);
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SET_FLAGS_OSZAPC_64(op1_64, op2_64, sum_64, BX_INSTR_ADD64);
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}
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void BX_CPU_C::ADD_RAXId(bxInstruction_c *i)
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{
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/* for 64 bit operand size mode */
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Bit64u op1_64, op2_64, sum_64;
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op1_64 = RAX;
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op2_64 = (Bit32s) i->Id();
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sum_64 = op1_64 + op2_64;
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/* now write sum back to destination */
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RAX = sum_64;
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SET_FLAGS_OSZAPC_64(op1_64, op2_64, sum_64, BX_INSTR_ADD64);
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}
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void BX_CPU_C::ADC_EqGq(bxInstruction_c *i)
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{
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bx_bool temp_CF = getB_CF();
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/* for 64 bit operand size mode */
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Bit64u op2_64, op1_64, sum_64;
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op2_64 = BX_READ_64BIT_REG(i->nnn());
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/* op1_64 is a register or memory reference */
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if (i->modC0()) {
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op1_64 = BX_READ_64BIT_REG(i->rm());
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sum_64 = op1_64 + op2_64 + temp_CF;
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BX_WRITE_64BIT_REG(i->rm(), sum_64);
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}
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else {
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/* pointer, segment address pair */
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read_RMW_virtual_qword(i->seg(), RMAddr(i), &op1_64);
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sum_64 = op1_64 + op2_64 + temp_CF;
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write_RMW_virtual_qword(sum_64);
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}
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SET_FLAGS_OSZAPC_64(op1_64, op2_64, sum_64, BX_INSTR_ADD_ADC64(temp_CF));
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}
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void BX_CPU_C::ADC_GqEq(bxInstruction_c *i)
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{
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bx_bool temp_CF = getB_CF();
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/* for 64 bit operand size mode */
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Bit64u op1_64, op2_64, sum_64;
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op1_64 = BX_READ_64BIT_REG(i->nnn());
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/* op2_64 is a register or memory reference */
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if (i->modC0()) {
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op2_64 = BX_READ_64BIT_REG(i->rm());
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}
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else {
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/* pointer, segment address pair */
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read_virtual_qword(i->seg(), RMAddr(i), &op2_64);
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}
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sum_64 = op1_64 + op2_64 + temp_CF;
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/* now write sum back to destination */
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BX_WRITE_64BIT_REG(i->nnn(), sum_64);
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SET_FLAGS_OSZAPC_64(op1_64, op2_64, sum_64, BX_INSTR_ADD_ADC64(temp_CF));
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}
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void BX_CPU_C::ADC_RAXId(bxInstruction_c *i)
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{
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bx_bool temp_CF = getB_CF();
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/* for 64 bit operand size mode */
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Bit64u op1_64, op2_64, sum_64;
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op1_64 = RAX;
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op2_64 = (Bit32s) i->Id();
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sum_64 = op1_64 + op2_64 + temp_CF;
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/* now write sum back to destination */
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RAX = sum_64;
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SET_FLAGS_OSZAPC_64(op1_64, op2_64, sum_64, BX_INSTR_ADD_ADC64(temp_CF));
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}
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void BX_CPU_C::SBB_EqGq(bxInstruction_c *i)
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{
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bx_bool temp_CF = getB_CF();
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/* for 64 bit operand size mode */
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Bit64u op2_64, op1_64, diff_64;
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op2_64 = BX_READ_64BIT_REG(i->nnn());
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/* op1_64 is a register or memory reference */
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if (i->modC0()) {
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op1_64 = BX_READ_64BIT_REG(i->rm());
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diff_64 = op1_64 - (op2_64 + temp_CF);
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BX_WRITE_64BIT_REG(i->rm(), diff_64);
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}
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else {
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/* pointer, segment address pair */
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read_RMW_virtual_qword(i->seg(), RMAddr(i), &op1_64);
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diff_64 = op1_64 - (op2_64 + temp_CF);
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write_RMW_virtual_qword(diff_64);
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}
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SET_FLAGS_OSZAPC_64(op1_64, op2_64, diff_64, BX_INSTR_SUB_SBB64(temp_CF));
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}
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void BX_CPU_C::SBB_GqEq(bxInstruction_c *i)
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{
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bx_bool temp_CF = getB_CF();
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/* for 64 bit operand size mode */
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Bit64u op1_64, op2_64, diff_64;
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op1_64 = BX_READ_64BIT_REG(i->nnn());
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/* op2_64 is a register or memory reference */
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if (i->modC0()) {
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op2_64 = BX_READ_64BIT_REG(i->rm());
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}
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else {
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/* pointer, segment address pair */
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read_virtual_qword(i->seg(), RMAddr(i), &op2_64);
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}
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diff_64 = op1_64 - (op2_64 + temp_CF);
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/* now write diff back to destination */
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BX_WRITE_64BIT_REG(i->nnn(), diff_64);
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SET_FLAGS_OSZAPC_64(op1_64, op2_64, diff_64, BX_INSTR_SUB_SBB64(temp_CF));
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}
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void BX_CPU_C::SBB_RAXId(bxInstruction_c *i)
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{
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bx_bool temp_CF = getB_CF();
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/* for 64 bit operand size mode */
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Bit64u op1_64, op2_64, diff_64;
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op1_64 = RAX;
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op2_64 = (Bit32s) i->Id();
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diff_64 = op1_64 - (op2_64 + temp_CF);
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/* now write diff back to destination */
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RAX = diff_64;
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SET_FLAGS_OSZAPC_64(op1_64, op2_64, diff_64, BX_INSTR_SUB_SBB64(temp_CF));
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}
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void BX_CPU_C::SBB_EqId(bxInstruction_c *i)
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{
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bx_bool temp_CF = getB_CF();
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/* for 64 bit operand size mode */
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Bit64u op2_64, op1_64, diff_64;
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op2_64 = (Bit32s) i->Id();
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/* op1_64 is a register or memory reference */
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if (i->modC0()) {
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op1_64 = BX_READ_64BIT_REG(i->rm());
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diff_64 = op1_64 - (op2_64 + temp_CF);
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BX_WRITE_64BIT_REG(i->rm(), diff_64);
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}
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else {
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/* pointer, segment address pair */
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read_RMW_virtual_qword(i->seg(), RMAddr(i), &op1_64);
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diff_64 = op1_64 - (op2_64 + temp_CF);
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write_RMW_virtual_qword(diff_64);
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}
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SET_FLAGS_OSZAPC_64(op1_64, op2_64, diff_64, BX_INSTR_SUB_SBB64(temp_CF));
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}
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void BX_CPU_C::SUB_EqGq(bxInstruction_c *i)
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{
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/* for 64 bit operand size mode */
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Bit64u op2_64, op1_64, diff_64;
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op2_64 = BX_READ_64BIT_REG(i->nnn());
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/* op1_64 is a register or memory reference */
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if (i->modC0()) {
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op1_64 = BX_READ_64BIT_REG(i->rm());
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diff_64 = op1_64 - op2_64;
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BX_WRITE_64BIT_REG(i->rm(), diff_64);
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}
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else {
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/* pointer, segment address pair */
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read_RMW_virtual_qword(i->seg(), RMAddr(i), &op1_64);
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diff_64 = op1_64 - op2_64;
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write_RMW_virtual_qword(diff_64);
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}
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SET_FLAGS_OSZAPC_64(op1_64, op2_64, diff_64, BX_INSTR_SUB64);
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}
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void BX_CPU_C::SUB_GqEq(bxInstruction_c *i)
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{
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/* for 64 bit operand size mode */
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Bit64u op1_64, op2_64, diff_64;
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op1_64 = BX_READ_64BIT_REG(i->nnn());
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/* op2_64 is a register or memory reference */
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if (i->modC0()) {
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op2_64 = BX_READ_64BIT_REG(i->rm());
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}
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else {
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/* pointer, segment address pair */
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read_virtual_qword(i->seg(), RMAddr(i), &op2_64);
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}
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diff_64 = op1_64 - op2_64;
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/* now write diff back to destination */
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BX_WRITE_64BIT_REG(i->nnn(), diff_64);
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SET_FLAGS_OSZAPC_64(op1_64, op2_64, diff_64, BX_INSTR_SUB64);
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}
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void BX_CPU_C::SUB_RAXId(bxInstruction_c *i)
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{
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/* for 64 bit operand size mode */
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Bit64u op1_64, op2_64, diff_64;
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op1_64 = RAX;
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op2_64 = (Bit32s) i->Id();
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diff_64 = op1_64 - op2_64;
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/* now write diff back to destination */
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RAX = diff_64;
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SET_FLAGS_OSZAPC_64(op1_64, op2_64, diff_64, BX_INSTR_SUB64);
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}
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void BX_CPU_C::CMP_EqGq(bxInstruction_c *i)
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{
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/* for 64 bit operand size mode */
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Bit64u op2_64, op1_64, diff_64;
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op2_64 = BX_READ_64BIT_REG(i->nnn());
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/* op1_64 is a register or memory reference */
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if (i->modC0()) {
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op1_64 = BX_READ_64BIT_REG(i->rm());
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}
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else {
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/* pointer, segment address pair */
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read_virtual_qword(i->seg(), RMAddr(i), &op1_64);
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}
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diff_64 = op1_64 - op2_64;
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SET_FLAGS_OSZAPC_64(op1_64, op2_64, diff_64, BX_INSTR_COMPARE64);
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}
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void BX_CPU_C::CMP_GqEq(bxInstruction_c *i)
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{
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/* for 64 bit operand size mode */
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Bit64u op1_64, op2_64, diff_64;
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op1_64 = BX_READ_64BIT_REG(i->nnn());
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/* op2_64 is a register or memory reference */
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if (i->modC0()) {
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op2_64 = BX_READ_64BIT_REG(i->rm());
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}
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else {
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/* pointer, segment address pair */
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read_virtual_qword(i->seg(), RMAddr(i), &op2_64);
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}
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diff_64 = op1_64 - op2_64;
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SET_FLAGS_OSZAPC_64(op1_64, op2_64, diff_64, BX_INSTR_COMPARE64);
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}
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void BX_CPU_C::CMP_RAXId(bxInstruction_c *i)
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{
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/* for 64 bit operand size mode */
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Bit64u op1_64, op2_64, diff_64;
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op1_64 = RAX;
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op2_64 = (Bit32s) i->Id();
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diff_64 = op1_64 - op2_64;
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SET_FLAGS_OSZAPC_64(op1_64, op2_64, diff_64, BX_INSTR_COMPARE64);
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}
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void BX_CPU_C::CDQE(bxInstruction_c *i)
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{
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/* CWDE: no flags are affected */
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RAX = (Bit32s) EAX;
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}
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void BX_CPU_C::CQO(bxInstruction_c *i)
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{
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/* CQO: no flags are affected */
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if (RAX & BX_CONST64(0x8000000000000000))
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RDX = BX_CONST64(0xffffffffffffffff);
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else
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RDX = 0;
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}
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void BX_CPU_C::XADD_EqGq(bxInstruction_c *i)
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{
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Bit64u op2_64, op1_64, sum_64;
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/* XADD dst(r/m), src(r)
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* temp <-- src + dst | sum = op2 + op1
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* src <-- dst | op2 = op1
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* dst <-- tmp | op1 = sum
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*/
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op2_64 = BX_READ_64BIT_REG(i->nnn());
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/* op1 is a register or memory reference */
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if (i->modC0()) {
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op1_64 = BX_READ_64BIT_REG(i->rm());
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}
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else {
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/* pointer, segment address pair */
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read_RMW_virtual_qword(i->seg(), RMAddr(i), &op1_64);
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}
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sum_64 = op1_64 + op2_64;
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/* now write sum back to destination */
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if (i->modC0()) {
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// and write destination into source
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// Note: if both op1 & op2 are registers, the last one written
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// should be the sum, as op1 & op2 may be the same register.
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// For example: XADD AL, AL
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BX_WRITE_64BIT_REG(i->nnn(), op1_64);
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BX_WRITE_64BIT_REG(i->rm(), sum_64);
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}
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else {
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write_RMW_virtual_qword(sum_64);
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/* and write destination into source */
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BX_WRITE_64BIT_REG(i->nnn(), op1_64);
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}
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SET_FLAGS_OSZAPC_64(op1_64, op2_64, sum_64, BX_INSTR_ADD64);
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}
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void BX_CPU_C::ADD_EqId(bxInstruction_c *i)
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{
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/* for 64 bit operand size mode */
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Bit64u op2_64, op1_64, sum_64;
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op2_64 = (Bit32s) i->Id();
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/* op1_64 is a register or memory reference */
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if (i->modC0()) {
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op1_64 = BX_READ_64BIT_REG(i->rm());
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sum_64 = op1_64 + op2_64;
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BX_WRITE_64BIT_REG(i->rm(), sum_64);
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}
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else {
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/* pointer, segment address pair */
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read_RMW_virtual_qword(i->seg(), RMAddr(i), &op1_64);
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sum_64 = op1_64 + op2_64;
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write_RMW_virtual_qword(sum_64);
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}
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SET_FLAGS_OSZAPC_64(op1_64, op2_64, sum_64, BX_INSTR_ADD64);
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}
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void BX_CPU_C::ADC_EqId(bxInstruction_c *i)
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{
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bx_bool temp_CF = getB_CF();
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/* for 64 bit operand size mode */
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Bit64u op2_64, op1_64, sum_64;
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op2_64 = (Bit32s) i->Id();
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/* op1_64 is a register or memory reference */
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if (i->modC0()) {
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op1_64 = BX_READ_64BIT_REG(i->rm());
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sum_64 = op1_64 + op2_64 + temp_CF;
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BX_WRITE_64BIT_REG(i->rm(), sum_64);
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}
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else {
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/* pointer, segment address pair */
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read_RMW_virtual_qword(i->seg(), RMAddr(i), &op1_64);
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sum_64 = op1_64 + op2_64 + temp_CF;
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write_RMW_virtual_qword(sum_64);
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}
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SET_FLAGS_OSZAPC_64(op1_64, op2_64, sum_64, BX_INSTR_ADD_ADC64(temp_CF));
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}
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|
|
|
void BX_CPU_C::SUB_EqId(bxInstruction_c *i)
|
|
{
|
|
/* for 64 bit operand size mode */
|
|
Bit64u op2_64, op1_64, diff_64;
|
|
|
|
op2_64 = (Bit32s) i->Id();
|
|
|
|
/* op1_64 is a register or memory reference */
|
|
if (i->modC0()) {
|
|
op1_64 = BX_READ_64BIT_REG(i->rm());
|
|
diff_64 = op1_64 - op2_64;
|
|
BX_WRITE_64BIT_REG(i->rm(), diff_64);
|
|
}
|
|
else {
|
|
/* pointer, segment address pair */
|
|
read_RMW_virtual_qword(i->seg(), RMAddr(i), &op1_64);
|
|
diff_64 = op1_64 - op2_64;
|
|
write_RMW_virtual_qword(diff_64);
|
|
}
|
|
|
|
SET_FLAGS_OSZAPC_64(op1_64, op2_64, diff_64, BX_INSTR_SUB64);
|
|
}
|
|
|
|
void BX_CPU_C::CMP_EqId(bxInstruction_c *i)
|
|
{
|
|
/* for 64 bit operand size mode */
|
|
Bit64u op2_64, op1_64, diff_64;
|
|
|
|
op2_64 = (Bit32s) i->Id();
|
|
|
|
/* op1_64 is a register or memory reference */
|
|
if (i->modC0()) {
|
|
op1_64 = BX_READ_64BIT_REG(i->rm());
|
|
}
|
|
else {
|
|
/* pointer, segment address pair */
|
|
read_virtual_qword(i->seg(), RMAddr(i), &op1_64);
|
|
}
|
|
|
|
diff_64 = op1_64 - op2_64;
|
|
|
|
SET_FLAGS_OSZAPC_64(op1_64, op2_64, diff_64, BX_INSTR_COMPARE64);
|
|
}
|
|
|
|
void BX_CPU_C::NEG_Eq(bxInstruction_c *i)
|
|
{
|
|
/* for 64 bit operand size mode */
|
|
Bit64u op1_64, diff_64;
|
|
|
|
/* op1_64 is a register or memory reference */
|
|
if (i->modC0()) {
|
|
op1_64 = BX_READ_64BIT_REG(i->rm());
|
|
diff_64 = -op1_64;
|
|
BX_WRITE_64BIT_REG(i->rm(), diff_64);
|
|
}
|
|
else {
|
|
/* pointer, segment address pair */
|
|
read_RMW_virtual_qword(i->seg(), RMAddr(i), &op1_64);
|
|
diff_64 = -op1_64;
|
|
write_RMW_virtual_qword(diff_64);
|
|
}
|
|
|
|
SET_FLAGS_OSZAPC_RESULT_64(diff_64, BX_INSTR_NEG64);
|
|
}
|
|
|
|
void BX_CPU_C::INC_Eq(bxInstruction_c *i)
|
|
{
|
|
Bit64u op1_64;
|
|
|
|
/* op1_64 is a register or memory reference */
|
|
if (i->modC0()) {
|
|
op1_64 = BX_READ_64BIT_REG(i->rm());
|
|
op1_64++;
|
|
BX_WRITE_64BIT_REG(i->rm(), op1_64);
|
|
}
|
|
else {
|
|
/* pointer, segment address pair */
|
|
read_RMW_virtual_qword(i->seg(), RMAddr(i), &op1_64);
|
|
op1_64++;
|
|
write_RMW_virtual_qword(op1_64);
|
|
}
|
|
|
|
SET_FLAGS_OSZAP_RESULT_64(op1_64, BX_INSTR_INC64);
|
|
}
|
|
|
|
void BX_CPU_C::DEC_Eq(bxInstruction_c *i)
|
|
{
|
|
Bit64u op1_64;
|
|
|
|
/* op1_64 is a register or memory reference */
|
|
if (i->modC0()) {
|
|
op1_64 = BX_READ_64BIT_REG(i->rm());
|
|
op1_64--;
|
|
BX_WRITE_64BIT_REG(i->rm(), op1_64);
|
|
}
|
|
else {
|
|
/* pointer, segment address pair */
|
|
read_RMW_virtual_qword(i->seg(), RMAddr(i), &op1_64);
|
|
op1_64--;
|
|
write_RMW_virtual_qword(op1_64);
|
|
}
|
|
|
|
SET_FLAGS_OSZAP_RESULT_64(op1_64, BX_INSTR_DEC64);
|
|
}
|
|
|
|
void BX_CPU_C::CMPXCHG_EqGq(bxInstruction_c *i)
|
|
{
|
|
Bit64u op2_64, op1_64, diff_64;
|
|
|
|
/* op1_64 is a register or memory reference */
|
|
if (i->modC0()) {
|
|
op1_64 = BX_READ_64BIT_REG(i->rm());
|
|
}
|
|
else {
|
|
/* pointer, segment address pair */
|
|
read_RMW_virtual_qword(i->seg(), RMAddr(i), &op1_64);
|
|
}
|
|
|
|
diff_64 = RAX - op1_64;
|
|
|
|
SET_FLAGS_OSZAPC_64(RAX, op1_64, diff_64, BX_INSTR_COMPARE64);
|
|
|
|
if (diff_64 == 0) { // if accumulator == dest
|
|
// dest <-- src
|
|
op2_64 = BX_READ_64BIT_REG(i->nnn());
|
|
|
|
if (i->modC0()) {
|
|
BX_WRITE_64BIT_REG(i->rm(), op2_64);
|
|
}
|
|
else {
|
|
write_RMW_virtual_qword(op2_64);
|
|
}
|
|
}
|
|
else {
|
|
// accumulator <-- dest
|
|
RAX = op1_64;
|
|
}
|
|
}
|
|
|
|
void BX_CPU_C::CMPXCHG16B(bxInstruction_c *i)
|
|
{
|
|
Bit64u op1_64_lo, op1_64_hi, diff;
|
|
|
|
if (i->modC0()) {
|
|
BX_ERROR(("CMPXCHG16B: dest is not memory location (#UD)"));
|
|
UndefinedOpcode(i);
|
|
}
|
|
|
|
if (RMAddr(i) & 0xf) {
|
|
BX_ERROR(("CMPXCHG16B: not aligned memory location (#GP)"));
|
|
exception(BX_GP_EXCEPTION, 0, 0);
|
|
}
|
|
|
|
read_virtual_qword(i->seg(), RMAddr(i), &op1_64_lo);
|
|
read_RMW_virtual_qword(i->seg(), RMAddr(i) + 8, &op1_64_hi);
|
|
|
|
diff = RAX - op1_64_lo;
|
|
diff |= RDX - op1_64_hi;
|
|
|
|
if (diff == 0) { // if accumulator == dest
|
|
// ZF = 1
|
|
set_ZF(1);
|
|
// dest <-- src
|
|
write_RMW_virtual_qword(RCX);
|
|
write_virtual_qword(i->seg(), RMAddr(i), &RBX);
|
|
}
|
|
else {
|
|
// ZF = 0
|
|
set_ZF(0);
|
|
// accumulator <-- dest
|
|
RAX = op1_64_lo;
|
|
RDX = op1_64_hi;
|
|
}
|
|
}
|
|
|
|
#endif /* if BX_SUPPORT_X86_64 */
|