731 lines
23 KiB
C++
731 lines
23 KiB
C++
/////////////////////////////////////////////////////////////////////////
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// $Id$
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/////////////////////////////////////////////////////////////////////////
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//
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// Copyright (c) 2014-2017 Stanislav Shwartsman
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// Written by Stanislav Shwartsman [sshwarts at sourceforge net]
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//
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// This library is free software; you can redistribute it and/or
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// modify it under the terms of the GNU Lesser General Public
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// License as published by the Free Software Foundation; either
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// version 2 of the License, or (at your option) any later version.
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//
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// This library is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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// Lesser General Public License for more details.
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//
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// You should have received a copy of the GNU Lesser General Public
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// License along with this library; if not, write to the Free Software
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// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA B 02110-1301 USA
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//
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/////////////////////////////////////////////////////////////////////////
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#include "bochs.h"
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#include "cpu.h"
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#include "param_names.h"
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#include "trinity_apu.h"
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#define LOG_THIS cpu->
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#if BX_SUPPORT_X86_64 && BX_SUPPORT_AVX
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trinity_apu_t::trinity_apu_t(BX_CPU_C *cpu): bx_cpuid_t(cpu)
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{
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BX_INFO(("WARNING: Light Weight Profiling (LWP) support is not implemented !"));
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if (! BX_SUPPORT_SVM)
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BX_INFO(("WARNING: SVM support is not compiled in !"));
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if (! BX_SUPPORT_MONITOR_MWAIT)
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BX_INFO(("WARNING: MONITOR/MWAIT support is not compiled in !"));
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enable_cpu_extension(BX_ISA_X87);
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enable_cpu_extension(BX_ISA_486);
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enable_cpu_extension(BX_ISA_PENTIUM);
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enable_cpu_extension(BX_ISA_P6);
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enable_cpu_extension(BX_ISA_MMX);
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enable_cpu_extension(BX_ISA_SYSCALL_SYSRET_LEGACY);
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enable_cpu_extension(BX_ISA_SYSENTER_SYSEXIT);
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enable_cpu_extension(BX_ISA_CLFLUSH);
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enable_cpu_extension(BX_ISA_DEBUG_EXTENSIONS);
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enable_cpu_extension(BX_ISA_VME);
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enable_cpu_extension(BX_ISA_PSE);
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enable_cpu_extension(BX_ISA_PAE);
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enable_cpu_extension(BX_ISA_PGE);
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#if BX_PHY_ADDRESS_LONG
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enable_cpu_extension(BX_ISA_PSE36);
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#endif
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enable_cpu_extension(BX_ISA_MTRR);
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enable_cpu_extension(BX_ISA_PAT);
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enable_cpu_extension(BX_ISA_XAPIC);
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enable_cpu_extension(BX_ISA_LONG_MODE);
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enable_cpu_extension(BX_ISA_LM_LAHF_SAHF);
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enable_cpu_extension(BX_ISA_CMPXCHG16B);
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enable_cpu_extension(BX_ISA_NX);
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enable_cpu_extension(BX_ISA_SSE);
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enable_cpu_extension(BX_ISA_SSE2);
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enable_cpu_extension(BX_ISA_SSE3);
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enable_cpu_extension(BX_ISA_SSSE3);
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enable_cpu_extension(BX_ISA_SSE4_1);
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enable_cpu_extension(BX_ISA_SSE4_2);
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enable_cpu_extension(BX_ISA_LZCNT);
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enable_cpu_extension(BX_ISA_POPCNT);
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enable_cpu_extension(BX_ISA_SSE4A);
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#if BX_SUPPORT_MONITOR_MWAIT
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enable_cpu_extension(BX_ISA_MONITOR_MWAIT);
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#endif
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enable_cpu_extension(BX_ISA_RDTSCP);
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enable_cpu_extension(BX_ISA_XSAVE);
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enable_cpu_extension(BX_ISA_AES_PCLMULQDQ);
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enable_cpu_extension(BX_ISA_AVX);
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enable_cpu_extension(BX_ISA_AVX_F16C);
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enable_cpu_extension(BX_ISA_AVX_FMA);
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enable_cpu_extension(BX_ISA_FMA4);
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enable_cpu_extension(BX_ISA_XOP);
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enable_cpu_extension(BX_ISA_TBM);
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enable_cpu_extension(BX_ISA_BMI1);
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#if BX_SUPPORT_SVM
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enable_cpu_extension(BX_ISA_SVM);
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#endif
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enable_cpu_extension(BX_ISA_FFXSR);
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enable_cpu_extension(BX_ISA_1G_PAGES);
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enable_cpu_extension(BX_ISA_MISALIGNED_SSE);
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enable_cpu_extension(BX_ISA_ALT_MOV_CR8);
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enable_cpu_extension(BX_ISA_XAPIC_EXT);
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}
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void trinity_apu_t::get_cpuid_leaf(Bit32u function, Bit32u subfunction, cpuid_function_t *leaf) const
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{
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static const char* brand_string = "AMD A8-5600K APU with Radeon(tm) HD Graphics ";
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static bx_bool cpuid_limit_winnt = SIM->get_param_bool(BXPN_CPUID_LIMIT_WINNT)->get();
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if (cpuid_limit_winnt)
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if (function > 1 && function < 0x80000000) function = 1;
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switch(function) {
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case 0x80000000:
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get_ext_cpuid_leaf_0(leaf);
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return;
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case 0x80000001:
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get_ext_cpuid_leaf_1(leaf);
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return;
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case 0x80000002:
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case 0x80000003:
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case 0x80000004:
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get_ext_cpuid_brand_string_leaf(brand_string, function, leaf);
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return;
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case 0x80000005:
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get_ext_cpuid_leaf_5(leaf);
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return;
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case 0x80000006:
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get_ext_cpuid_leaf_6(leaf);
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return;
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case 0x80000007:
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get_ext_cpuid_leaf_7(leaf);
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return;
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case 0x80000008:
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get_ext_cpuid_leaf_8(leaf);
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return;
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#if BX_SUPPORT_SVM
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case 0x8000000A:
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get_ext_cpuid_leaf_A(leaf);
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return;
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#endif
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case 0x80000019:
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get_ext_cpuid_leaf_19(leaf);
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return;
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case 0x8000001A:
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get_ext_cpuid_leaf_1A(leaf);
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return;
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case 0x8000001B:
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get_ext_cpuid_leaf_1B(leaf);
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return;
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case 0x8000001C:
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get_ext_cpuid_leaf_1C(leaf);
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return;
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case 0x8000001D:
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get_ext_cpuid_leaf_1D(subfunction, leaf);
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return;
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case 0x8000001E:
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get_ext_cpuid_leaf_1E(leaf);
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return;
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case 0x00000000:
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get_std_cpuid_leaf_0(leaf);
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return;
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case 0x00000001:
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get_std_cpuid_leaf_1(leaf);
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return;
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#if BX_SUPPORT_MONITOR_MWAIT
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case 0x00000005:
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get_std_cpuid_leaf_5(leaf);
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return;
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#endif
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case 0x00000006:
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get_std_cpuid_leaf_6(leaf);
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return;
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case 0x00000007:
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get_std_cpuid_leaf_7(subfunction, leaf);
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return;
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case 0x0000000D:
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get_std_cpuid_xsave_leaf(subfunction, leaf);
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return;
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default:
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get_reserved_leaf(leaf);
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return;
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}
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}
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#if BX_SUPPORT_SVM
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Bit32u trinity_apu_t::get_svm_extensions_bitmask(void) const
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{
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return BX_CPUID_SVM_NESTED_PAGING |
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BX_CPUID_SVM_LBR_VIRTUALIZATION |
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BX_CPUID_SVM_SVM_LOCK |
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BX_CPUID_SVM_NRIP_SAVE |
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// BX_CPUID_SVM_TSCRATE | // not implemented yet
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// BX_CPUID_SVM_VMCB_CLEAN_BITS | // not implemented yet
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BX_CPUID_SVM_FLUSH_BY_ASID |
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// BX_CPUID_SVM_DECODE_ASSIST | // not implemented yet
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BX_CPUID_SVM_PAUSE_FILTER; // not implemented yet
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// BX_CPUID_SVM_PAUSE_FILTER_THRESHOLD; // not implemented yet
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}
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#endif
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// leaf 0x00000000 //
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void trinity_apu_t::get_std_cpuid_leaf_0(cpuid_function_t *leaf) const
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{
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static const char* vendor_string = "AuthenticAMD";
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// EAX: highest std function understood by CPUID
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// EBX: vendor ID string
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// EDX: vendor ID string
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// ECX: vendor ID string
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unsigned max_leaf = 0xD;
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static bx_bool cpuid_limit_winnt = SIM->get_param_bool(BXPN_CPUID_LIMIT_WINNT)->get();
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if (cpuid_limit_winnt)
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max_leaf = 0x1;
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get_leaf_0(max_leaf, vendor_string, leaf);
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}
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// leaf 0x00000001 //
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void trinity_apu_t::get_std_cpuid_leaf_1(cpuid_function_t *leaf) const
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{
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// EAX: CPU Version Information
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// [3:0] Stepping ID
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// [7:4] Model: starts at 1
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// [11:8] Family: 4=486, 5=Pentium, 6=PPro, ...
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// [13:12] Type: 0=OEM, 1=overdrive, 2=dual cpu, 3=reserved
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// [19:16] Extended Model
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// [27:20] Extended Family
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leaf->eax = 0x00610F01;
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// EBX:
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// [7:0] Brand ID
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// [15:8] CLFLUSH cache line size (value*8 = cache line size in bytes)
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// [23:16] Number of logical processors in one physical processor
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// [31:24] Local Apic ID
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unsigned n_logical_processors = ncores*nthreads;
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leaf->ebx = ((CACHE_LINE_SIZE / 8) << 8) |
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(n_logical_processors << 16);
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#if BX_SUPPORT_APIC
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leaf->ebx |= ((cpu->get_apic_id() & 0xff) << 24);
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#endif
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// ECX: Extended Feature Flags
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// * [0:0] SSE3: SSE3 Instructions
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// * [1:1] PCLMULQDQ Instruction support
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// [2:2] DTES64: 64-bit DS area
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// * [3:3] MONITOR/MWAIT support
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// [4:4] DS-CPL: CPL qualified debug store
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// [5:5] VMX: Virtual Machine Technology
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// [6:6] SMX: Secure Virtual Machine Technology
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// [7:7] EST: Enhanced Intel SpeedStep Technology
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// [8:8] TM2: Thermal Monitor 2
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// * [9:9] SSSE3: SSSE3 Instructions
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// [10:10] CNXT-ID: L1 context ID
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// [11:11] reserved
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// * [12:12] FMA Instructions support
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// * [13:13] CMPXCHG16B: CMPXCHG16B instruction support
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// [14:14] xTPR update control
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// [15:15] PDCM - Perfon and Debug Capability MSR
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// [16:16] reserved
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// [17:17] PCID: Process Context Identifiers
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// [18:18] DCA - Direct Cache Access
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// * [19:19] SSE4.1 Instructions
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// * [20:20] SSE4.2 Instructions
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// [21:21] X2APIC
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// [22:22] MOVBE instruction
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// * [23:23] POPCNT instruction
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// [24:24] TSC Deadline
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// * [25:25] AES Instructions
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// * [26:26] XSAVE extensions support
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// * [27:27] OSXSAVE support
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// * [28:28] AVX extensions support
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// [29:29] AVX F16C - Float16 conversion support
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// [30:30] RDRAND instruction
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// [31:31] reserved
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leaf->ecx = BX_CPUID_EXT_SSE3 |
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BX_CPUID_EXT_PCLMULQDQ |
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#if BX_SUPPORT_MONITOR_MWAIT
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BX_CPUID_EXT_MONITOR_MWAIT |
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#endif
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BX_CPUID_EXT_SSSE3 |
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BX_CPUID_EXT_FMA |
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BX_CPUID_EXT_CMPXCHG16B |
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BX_CPUID_EXT_SSE4_1 |
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BX_CPUID_EXT_SSE4_2 |
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BX_CPUID_EXT_POPCNT |
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BX_CPUID_EXT_AES |
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BX_CPUID_EXT_XSAVE |
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BX_CPUID_EXT_AVX |
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BX_CPUID_EXT_AVX_F16C;
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if (cpu->cr4.get_OSXSAVE())
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leaf->ecx |= BX_CPUID_EXT_OSXSAVE;
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// EDX: Standard Feature Flags
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// * [0:0] FPU on chip
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// * [1:1] VME: Virtual-8086 Mode enhancements
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// * [2:2] DE: Debug Extensions (I/O breakpoints)
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// * [3:3] PSE: Page Size Extensions
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// * [4:4] TSC: Time Stamp Counter
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// * [5:5] MSR: RDMSR and WRMSR support
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// * [6:6] PAE: Physical Address Extensions
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// * [7:7] MCE: Machine Check Exception
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// * [8:8] CXS: CMPXCHG8B instruction
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// * [9:9] APIC: APIC on Chip
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// [10:10] Reserved
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// * [11:11] SYSENTER/SYSEXIT support
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// * [12:12] MTRR: Memory Type Range Reg
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// * [13:13] PGE/PTE Global Bit
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// * [14:14] MCA: Machine Check Architecture
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// * [15:15] CMOV: Cond Mov/Cmp Instructions
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// * [16:16] PAT: Page Attribute Table
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// * [17:17] PSE-36: Physical Address Extensions
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// [18:18] PSN: Processor Serial Number
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// * [19:19] CLFLUSH: CLFLUSH Instruction support
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// [20:20] Reserved
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// [21:21] DS: Debug Store
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// [22:22] ACPI: Thermal Monitor and Software Controlled Clock Facilities
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// * [23:23] MMX Technology
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// * [24:24] FXSR: FXSAVE/FXRSTOR (also indicates CR4.OSFXSR is available)
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// * [25:25] SSE: SSE Extensions
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// * [26:26] SSE2: SSE2 Extensions
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// [27:27] Self Snoop
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// * [28:28] Hyper Threading Technology
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// [29:29] TM: Thermal Monitor
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// [30:30] Reserved
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// [31:31] PBE: Pending Break Enable
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leaf->edx = BX_CPUID_STD_X87 |
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BX_CPUID_STD_VME |
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BX_CPUID_STD_DEBUG_EXTENSIONS |
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BX_CPUID_STD_PSE |
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BX_CPUID_STD_TSC |
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BX_CPUID_STD_MSR |
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BX_CPUID_STD_PAE |
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BX_CPUID_STD_MCE |
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BX_CPUID_STD_CMPXCHG8B |
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BX_CPUID_STD_SYSENTER_SYSEXIT |
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BX_CPUID_STD_MTRR |
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BX_CPUID_STD_GLOBAL_PAGES |
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BX_CPUID_STD_MCA |
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BX_CPUID_STD_CMOV |
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BX_CPUID_STD_PAT |
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BX_CPUID_STD_PSE36 |
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BX_CPUID_STD_CLFLUSH |
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BX_CPUID_STD_MMX |
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BX_CPUID_STD_FXSAVE_FXRSTOR |
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BX_CPUID_STD_SSE |
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BX_CPUID_STD_SSE2 |
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BX_CPUID_STD_HT;
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#if BX_SUPPORT_APIC
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// if MSR_APICBASE APIC Global Enable bit has been cleared,
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// the CPUID feature flag for the APIC is set to 0.
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if (cpu->msr.apicbase & 0x800)
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leaf->edx |= BX_CPUID_STD_APIC; // APIC on chip
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#endif
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}
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#if BX_SUPPORT_MONITOR_MWAIT
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// leaf 0x00000005 //
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void trinity_apu_t::get_std_cpuid_leaf_5(cpuid_function_t *leaf) const
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{
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// CPUID function 0x00000005 - MONITOR/MWAIT Leaf
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// EAX - Smallest monitor-line size in bytes
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// EBX - Largest monitor-line size in bytes
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// ECX -
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// [31:2] - reserved
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// [1:1] - exit MWAIT even with EFLAGS.IF = 0
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// [0:0] - MONITOR/MWAIT extensions are supported
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// EDX -
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// [03-00] - number of C0 sub C-states supported using MWAIT
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// [07-04] - number of C1 sub C-states supported using MWAIT
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// [11-08] - number of C2 sub C-states supported using MWAIT
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// [15-12] - number of C3 sub C-states supported using MWAIT
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// [19-16] - number of C4 sub C-states supported using MWAIT
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// [31-20] - reserved (MBZ)
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leaf->eax = CACHE_LINE_SIZE;
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leaf->ebx = CACHE_LINE_SIZE;
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leaf->ecx = 3;
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leaf->edx = 0;
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}
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#endif
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// leaf 0x00000006 //
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void trinity_apu_t::get_std_cpuid_leaf_6(cpuid_function_t *leaf) const
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{
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// CPUID function 0x00000006 - Thermal and Power Management Leaf
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leaf->eax = 0x00000000;
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leaf->ebx = 0x00000000;
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leaf->ecx = 0x00000001;
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leaf->edx = 0x00000000;
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}
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// leaf 0x00000007 //
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void trinity_apu_t::get_std_cpuid_leaf_7(Bit32u subfunction, cpuid_function_t *leaf) const
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{
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switch(subfunction) {
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case 0:
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leaf->eax = 0; /* report max sub-leaf that supported in leaf 7 */
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// [0:0] FS/GS BASE access instructions
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// [1:1] Support for IA32_TSC_ADJUST MSR
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// [2:2] reserved
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// * [3:3] BMI1: Advanced Bit Manipulation Extensions
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// [4:4] HLE: Hardware Lock Elision
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// [5:5] AVX2
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// [6:6] reserved
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// [7:7] SMEP: Supervisor Mode Execution Protection
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// [8:8] BMI2: Advanced Bit Manipulation Extensions
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// [9:9] Support for Enhanced REP MOVSB/STOSB
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// [10:10] Support for INVPCID instruction
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// [11:11] RTM: Restricted Transactional Memory
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// [12:12] Supports Quality of Service (QoS) capability
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// [13:13] Deprecates FPU CS and FPU DS values
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// [17:14] reserved
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// [18:18] RDSEED instruction support
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// [19:19] ADCX/ADOX instructions support
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// [20:20] SMAP: Supervisor Mode Access Prevention
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// [31:21] reserved
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leaf->ebx = BX_CPUID_EXT3_BMI1;
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leaf->ecx = 0;
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leaf->edx = 0;
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break;
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default:
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leaf->eax = 0;
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leaf->ebx = 0;
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leaf->ecx = 0;
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leaf->edx = 0;
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}
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}
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// leaf 0x0000000D - XSAVE //
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// leaf 0x80000000 //
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void trinity_apu_t::get_ext_cpuid_leaf_0(cpuid_function_t *leaf) const
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{
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get_leaf_0(0x8000001E, "AuthenticAMD", leaf);
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}
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// leaf 0x80000001 //
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void trinity_apu_t::get_ext_cpuid_leaf_1(cpuid_function_t *leaf) const
|
|
{
|
|
// EAX: CPU Version Information (same as 0x00000001.EAX)
|
|
leaf->eax = 0x00600f12;
|
|
|
|
// EBX:
|
|
// [15:00] Brand ID
|
|
// [27:16] Reserved
|
|
// [31:28] Package Type
|
|
leaf->ebx = 0x20000000;
|
|
|
|
// ECX:
|
|
// * [0:0] LAHF/SAHF instructions support in 64-bit mode
|
|
// * [1:1] CMP_Legacy: Core multi-processing legacy mode (AMD)
|
|
// * [2:2] SVM: Secure Virtual Machine (AMD)
|
|
// * [3:3] Extended APIC Space
|
|
// * [4:4] AltMovCR8: LOCK MOV CR0 means MOV CR8
|
|
// * [5:5] LZCNT: LZCNT instruction support
|
|
// * [6:6] SSE4A: SSE4A Instructions support
|
|
// * [7:7] Misaligned SSE support
|
|
// * [8:8] PREFETCHW: PREFETCHW instruction support
|
|
// * [9:9] OSVW: OS visible workarounds (AMD)
|
|
// * [10:10] IBS: Instruction based sampling
|
|
// * [11:11] XOP: Extended Operations Support and XOP Prefix
|
|
// * [12:12] SKINIT support
|
|
// * [13:13] WDT: Watchdog timer support
|
|
// [14:14] Reserved
|
|
// * [15:15] LWP: Light weight profiling
|
|
// * [16:16] FMA4: Four-operand FMA instructions support
|
|
// * [17:17] Translation Cache Extensions
|
|
// [18:18] Reserved
|
|
// * [19:19] NodeId: Indicates support for NodeId MSR (0xc001100c)
|
|
// [20:20] Reserved
|
|
// * [21:21] TBM: trailing bit manipulation instructions support
|
|
// * [22:22] Topology extensions support
|
|
// * [23:23] PerfCtrExtCore: core perf counter extensions support
|
|
// * [24:24] PerfCtrExtNB: NB perf counter extensions support
|
|
// [31:25] Reserved
|
|
|
|
leaf->ecx = BX_CPUID_EXT2_LAHF_SAHF |
|
|
BX_CPUID_EXT2_CMP_LEGACY |
|
|
#if BX_SUPPORT_SVM
|
|
BX_CPUID_EXT2_SVM |
|
|
#endif
|
|
BX_CPUID_EXT2_EXT_APIC_SPACE |
|
|
BX_CPUID_EXT2_ALT_MOV_CR8 |
|
|
BX_CPUID_EXT2_LZCNT |
|
|
BX_CPUID_EXT2_SSE4A |
|
|
BX_CPUID_EXT2_MISALIGNED_SSE |
|
|
BX_CPUID_EXT2_PREFETCHW |
|
|
BX_CPUID_EXT2_OSVW |
|
|
BX_CPUID_EXT2_IBS |
|
|
BX_CPUID_EXT2_XOP |
|
|
/* BX_CPUID_EXT2_SKINIT | */ // not implemented
|
|
BX_CPUID_EXT2_WDT |
|
|
/* BX_CPUID_EXT2_LWP | */ // not implemented
|
|
BX_CPUID_EXT2_FMA4 |
|
|
BX_CPUID_EXT2_TCE |
|
|
BX_CPUID_EXT2_NODEID |
|
|
BX_CPUID_EXT2_TBM |
|
|
BX_CPUID_EXT2_TOPOLOGY_EXTENSIONS |
|
|
BX_CPUID_EXT2_PERFCTR_EXT_CORE |
|
|
BX_CPUID_EXT2_PERFCTR_EXT_NB;
|
|
|
|
// EDX:
|
|
// Many of the bits in EDX are the same as FN 0x00000001 for AMD
|
|
// * [0:0] FPU on chip
|
|
// * [1:1] VME: Virtual-8086 Mode enhancements
|
|
// * [2:2] DE: Debug Extensions (I/O breakpoints)
|
|
// * [3:3] PSE: Page Size Extensions
|
|
// * [4:4] TSC: Time Stamp Counter
|
|
// * [5:5] MSR: RDMSR and WRMSR support
|
|
// * [6:6] PAE: Physical Address Extensions
|
|
// * [7:7] MCE: Machine Check Exception
|
|
// * [8:8] CXS: CMPXCHG8B instruction
|
|
// * [9:9] APIC: APIC on Chip
|
|
// [10:10] Reserved
|
|
// * [11:11] SYSCALL/SYSRET support
|
|
// * [12:12] MTRR: Memory Type Range Reg
|
|
// * [13:13] PGE/PTE Global Bit
|
|
// * [14:14] MCA: Machine Check Architecture
|
|
// * [15:15] CMOV: Cond Mov/Cmp Instructions
|
|
// * [16:16] PAT: Page Attribute Table
|
|
// * [17:17] PSE-36: Physical Address Extensions
|
|
// [18:18] Reserved
|
|
// [19:19] Reserved
|
|
// * [20:20] No-Execute page protection
|
|
// [21:21] Reserved
|
|
// * [22:22] AMD MMX Extensions
|
|
// * [23:23] MMX Technology
|
|
// * [24:24] FXSR: FXSAVE/FXRSTOR (also indicates CR4.OSFXSR is available)
|
|
// * [25:25] Fast FXSAVE/FXRSTOR mode support
|
|
// * [26:26] 1G paging support
|
|
// * [27:27] Support RDTSCP Instruction
|
|
// [28:28] Reserved
|
|
// * [29:29] Long Mode
|
|
// [30:30] AMD 3DNow! Extensions
|
|
// [31:31] AMD 3DNow! Instructions
|
|
leaf->edx = BX_CPUID_STD_X87 |
|
|
BX_CPUID_STD_VME |
|
|
BX_CPUID_STD_DEBUG_EXTENSIONS |
|
|
BX_CPUID_STD_PSE |
|
|
BX_CPUID_STD_TSC |
|
|
BX_CPUID_STD_MSR |
|
|
BX_CPUID_STD_PAE |
|
|
BX_CPUID_STD_MCE |
|
|
BX_CPUID_STD_CMPXCHG8B |
|
|
BX_CPUID_STD2_SYSCALL_SYSRET |
|
|
BX_CPUID_STD_MTRR |
|
|
BX_CPUID_STD_GLOBAL_PAGES |
|
|
BX_CPUID_STD_MCA |
|
|
BX_CPUID_STD_CMOV |
|
|
BX_CPUID_STD_PAT |
|
|
BX_CPUID_STD_PSE36 |
|
|
BX_CPUID_STD2_NX |
|
|
BX_CPUID_STD2_AMD_MMX_EXT |
|
|
BX_CPUID_STD_MMX |
|
|
BX_CPUID_STD_FXSAVE_FXRSTOR |
|
|
BX_CPUID_STD2_FFXSR |
|
|
BX_CPUID_STD2_1G_PAGES |
|
|
BX_CPUID_STD2_RDTSCP |
|
|
BX_CPUID_STD2_LONG_MODE;
|
|
#if BX_SUPPORT_APIC
|
|
// if MSR_APICBASE APIC Global Enable bit has been cleared,
|
|
// the CPUID feature flag for the APIC is set to 0.
|
|
if (cpu->msr.apicbase & 0x800)
|
|
leaf->edx |= BX_CPUID_STD_APIC; // APIC on chip
|
|
#endif
|
|
}
|
|
|
|
// leaf 0x80000002 //
|
|
// leaf 0x80000003 //
|
|
// leaf 0x80000004 //
|
|
|
|
// leaf 0x80000005 //
|
|
void trinity_apu_t::get_ext_cpuid_leaf_5(cpuid_function_t *leaf) const
|
|
{
|
|
// CPUID function 0x800000005 - L1 Cache and TLB Identifiers
|
|
leaf->eax = 0xFF40FF18;
|
|
leaf->ebx = 0xFF40FF30;
|
|
leaf->ecx = 0x10040140;
|
|
leaf->edx = 0x40020140;
|
|
}
|
|
|
|
// leaf 0x80000006 //
|
|
void trinity_apu_t::get_ext_cpuid_leaf_6(cpuid_function_t *leaf) const
|
|
{
|
|
// CPUID function 0x800000006 - L2 Cache and TLB Identifiers
|
|
leaf->eax = 0x64006400;
|
|
leaf->ebx = 0x64004200;
|
|
leaf->ecx = 0x08008140;
|
|
leaf->edx = 0x00000000;
|
|
}
|
|
|
|
// leaf 0x80000007 //
|
|
void trinity_apu_t::get_ext_cpuid_leaf_7(cpuid_function_t *leaf) const
|
|
{
|
|
// CPUID function 0x800000007 - Advanced Power Management
|
|
leaf->eax = 0;
|
|
leaf->ebx = 0;
|
|
leaf->ecx = 0;
|
|
leaf->edx = 0x000007D9;
|
|
}
|
|
|
|
// leaf 0x80000008 //
|
|
void trinity_apu_t::get_ext_cpuid_leaf_8(cpuid_function_t *leaf) const
|
|
{
|
|
bx_cpuid_t::get_ext_cpuid_leaf_8(leaf);
|
|
|
|
// [17..16] Performance time-stamp counter size.
|
|
// [15..12] APIC ID size, Zero value indicates that legacy methods must be
|
|
// used to derive the maximum number of cores.
|
|
// [11..8] (reserved)
|
|
// [7..0] Number of physical cores - 1.
|
|
leaf->ecx = ncores - 1;
|
|
}
|
|
|
|
// leaf 0x80000009 : Reserved //
|
|
|
|
#if BX_SUPPORT_SVM
|
|
|
|
// leaf 0x8000000A : SVM //
|
|
void trinity_apu_t::get_ext_cpuid_leaf_A(cpuid_function_t *leaf) const
|
|
{
|
|
leaf->eax = 0x01; /* SVM revision ID */
|
|
leaf->ebx = 0x40; /* number of ASIDs */
|
|
leaf->ecx = 0;
|
|
|
|
// * [0:0] NP - Nested paging support
|
|
// * [1:1] LBR virtualization
|
|
// * [2:2] SVM Lock
|
|
// * [3:3] NRIPS - Next RIP save on VMEXIT
|
|
// * [4:4] TscRate - MSR based TSC ratio control
|
|
// * [5:5] VMCB Clean bits support
|
|
// * [6:6] Flush by ASID support
|
|
// * [7:7] Decode assists support
|
|
// [8:8] Reserved
|
|
// [9:9] Reserved
|
|
// * [10:10] Pause filter support
|
|
// [11:11] Reserved
|
|
// * [12:12] Pause filter threshold support
|
|
// [13:13] Advanced Virtual Interrupt Controller
|
|
leaf->edx = get_svm_extensions_bitmask();
|
|
}
|
|
|
|
#endif
|
|
|
|
// leaf 0x8000000B - 0x80000018: Reserved //
|
|
|
|
void trinity_apu_t::get_ext_cpuid_leaf_19(cpuid_function_t *leaf) const
|
|
{
|
|
// CPUID function 0x800000019 - 1G Page TLB Identifiers
|
|
leaf->eax = 0xF040F018;
|
|
leaf->ebx = 0x64006400;
|
|
leaf->ecx = 0;
|
|
leaf->edx = 0;
|
|
}
|
|
|
|
void trinity_apu_t::get_ext_cpuid_leaf_1A(cpuid_function_t *leaf) const
|
|
{
|
|
// CPUID function 0x80000001A - Performance Optimization Identifiers
|
|
leaf->eax = 0x00000003;
|
|
leaf->ebx = 0;
|
|
leaf->ecx = 0;
|
|
leaf->edx = 0;
|
|
}
|
|
|
|
void trinity_apu_t::get_ext_cpuid_leaf_1B(cpuid_function_t *leaf) const
|
|
{
|
|
// CPUID function 0x80000001B - Instruction Based Sampling Identifiers
|
|
leaf->eax = 0xFF;
|
|
leaf->ebx = 0;
|
|
leaf->ecx = 0;
|
|
leaf->edx = 0;
|
|
|
|
BX_INFO(("WARNING: Instruction Based Sampling is not implemented"));
|
|
}
|
|
|
|
void trinity_apu_t::get_ext_cpuid_leaf_1C(cpuid_function_t *leaf) const
|
|
{
|
|
// CPUID function 0x80000001C - Lightweight Profiling Capabilities (not implemented)
|
|
leaf->eax = 0;
|
|
leaf->ebx = 0;
|
|
leaf->ecx = 0;
|
|
leaf->edx = 0;
|
|
}
|
|
|
|
void trinity_apu_t::get_ext_cpuid_leaf_1D(Bit32u subfunction, cpuid_function_t *leaf) const
|
|
{
|
|
// CPUID function 0x80000001D - Cache Properties
|
|
switch(subfunction) {
|
|
case 0:
|
|
leaf->eax = 0x00000121;
|
|
leaf->ebx = 0x00C0003F;
|
|
leaf->ecx = 0x0000003F;
|
|
leaf->edx = 0x00000000;
|
|
return;
|
|
case 1:
|
|
leaf->eax = 0x00004122;
|
|
leaf->ebx = 0x0040003F;
|
|
leaf->ecx = 0x000001FF;
|
|
leaf->edx = 0x00000000;
|
|
return;
|
|
case 2:
|
|
leaf->eax = 0x00004143;
|
|
leaf->ebx = 0x03C0003F;
|
|
leaf->ecx = 0x000007FF;
|
|
leaf->edx = 0x00000001;
|
|
return;
|
|
default:
|
|
leaf->eax = 0;
|
|
leaf->ebx = 0;
|
|
leaf->ecx = 0;
|
|
leaf->edx = 0;
|
|
return;
|
|
}
|
|
}
|
|
|
|
void trinity_apu_t::get_ext_cpuid_leaf_1E(cpuid_function_t *leaf) const
|
|
{
|
|
// CPUID function 0x80000001E - Topology Extensions
|
|
leaf->eax = 0;
|
|
leaf->ebx = (ncores - 1) << 8;
|
|
leaf->ecx = 0;
|
|
leaf->edx = 0;
|
|
}
|
|
|
|
void trinity_apu_t::dump_cpuid(void) const
|
|
{
|
|
bx_cpuid_t::dump_cpuid(0xD, 0x1E);
|
|
}
|
|
|
|
bx_cpuid_t *create_trinity_apu_cpuid(BX_CPU_C *cpu) { return new trinity_apu_t(cpu); }
|
|
|
|
#endif
|