5899932f0c
- Fix lowest priority interrupt delivery from I/O APIC - XAPIC support - Implemented APIC bus functionality - cleanup APIC code
213 lines
7.0 KiB
C++
213 lines
7.0 KiB
C++
/////////////////////////////////////////////////////////////////////////
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// $Id: apic.h,v 1.25 2006-01-10 06:13:26 sshwarts Exp $
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/////////////////////////////////////////////////////////////////////////
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//
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// Copyright (C) 2001 MandrakeSoft S.A.
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//
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// MandrakeSoft S.A.
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// 43, rue d'Aboukir
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// 75002 Paris - France
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// http://www.linux-mandrake.com/
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// http://www.mandrakesoft.com/
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//
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// This library is free software; you can redistribute it and/or
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// modify it under the terms of the GNU Lesser General Public
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// License as published by the Free Software Foundation; either
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// version 2 of the License, or (at your option) any later version.
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//
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// This library is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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// Lesser General Public License for more details.
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//
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// You should have received a copy of the GNU Lesser General Public
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// License along with this library; if not, write to the Free Software
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// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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//
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/////////////////////////////////////////////////////////////////////////
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#ifndef BX_CPU_APIC_H
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# define BX_CPU_APIC_H 1
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#define APIC_BASE_ADDR 0xfee00000 // default APIC address
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#if BX_CPU_LEVEL == 6 && BX_SUPPORT_SSE >= 2
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#define BX_IMPLEMENT_XAPIC 1
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#endif
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#ifdef BX_IMPLEMENT_XAPIC
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# define APIC_VERSION_ID 0x00050014 // P4 has 6 LVT entries
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#else
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# define APIC_VERSION_ID 0x00040010 // P6 has 4 LVT entries
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#endif
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#if BX_SUPPORT_APIC
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#define BX_CPU_APIC(i) (&(BX_CPU(i)->local_apic))
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typedef enum {
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APIC_TYPE_IOAPIC,
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APIC_TYPE_LOCAL_APIC
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} bx_apic_type_t;
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#define BX_NUM_LOCAL_APICS BX_SMP_PROCESSORS
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class BOCHSAPI bx_generic_apic_c : public logfunctions {
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protected:
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bx_address base_addr;
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Bit8u id;
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#define APIC_UNKNOWN_ID 0xff
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public:
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bx_generic_apic_c ();
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virtual ~bx_generic_apic_c () { }
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// init is called during RESET and when an INIT message is delivered
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virtual void init () { }
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virtual void reset () { }
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bx_address get_base (void) const { return base_addr; }
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void set_base (bx_address newbase);
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void set_id (Bit8u newid);
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Bit8u get_id () const { return id; }
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bx_bool is_selected (bx_address addr, Bit32u len);
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void read (Bit32u addr, void *data, unsigned len);
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virtual void read_aligned(Bit32u address, Bit32u *data, unsigned len) = 0;
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virtual void write(Bit32u address, Bit32u *value, unsigned len) = 0;
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virtual bx_apic_type_t get_type () = 0;
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};
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#define BX_APIC_FIRST_VECTOR 0x10
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#define BX_APIC_LAST_VECTOR 0xfe
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#define BX_LOCAL_APIC_MAX_INTS 256
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#define APIC_LEVEL_TRIGGERED 1
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#define APIC_EDGE_TRIGGERED 0
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class BOCHSAPI bx_local_apic_c : public bx_generic_apic_c
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{
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Bit32u spurious_vector;
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bx_bool software_enabled;
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bx_bool focus_disable;
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Bit32u task_priority; // Task priority (TPR)
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Bit32u log_dest; // Logical destination (LDR)
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Bit32u dest_format; // Destination format (DFR)
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// ISR=in-service register. When an IRR bit is cleared, the corresponding
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// bit in ISR is set.
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Bit8u isr[BX_LOCAL_APIC_MAX_INTS];
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// TMR=trigger mode register. Cleared for edge-triggered interrupts
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// and set for level-triggered interrupts. If set, local APIC must send
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// EOI message to all other APICs.
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Bit8u tmr[BX_LOCAL_APIC_MAX_INTS];
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// IRR=interrupt request register. When an interrupt is triggered by
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// the I/O APIC or another processor, it sets a bit in irr. The bit is
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// cleared when the interrupt is acknowledged by the processor.
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Bit8u irr[BX_LOCAL_APIC_MAX_INTS];
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#define APIC_ERR_ILLEGAL_ADDR 0x80
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#define APIC_ERR_RX_ILLEGAL_VEC 0x40
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#define APIC_ERR_TX_ILLEGAL_VEC 0x20
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#define APIC_ERR_RX_ACCEPT_ERR 0x08
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#define APIC_ERR_TX_ACCEPT_ERR 0x04
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#define APIC_ERR_RX_CHECKSUM 0x02
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#define APIC_ERR_TX_CHECKSUM 0x01
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// Error status Register (ESR)
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Bit32u error_status, shadow_error_status;
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Bit32u icr_hi; // Interrupt command register (ICR)
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Bit32u icr_lo;
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#define APIC_LVT_ENTRIES 6
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Bit32u lvt[6];
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#define APIC_LVT_TIMER 0
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#define APIC_LVT_THERMAL 1
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#define APIC_LVT_PERFORM 2
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#define APIC_LVT_LINT0 3
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#define APIC_LVT_LINT1 4
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#define APIC_LVT_ERROR 5
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Bit32u timer_initial; // Initial timer count
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Bit32u timer_current; // current timer count
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Bit32u timer_divconf; // Timer divide configuration register
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Bit32u timer_divide_counter, timer_divide_factor;
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// Internal timer state, not accessible from bus
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bx_bool timer_active;
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int timer_handle;
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Bit64u ticksInitial;
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/* APIC delivery modes */
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#define APIC_DM_FIXED 0
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#define APIC_DM_LOWPRI 1
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#define APIC_DM_SMI 2
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/* RESERVED 3 */
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#define APIC_DM_NMI 4
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#define APIC_DM_INIT 5
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#define APIC_DM_SIPI 6
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#define APIC_DM_EXTINT 7
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BX_CPU_C *cpu;
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// corresponding BX_CPU_ID for the local APIC
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unsigned cpu_id;
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bx_bool bypass_irr_isr;
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public:
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bx_bool INTR;
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bx_local_apic_c(BX_CPU_C *cpu);
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virtual ~bx_local_apic_c(void) { }
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virtual void reset (void);
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virtual void init (void);
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BX_CPU_C *get_cpu () { return cpu; }
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void set_id (Bit8u newid); // redefine to set cpu->name
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virtual void write (Bit32u addr, Bit32u *data, unsigned len);
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virtual void read_aligned(Bit32u address, Bit32u *data, unsigned len);
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void startup_msg (Bit32u vector);
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// on local APIC, trigger means raise the CPU's INTR line. For now
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// I also have to raise pc_system.INTR but that should be replaced
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// with the cpu-specific INTR signals.
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void trigger_irq (unsigned num, unsigned trigger_mode);
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void untrigger_irq (unsigned num, unsigned trigger_mode);
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Bit8u acknowledge_int (void); // only the local CPU should call this
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int highest_priority_int (Bit8u *array);
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void receive_EOI(Bit32u value);
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void send_ipi(void);
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void write_spurious_interrupt_register(Bit32u value);
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void service_local_apic(void);
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void print_status(void);
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bx_bool match_logical_addr (Bit8u address);
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virtual bx_apic_type_t get_type(void) { return APIC_TYPE_LOCAL_APIC; }
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virtual bx_bool deliver (Bit8u vector, Bit8u delivery_mode, Bit8u trig_mode);
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Bit8u get_tpr (void);
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void set_tpr (Bit8u tpr);
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Bit8u get_ppr (void);
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Bit8u get_apr (void);
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bx_bool is_focus(Bit8u vector);
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static void periodic_smf(void *);
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void periodic(void);
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void set_divide_configuration(Bit32u value);
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void set_initial_timer_count(Bit32u value);
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/*
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Bit32u get_arb_id (void);
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void set_arb_id (Bit32u newid);
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*/
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};
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// For P6 and Pentium family processors the local APIC ID feild is 4 bits.
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#ifdef BX_IMPLEMENT_XAPIC
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#define APIC_MAX_ID 0xff
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#define APIC_ID_MASK 0xff
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#else
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#define APIC_MAX_ID 0x0f
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#define APIC_ID_MASK 0x0f
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#endif
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int apic_bus_deliver_lowest_priority(Bit8u vector, Bit8u dest, bx_bool trig_mode, bx_bool broadcast);
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int apic_bus_deliver_interrupt(Bit8u vector, Bit8u dest, Bit8u delivery_mode, Bit8u dest_mode, bx_bool level, bx_bool trig_mode);
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int apic_bus_broadcast_interrupt(Bit8u vector, Bit8u delivery_mode, bx_bool trig_mode, int exclude_cpu);
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#endif // if BX_SUPPORT_APIC
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#endif
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