49664f7503
tries to fix it. The shortcuts to register names such as AX and DL are #defines in cpu/cpu.h, and they are defined in terms of BX_CPU_THIS_PTR. When BX_USE_CPU_SMF=1, this works fine. (This is what bochs used for a long time, and nobody used the SMF=0 mode at all.) To make SMP bochs work, I had to get SMF=0 mode working for the CPU so that there could be an array of cpus. When SMF=0 for the CPU, BX_CPU_THIS_PTR is defined to be "this->" which only works within methods of BX_CPU_C. Code outside of BX_CPU_C must reference BX_CPU(num) instead. - to try to enforce the correct use of AL/AX/DL/etc. shortcuts, they are now only #defined when "NEED_CPU_REG_SHORTCUTS" is #defined. This is only done in the cpu/*.cc code.
875 lines
15 KiB
C++
875 lines
15 KiB
C++
// Copyright (C) 2001 MandrakeSoft S.A.
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//
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// MandrakeSoft S.A.
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// 43, rue d'Aboukir
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// 75002 Paris - France
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// http://www.linux-mandrake.com/
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// http://www.mandrakesoft.com/
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//
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// This library is free software; you can redistribute it and/or
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// modify it under the terms of the GNU Lesser General Public
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// License as published by the Free Software Foundation; either
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// version 2 of the License, or (at your option) any later version.
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//
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// This library is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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// Lesser General Public License for more details.
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//
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// You should have received a copy of the GNU Lesser General Public
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// License along with this library; if not, write to the Free Software
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// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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#define NEED_CPU_REG_SHORTCUTS 1
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#include "bochs.h"
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#define LOG_THIS BX_CPU_THIS_PTR
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/* MOVSB ES:[EDI], DS:[ESI] DS may be overridden
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* mov string from DS:[ESI] into ES:[EDI]
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*/
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void
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BX_CPU_C::MOVSB_XbYb(BxInstruction_t *i)
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{
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unsigned seg;
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Bit8u temp8;
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if (!BX_NULL_SEG_REG(i->seg)) {
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seg = i->seg;
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}
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else {
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seg = BX_SEG_REG_DS;
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}
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#if BX_CPU_LEVEL >= 3
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if (i->as_32) {
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Bit32u esi, edi;
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esi = ESI;
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edi = EDI;
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read_virtual_byte(seg, esi, &temp8);
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write_virtual_byte(BX_SEG_REG_ES, edi, &temp8);
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if (BX_CPU_THIS_PTR eflags.df) {
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/* decrement ESI, EDI */
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esi--;
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edi--;
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}
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else {
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/* increment ESI, EDI */
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esi++;
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edi++;
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}
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ESI = esi;
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EDI = edi;
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}
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else
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#endif /* BX_CPU_LEVEL >= 3 */
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{ /* 16 bit address mode */
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Bit16u si, di;
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si = SI;
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di = DI;
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read_virtual_byte(seg, si, &temp8);
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write_virtual_byte(BX_SEG_REG_ES, di, &temp8);
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if (BX_CPU_THIS_PTR eflags.df) {
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/* decrement SI, DI */
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si--;
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di--;
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}
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else {
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/* increment SI, DI */
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si++;
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di++;
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}
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SI = si;
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DI = di;
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}
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}
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void
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BX_CPU_C::MOVSW_XvYv(BxInstruction_t *i)
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{
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unsigned seg;
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if (!BX_NULL_SEG_REG(i->seg)) {
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seg = i->seg;
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}
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else {
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seg = BX_SEG_REG_DS;
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}
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#if BX_CPU_LEVEL >= 3
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if (i->as_32) {
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Bit32u temp32;
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Bit32u esi, edi;
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esi = ESI;
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edi = EDI;
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if (i->os_32) {
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read_virtual_dword(seg, esi, &temp32);
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write_virtual_dword(BX_SEG_REG_ES, edi, &temp32);
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if (BX_CPU_THIS_PTR eflags.df) {
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/* decrement ESI */
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esi -= 4;
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edi -= 4;
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}
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else {
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/* increment ESI */
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esi += 4;
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edi += 4;
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}
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} /* if (i->os_32) ... */
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else { /* 16 bit opsize mode */
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Bit16u temp16;
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read_virtual_word(seg, esi, &temp16);
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write_virtual_word(BX_SEG_REG_ES, edi, &temp16);
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if (BX_CPU_THIS_PTR eflags.df) {
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/* decrement ESI */
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esi -= 2;
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edi -= 2;
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}
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else {
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/* increment ESI */
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esi += 2;
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edi += 2;
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}
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}
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ESI = esi;
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EDI = edi;
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}
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else
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#endif /* BX_CPU_LEVEL >= 3 */
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{ /* 16bit address mode */
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Bit16u si, di;
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si = SI;
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di = DI;
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#if BX_CPU_LEVEL >= 3
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if (i->os_32) {
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Bit32u temp32;
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read_virtual_dword(seg, si, &temp32);
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write_virtual_dword(BX_SEG_REG_ES, di, &temp32);
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if (BX_CPU_THIS_PTR eflags.df) {
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/* decrement ESI */
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si -= 4;
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di -= 4;
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}
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else {
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/* increment ESI */
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si += 4;
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di += 4;
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}
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} /* if (i->os_32) ... */
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else
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#endif /* BX_CPU_LEVEL >= 3 */
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{ /* 16 bit opsize mode */
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Bit16u temp16;
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read_virtual_word(seg, si, &temp16);
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write_virtual_word(BX_SEG_REG_ES, di, &temp16);
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if (BX_CPU_THIS_PTR eflags.df) {
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/* decrement SI, DI */
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si -= 2;
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di -= 2;
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}
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else {
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/* increment SI, DI */
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si += 2;
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di += 2;
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}
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}
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SI = si;
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DI = di;
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}
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}
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void
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BX_CPU_C::CMPSB_XbYb(BxInstruction_t *i)
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{
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unsigned seg;
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Bit8u op1_8, op2_8, diff_8;
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if (!BX_NULL_SEG_REG(i->seg)) {
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seg = i->seg;
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}
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else {
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seg = BX_SEG_REG_DS;
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}
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#if BX_CPU_LEVEL >= 3
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if (i->as_32) {
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Bit32u esi, edi;
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esi = ESI;
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edi = EDI;
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read_virtual_byte(seg, esi, &op1_8);
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read_virtual_byte(BX_SEG_REG_ES, edi, &op2_8);
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diff_8 = op1_8 - op2_8;
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SET_FLAGS_OSZAPC_8(op1_8, op2_8, diff_8, BX_INSTR_CMPS8);
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if (BX_CPU_THIS_PTR eflags.df) {
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/* decrement ESI */
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esi--;
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edi--;
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}
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else {
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/* increment ESI */
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esi++;
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edi++;
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}
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EDI = edi;
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ESI = esi;
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}
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else
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#endif /* BX_CPU_LEVEL >= 3 */
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{ /* 16bit address mode */
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Bit16u si, di;
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si = SI;
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di = DI;
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read_virtual_byte(seg, si, &op1_8);
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read_virtual_byte(BX_SEG_REG_ES, di, &op2_8);
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diff_8 = op1_8 - op2_8;
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SET_FLAGS_OSZAPC_8(op1_8, op2_8, diff_8, BX_INSTR_CMPS8);
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if (BX_CPU_THIS_PTR eflags.df) {
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/* decrement ESI */
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si--;
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di--;
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}
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else {
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/* increment ESI */
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si++;
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di++;
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}
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DI = di;
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SI = si;
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}
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}
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void
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BX_CPU_C::CMPSW_XvYv(BxInstruction_t *i)
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{
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unsigned seg;
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if (!BX_NULL_SEG_REG(i->seg)) {
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seg = i->seg;
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}
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else {
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seg = BX_SEG_REG_DS;
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}
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#if BX_CPU_LEVEL >= 3
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if (i->as_32) {
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Bit32u op1_32, op2_32, diff_32;
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Bit32u esi, edi;
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esi = ESI;
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edi = EDI;
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if (i->os_32) {
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read_virtual_dword(seg, esi, &op1_32);
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read_virtual_dword(BX_SEG_REG_ES, edi, &op2_32);
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diff_32 = op1_32 - op2_32;
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SET_FLAGS_OSZAPC_32(op1_32, op2_32, diff_32, BX_INSTR_CMPS32);
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if (BX_CPU_THIS_PTR eflags.df) {
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/* decrement ESI */
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esi -= 4;
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edi -= 4;
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}
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else {
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/* increment ESI */
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esi += 4;
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edi += 4;
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}
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}
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else { /* 16 bit opsize */
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Bit16u op1_16, op2_16, diff_16;
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read_virtual_word(seg, esi, &op1_16);
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read_virtual_word(BX_SEG_REG_ES, edi, &op2_16);
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diff_16 = op1_16 - op2_16;
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SET_FLAGS_OSZAPC_16(op1_16, op2_16, diff_16, BX_INSTR_CMPS16);
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if (BX_CPU_THIS_PTR eflags.df) {
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/* decrement ESI */
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esi -= 2;
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edi -= 2;
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}
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else {
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/* increment ESI */
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esi += 2;
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edi += 2;
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}
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}
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EDI = edi;
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ESI = esi;
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}
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else
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#endif /* BX_CPU_LEVEL >= 3 */
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{ /* 16 bit address mode */
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Bit16u si, di;
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si = SI;
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di = DI;
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#if BX_CPU_LEVEL >= 3
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if (i->os_32) {
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Bit32u op1_32, op2_32, diff_32;
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read_virtual_dword(seg, si, &op1_32);
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read_virtual_dword(BX_SEG_REG_ES, di, &op2_32);
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diff_32 = op1_32 - op2_32;
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SET_FLAGS_OSZAPC_32(op1_32, op2_32, diff_32, BX_INSTR_CMPS32);
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if (BX_CPU_THIS_PTR eflags.df) {
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/* decrement ESI */
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si -= 4;
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di -= 4;
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}
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else {
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/* increment ESI */
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si += 4;
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di += 4;
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}
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}
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else
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#endif /* BX_CPU_LEVEL >= 3 */
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{ /* 16 bit opsize */
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Bit16u op1_16, op2_16, diff_16;
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read_virtual_word(seg, si, &op1_16);
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read_virtual_word(BX_SEG_REG_ES, di, &op2_16);
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diff_16 = op1_16 - op2_16;
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SET_FLAGS_OSZAPC_16(op1_16, op2_16, diff_16, BX_INSTR_CMPS16);
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if (BX_CPU_THIS_PTR eflags.df) {
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/* decrement ESI */
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si -= 2;
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di -= 2;
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}
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else {
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/* increment ESI */
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si += 2;
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di += 2;
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}
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}
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DI = di;
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SI = si;
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}
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}
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void
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BX_CPU_C::SCASB_ALXb(BxInstruction_t *i)
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{
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Bit8u op1_8, op2_8, diff_8;
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#if BX_CPU_LEVEL >= 3
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if (i->as_32) {
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Bit32u edi;
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edi = EDI;
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op1_8 = AL;
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read_virtual_byte(BX_SEG_REG_ES, edi, &op2_8);
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diff_8 = op1_8 - op2_8;
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SET_FLAGS_OSZAPC_8(op1_8, op2_8, diff_8, BX_INSTR_SCAS8);
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if (BX_CPU_THIS_PTR eflags.df) {
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/* decrement ESI */
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edi--;
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}
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else {
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/* increment ESI */
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edi++;
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}
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EDI = edi;
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}
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else
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#endif /* BX_CPU_LEVEL >= 3 */
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{ /* 16bit address mode */
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Bit16u di;
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di = DI;
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op1_8 = AL;
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read_virtual_byte(BX_SEG_REG_ES, di, &op2_8);
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diff_8 = op1_8 - op2_8;
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SET_FLAGS_OSZAPC_8(op1_8, op2_8, diff_8, BX_INSTR_SCAS8);
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if (BX_CPU_THIS_PTR eflags.df) {
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/* decrement ESI */
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di--;
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}
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else {
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/* increment ESI */
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di++;
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}
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DI = di;
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}
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}
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void
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BX_CPU_C::SCASW_eAXXv(BxInstruction_t *i)
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{
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#if BX_CPU_LEVEL >= 3
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if (i->as_32) {
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Bit32u edi;
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edi = EDI;
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if (i->os_32) {
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Bit32u op1_32, op2_32, diff_32;
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op1_32 = EAX;
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read_virtual_dword(BX_SEG_REG_ES, edi, &op2_32);
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diff_32 = op1_32 - op2_32;
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SET_FLAGS_OSZAPC_32(op1_32, op2_32, diff_32, BX_INSTR_SCAS32);
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if (BX_CPU_THIS_PTR eflags.df) {
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/* decrement ESI */
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edi -= 4;
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}
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else {
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/* increment ESI */
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edi += 4;
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}
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}
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else { /* 16 bit opsize */
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Bit16u op1_16, op2_16, diff_16;
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op1_16 = AX;
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read_virtual_word(BX_SEG_REG_ES, edi, &op2_16);
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diff_16 = op1_16 - op2_16;
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SET_FLAGS_OSZAPC_16(op1_16, op2_16, diff_16, BX_INSTR_SCAS16);
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if (BX_CPU_THIS_PTR eflags.df) {
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/* decrement ESI */
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edi -= 2;
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}
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else {
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/* increment ESI */
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edi += 2;
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}
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}
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EDI = edi;
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}
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else
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#endif /* BX_CPU_LEVEL >= 3 */
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{ /* 16bit address mode */
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Bit16u di;
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di = DI;
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#if BX_CPU_LEVEL >= 3
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if (i->os_32) {
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Bit32u op1_32, op2_32, diff_32;
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op1_32 = EAX;
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read_virtual_dword(BX_SEG_REG_ES, di, &op2_32);
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diff_32 = op1_32 - op2_32;
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SET_FLAGS_OSZAPC_32(op1_32, op2_32, diff_32, BX_INSTR_SCAS32);
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if (BX_CPU_THIS_PTR eflags.df) {
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/* decrement ESI */
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di -= 4;
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}
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else {
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/* increment ESI */
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di += 4;
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}
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}
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else
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#endif /* BX_CPU_LEVEL >= 3 */
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{ /* 16 bit opsize */
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Bit16u op1_16, op2_16, diff_16;
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op1_16 = AX;
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read_virtual_word(BX_SEG_REG_ES, di, &op2_16);
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diff_16 = op1_16 - op2_16;
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SET_FLAGS_OSZAPC_16(op1_16, op2_16, diff_16, BX_INSTR_SCAS16);
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if (BX_CPU_THIS_PTR eflags.df) {
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/* decrement ESI */
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di -= 2;
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}
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else {
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/* increment ESI */
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di += 2;
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}
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}
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DI = di;
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|
}
|
|
}
|
|
|
|
void
|
|
BX_CPU_C::STOSB_YbAL(BxInstruction_t *i)
|
|
{
|
|
Bit8u al;
|
|
|
|
#if BX_CPU_LEVEL >= 3
|
|
if (i->as_32) {
|
|
Bit32u edi;
|
|
|
|
edi = EDI;
|
|
|
|
al = AL;
|
|
write_virtual_byte(BX_SEG_REG_ES, edi, &al);
|
|
|
|
if (BX_CPU_THIS_PTR eflags.df) {
|
|
/* decrement EDI */
|
|
edi--;
|
|
}
|
|
else {
|
|
/* increment EDI */
|
|
edi++;
|
|
}
|
|
|
|
EDI = edi;
|
|
}
|
|
else
|
|
#endif /* BX_CPU_LEVEL >= 3 */
|
|
{ /* 16bit address size */
|
|
Bit16u di;
|
|
|
|
di = DI;
|
|
|
|
al = AL;
|
|
write_virtual_byte(BX_SEG_REG_ES, di, &al);
|
|
|
|
if (BX_CPU_THIS_PTR eflags.df) {
|
|
/* decrement EDI */
|
|
di--;
|
|
}
|
|
else {
|
|
/* increment EDI */
|
|
di++;
|
|
}
|
|
|
|
DI = di;
|
|
}
|
|
}
|
|
|
|
void
|
|
BX_CPU_C::STOSW_YveAX(BxInstruction_t *i)
|
|
{
|
|
#if BX_CPU_LEVEL >= 3
|
|
if (i->as_32) {
|
|
Bit32u edi;
|
|
|
|
edi = EDI;
|
|
|
|
if (i->os_32) {
|
|
Bit32u eax;
|
|
|
|
eax = EAX;
|
|
write_virtual_dword(BX_SEG_REG_ES, edi, &eax);
|
|
|
|
if (BX_CPU_THIS_PTR eflags.df) {
|
|
/* decrement EDI */
|
|
edi -= 4;
|
|
}
|
|
else {
|
|
/* increment EDI */
|
|
edi += 4;
|
|
}
|
|
} /* if (i->os_32) ... */
|
|
else { /* 16 bit opsize mode */
|
|
Bit16u ax;
|
|
|
|
ax = AX;
|
|
write_virtual_word(BX_SEG_REG_ES, edi, &ax);
|
|
|
|
if (BX_CPU_THIS_PTR eflags.df) {
|
|
/* decrement EDI */
|
|
edi -= 2;
|
|
}
|
|
else {
|
|
/* increment EDI */
|
|
edi += 2;
|
|
}
|
|
}
|
|
|
|
EDI = edi;
|
|
}
|
|
|
|
else
|
|
#endif /* BX_CPU_LEVEL >= 3 */
|
|
{ /* 16bit address size */
|
|
Bit16u di;
|
|
|
|
di = DI;
|
|
|
|
#if BX_CPU_LEVEL >= 3
|
|
if (i->os_32) {
|
|
Bit32u eax;
|
|
|
|
eax = EAX;
|
|
write_virtual_dword(BX_SEG_REG_ES, di, &eax);
|
|
|
|
if (BX_CPU_THIS_PTR eflags.df) {
|
|
/* decrement EDI */
|
|
di -= 4;
|
|
}
|
|
else {
|
|
/* increment EDI */
|
|
di += 4;
|
|
}
|
|
} /* if (i->os_32) ... */
|
|
else
|
|
#endif /* BX_CPU_LEVEL >= 3 */
|
|
{ /* 16 bit opsize mode */
|
|
Bit16u ax;
|
|
|
|
ax = AX;
|
|
write_virtual_word(BX_SEG_REG_ES, di, &ax);
|
|
|
|
if (BX_CPU_THIS_PTR eflags.df) {
|
|
/* decrement EDI */
|
|
di -= 2;
|
|
}
|
|
else {
|
|
/* increment EDI */
|
|
di += 2;
|
|
}
|
|
}
|
|
|
|
DI = di;
|
|
}
|
|
}
|
|
|
|
|
|
void
|
|
BX_CPU_C::LODSB_ALXb(BxInstruction_t *i)
|
|
{
|
|
unsigned seg;
|
|
Bit8u al;
|
|
|
|
if (!BX_NULL_SEG_REG(i->seg)) {
|
|
seg = i->seg;
|
|
}
|
|
else {
|
|
seg = BX_SEG_REG_DS;
|
|
}
|
|
|
|
#if BX_CPU_LEVEL >= 3
|
|
if (i->as_32) {
|
|
Bit32u esi;
|
|
|
|
esi = ESI;
|
|
|
|
read_virtual_byte(seg, esi, &al);
|
|
|
|
AL = al;
|
|
if (BX_CPU_THIS_PTR eflags.df) {
|
|
/* decrement ESI */
|
|
esi--;
|
|
}
|
|
else {
|
|
/* increment ESI */
|
|
esi++;
|
|
}
|
|
|
|
ESI = esi;
|
|
}
|
|
else
|
|
#endif /* BX_CPU_LEVEL >= 3 */
|
|
{ /* 16bit address mode */
|
|
Bit16u si;
|
|
|
|
si = SI;
|
|
|
|
read_virtual_byte(seg, si, &al);
|
|
|
|
AL = al;
|
|
if (BX_CPU_THIS_PTR eflags.df) {
|
|
/* decrement ESI */
|
|
si--;
|
|
}
|
|
else {
|
|
/* increment ESI */
|
|
si++;
|
|
}
|
|
|
|
SI = si;
|
|
}
|
|
}
|
|
|
|
void
|
|
BX_CPU_C::LODSW_eAXXv(BxInstruction_t *i)
|
|
{
|
|
unsigned seg;
|
|
|
|
if (!BX_NULL_SEG_REG(i->seg)) {
|
|
seg = i->seg;
|
|
}
|
|
else {
|
|
seg = BX_SEG_REG_DS;
|
|
}
|
|
|
|
#if BX_CPU_LEVEL >= 3
|
|
if (i->as_32) {
|
|
Bit32u esi;
|
|
|
|
esi = ESI;
|
|
|
|
if (i->os_32) {
|
|
Bit32u eax;
|
|
|
|
read_virtual_dword(seg, esi, &eax);
|
|
|
|
EAX = eax;
|
|
if (BX_CPU_THIS_PTR eflags.df) {
|
|
/* decrement ESI */
|
|
esi -= 4;
|
|
}
|
|
else {
|
|
/* increment ESI */
|
|
esi += 4;
|
|
}
|
|
} /* if (i->os_32) ... */
|
|
else { /* 16 bit opsize mode */
|
|
Bit16u ax;
|
|
read_virtual_word(seg, esi, &ax);
|
|
|
|
AX = ax;
|
|
if (BX_CPU_THIS_PTR eflags.df) {
|
|
/* decrement ESI */
|
|
esi -= 2;
|
|
}
|
|
else {
|
|
/* increment ESI */
|
|
esi += 2;
|
|
}
|
|
}
|
|
|
|
ESI = esi;
|
|
}
|
|
else
|
|
#endif /* BX_CPU_LEVEL >= 3 */
|
|
{ /* 16bit address mode */
|
|
Bit16u si;
|
|
|
|
si = SI;
|
|
|
|
#if BX_CPU_LEVEL >= 3
|
|
if (i->os_32) {
|
|
Bit32u eax;
|
|
|
|
read_virtual_dword(seg, si, &eax);
|
|
|
|
EAX = eax;
|
|
if (BX_CPU_THIS_PTR eflags.df) {
|
|
/* decrement ESI */
|
|
si -= 4;
|
|
}
|
|
else {
|
|
/* increment ESI */
|
|
si += 4;
|
|
}
|
|
}
|
|
else
|
|
#endif /* BX_CPU_LEVEL >= 3 */
|
|
{ /* 16 bit opsize mode */
|
|
Bit16u ax;
|
|
|
|
read_virtual_word(seg, si, &ax);
|
|
|
|
AX = ax;
|
|
if (BX_CPU_THIS_PTR eflags.df) {
|
|
/* decrement ESI */
|
|
si -= 2;
|
|
}
|
|
else {
|
|
/* increment ESI */
|
|
si += 2;
|
|
}
|
|
}
|
|
|
|
SI = si;
|
|
}
|
|
}
|