199 lines
6.4 KiB
C
Executable File
199 lines
6.4 KiB
C
Executable File
/////////////////////////////////////////////////////////////////////////
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// $Id: crregs.h,v 1.17 2009-01-31 10:43:23 sshwarts Exp $
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/////////////////////////////////////////////////////////////////////////
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//
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// Copyright (c) 2007 Stanislav Shwartsman
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// Written by Stanislav Shwartsman [sshwarts at sourceforge net]
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//
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// This library is free software; you can redistribute it and/or
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// modify it under the terms of the GNU Lesser General Public
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// License as published by the Free Software Foundation; either
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// version 2 of the License, or (at your option) any later version.
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//
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// This library is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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// Lesser General Public License for more details.
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//
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// You should have received a copy of the GNU Lesser General Public
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// License along with this library; if not, write to the Free Software
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// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA B 02110-1301 USA
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//
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/////////////////////////////////////////////////////////////////////////
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#ifndef BX_CRREGS
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#define BX_CRREGS
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struct bx_cr0_t {
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Bit32u val32; // 32bit value of register
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// Accessors for all cr0 bitfields.
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#define IMPLEMENT_CRREG_ACCESSORS(name,bitnum) \
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BX_CPP_INLINE bx_bool get_##name () { \
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return 1 & (val32 >> bitnum); \
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} \
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BX_CPP_INLINE void set_##name (Bit8u val) { \
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val32 = (val32&~(1<<bitnum)) | (val ? (1<<bitnum) : 0); \
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}
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// CR0 notes:
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// Each x86 level has its own quirks regarding how it handles
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// reserved bits. I used DOS DEBUG.EXE in real mode on the
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// following processors, tried to clear bits 1..30, then tried
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// to set bits 1..30, to see how these bits are handled.
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// I found the following:
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//
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// Processor try to clear bits 1..30 try to set bits 1..30
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// 386 7FFFFFF0 7FFFFFFE
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// 486DX2 00000010 6005003E
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// Pentium 00000010 7FFFFFFE
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// Pentium-II 00000010 6005003E
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//
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// My assumptions:
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// All processors: bit 4 is hardwired to 1 (not true on all clones)
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// 386: bits 5..30 of CR0 are also hardwired to 1
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// Pentium: reserved bits retain value set using mov cr0, reg32
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// 486DX2/Pentium-II: reserved bits are hardwired to 0
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IMPLEMENT_CRREG_ACCESSORS(PE, 0);
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IMPLEMENT_CRREG_ACCESSORS(MP, 1);
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IMPLEMENT_CRREG_ACCESSORS(EM, 2);
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IMPLEMENT_CRREG_ACCESSORS(TS, 3);
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#if BX_CPU_LEVEL >= 4
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IMPLEMENT_CRREG_ACCESSORS(ET, 4);
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IMPLEMENT_CRREG_ACCESSORS(NE, 5);
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IMPLEMENT_CRREG_ACCESSORS(WP, 16);
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IMPLEMENT_CRREG_ACCESSORS(AM, 18);
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IMPLEMENT_CRREG_ACCESSORS(CD, 29);
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IMPLEMENT_CRREG_ACCESSORS(NW, 30);
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#endif
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IMPLEMENT_CRREG_ACCESSORS(PG, 31);
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BX_CPP_INLINE Bit32u get32() { return val32; }
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// ET is hardwired bit in CR0
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BX_CPP_INLINE void set32(Bit32u val) { val32 = val | 0x10; }
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};
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#if BX_CPU_LEVEL >= 4
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struct bx_cr4_t {
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Bit32u val32; // 32bit value of register
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#if BX_SUPPORT_VME
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IMPLEMENT_CRREG_ACCESSORS(VME, 0);
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IMPLEMENT_CRREG_ACCESSORS(PVI, 1);
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#endif
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IMPLEMENT_CRREG_ACCESSORS(TSD, 2);
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IMPLEMENT_CRREG_ACCESSORS(DE, 3);
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IMPLEMENT_CRREG_ACCESSORS(PSE, 4);
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IMPLEMENT_CRREG_ACCESSORS(PAE, 5);
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IMPLEMENT_CRREG_ACCESSORS(MCE, 6);
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IMPLEMENT_CRREG_ACCESSORS(PGE, 7);
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IMPLEMENT_CRREG_ACCESSORS(PCE, 8);
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IMPLEMENT_CRREG_ACCESSORS(OSFXSR, 9);
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IMPLEMENT_CRREG_ACCESSORS(OSXMMEXCPT, 10);
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#if BX_SUPPORT_VMX
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IMPLEMENT_CRREG_ACCESSORS(VMXE, 13);
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#endif
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#if BX_SUPPORT_XSAVE
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IMPLEMENT_CRREG_ACCESSORS(OSXSAVE, 18);
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#endif
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BX_CPP_INLINE Bit32u get32() { return val32; }
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BX_CPP_INLINE void set32(Bit32u val) { val32 = val; }
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};
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#endif // #if BX_CPU_LEVEL >= 4
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extern bx_address get_cr4_allow_mask(void);
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#if BX_SUPPORT_VME
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#define BX_CR4_VME_ENABLED (BX_CPU_THIS_PTR cr4.get_VME())
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#else
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#define BX_CR4_VME_ENABLED (0)
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#endif
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#if BX_SUPPORT_X86_64
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struct bx_efer_t {
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Bit32u val32; // 32bit value of register
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IMPLEMENT_CRREG_ACCESSORS(SCE, 0);
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IMPLEMENT_CRREG_ACCESSORS(LME, 8);
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IMPLEMENT_CRREG_ACCESSORS(LMA, 10);
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IMPLEMENT_CRREG_ACCESSORS(NXE, 11);
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IMPLEMENT_CRREG_ACCESSORS(FFXSR, 14);
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BX_CPP_INLINE Bit32u get32() { return val32; }
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BX_CPP_INLINE void set32(Bit32u val) { val32 = val; }
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};
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#define BX_EFER_LMA_MASK (1<<10)
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#define BX_EFER_SUPPORTED_BITS BX_CONST64(0x00004d01)
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#endif
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#if BX_SUPPORT_XSAVE
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struct xcr0_t {
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Bit32u val32; // 32bit value of register
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#define BX_XCR0_SUPPORTED_BITS 0x3
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#define BX_XCR0_FPU_BIT 0
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#define BX_XCR0_FPU_MASK (1<<BX_XCR0_FPU_BIT)
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#define BX_XCR0_SSE_BIT 1
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#define BX_XCR0_SSE_MASK (1<<BX_XCR0_SSE_BIT)
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IMPLEMENT_CRREG_ACCESSORS(FPU, BX_XCR0_FPU_BIT);
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#if BX_SUPPORT_SSE
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IMPLEMENT_CRREG_ACCESSORS(SSE, BX_XCR0_SSE_BIT);
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#endif
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BX_CPP_INLINE Bit32u get32() { return val32; }
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BX_CPP_INLINE void set32(Bit32u val) { val32 = val; }
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};
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#endif
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#undef IMPLEMENT_CRREG_ACCESSORS
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typedef struct msr {
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unsigned index; // MSR index
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unsigned type; // MSR type: 1 - lin address, 2 - phy address
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#define BX_LIN_ADDRESS_MSR 1
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#define BX_PHY_ADDRESS_MSR 2
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Bit64u val64; // current MSR value
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Bit64u reset_value; // reset value
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Bit64u reserved; // r/o bits - fault on write
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Bit64u ignored; // hardwired bits - ignored on write
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msr(unsigned idx, unsigned msr_type = 0, Bit64u reset_val = 0, Bit64u rsrv = 0, Bit64u ign = 0):
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index(idx), type(msr_type), val64(reset_val), reset_value(reset_val),
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reserved(rsrv), ignored(ign) {}
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msr(unsigned idx, Bit64u reset_val = 0, Bit64u rsrv = 0, Bit64u ign = 0):
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index(idx), type(0), val64(reset_val), reset_value(reset_val),
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reserved(rsrv), ignored(ign) {}
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BX_CPP_INLINE void reset() { val64 = reset_value; }
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BX_CPP_INLINE Bit64u get64() { return val64; }
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BX_CPP_INLINE bx_bool set64(Bit64u new_val) {
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new_val = (new_val & ~ignored) | (val64 & ignored);
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switch(type) {
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#if BX_SUPPORT_X86_64
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case BX_LIN_ADDRESS_MSR:
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if (! IsCanonical(new_val)) return 0;
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break;
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#endif
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case BX_PHY_ADDRESS_MSR:
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if (! IsValidPhyAddr(new_val)) return 0;
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break;
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default:
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if ((val64 ^ new_val) & reserved) return 0;
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break;
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}
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val64 = new_val;
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return 1;
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}
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} MSR;
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#endif
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