bb7a648d91
------------ Implemented SVN nested paging support - the Virtual Box boots perfectly with Nested Paging guest ! A lot of code duplication was added for now - major cleanup will follow later. ! Added AMD Phenom X3 8650 (Toliman) configuration to the CPUDB - this configuration has Nested Paging enabled. Some CPUID modules rework done to enable Toliman configuration. Ckean up 'executable' attribute from all CPU source files.
57 lines
1.4 KiB
Plaintext
57 lines
1.4 KiB
Plaintext
TODO (know issues in CPU model):
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-------------------------------
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[!] The following 3DNow! instructions still not implemented:
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PF2IW_PqQq
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PFNACC_PqQq
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PFPNACC_PqQq
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PFCMPGE_PqQq
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PFCMPGT_PqQq
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PFCMPEQ_PqQq
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PFMIN_PqQq
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PFMAX_PqQq
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PFRCP_PqQq
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PFRSQRT_PqQq
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PFSUB_PqQq
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PFSUBR_PqQq
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PFADD_PqQq
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PFACC_PqQq,
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PFMUL_PqQq
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PFRCPIT1_PqQq
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PFRSQIT1_PqQq
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PFRCPIT2_PqQq
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[!] CPUID does not report 3DNow! instruction set
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[!] Some of APIC functionality still not implemented, for example
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- LVT pins handling
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- Filter interrupts according processor priority (PPR)
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[!] REP NOP is PAUSE (on P4/XEON)
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When running in SMP mode, this means that we are in a spin loop.
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This processor should yield to the other one, as we are anyhow waiting
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for a lock, and any other processor is responsible for this.
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[!] 32-bit linear address wrap when executing in legacy mode might be
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not implemented correctly for system memory accesses (like descriptor
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tables and etc)
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[!] AMD and Intel x86_64 implementations are different.
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Currently Bochs emulation is according to Intel version.
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Do we need to support both ?
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[!] VMX:
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- Dual-monitor treatment of SMIs and SMM not implemented yet
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- VMENTER to not-active state not supported yet
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[!] SVM:
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- Decoding assists, pause filter, VMCB clean are not implemented yet
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- More?
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[!] TODO: Convert CPUDB to plugins and search for them in runtime
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