d4688e8b95
for CPU emulation performance reasons, the alignment check compilation
still can be enabled using configure option --enable-alignment-check.
There is no software in the world which enable #AC exception checking, this
x86 feature is completely legacy but its emulation support costs up to 3-5%
emulation speed.
The checking for #AC exception enable still will be done, if
CPL == 3, EFLAGS.AC = 1 and CR0.AM = 1
but the alignment check is not compiled in, the Bochs will PANIC with corresponding message.
You can press 'always continue' and ignore the PANIC, the simulation will continue as if alignment checking is not enabled.
112 lines
3.4 KiB
C++
112 lines
3.4 KiB
C++
/////////////////////////////////////////////////////////////////////////
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// $Id$
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/////////////////////////////////////////////////////////////////////////
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//
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// Copyright (C) 2001-2011 The Bochs Project
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//
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// This library is free software; you can redistribute it and/or
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// modify it under the terms of the GNU Lesser General Public
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// License as published by the Free Software Foundation; either
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// version 2 of the License, or (at your option) any later version.
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//
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// This library is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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// Lesser General Public License for more details.
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//
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// You should have received a copy of the GNU Lesser General Public
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// License along with this library; if not, write to the Free Software
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// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA B 02110-1301 USA
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//
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/////////////////////////////////////////////////////////////////////////
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#define NEED_CPU_REG_SHORTCUTS 1
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#include "bochs.h"
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#include "cpu.h"
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#define LOG_THIS BX_CPU_THIS_PTR
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void BX_CPP_AttrRegparmN(1) BX_CPU_C::setEFlags(Bit32u val)
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{
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// VM flag could not be set from long mode
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#if BX_SUPPORT_X86_64
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if (long_mode()) {
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if (BX_CPU_THIS_PTR get_VM()) BX_PANIC(("VM is set in long mode !"));
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val &= ~EFlagsVMMask;
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}
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#endif
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if (val & EFlagsRFMask) invalidate_prefetch_q();
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if (val & EFlagsTFMask) {
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BX_CPU_THIS_PTR async_event = 1; // TF == 1 || RF == 1
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}
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if (val & EFlagsIFMask) {
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if (! BX_CPU_THIS_PTR get_IF())
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BX_CPU_THIS_PTR async_event = 1; // IF bit was set
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}
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BX_CPU_THIS_PTR eflags = val;
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setEFlagsOSZAPC(val); // update lazy flags state
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#if BX_CPU_LEVEL >= 4
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handleAlignmentCheck(/* EFLAGS.AC reloaded */);
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#endif
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handleCpuModeChange(); // VM flag might be changed
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}
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void BX_CPP_AttrRegparmN(2)
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BX_CPU_C::writeEFlags(Bit32u flags, Bit32u changeMask)
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{
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// Build a mask of the non-reserved bits:
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// ID,VIP,VIF,AC,VM,RF,x,NT,IOPL,OF,DF,IF,TF,SF,ZF,x,AF,x,PF,x,CF
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Bit32u supportMask = 0x00037fd5;
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#if BX_CPU_LEVEL >= 4
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supportMask |= (EFlagsIDMask | EFlagsACMask); // ID/AC
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#endif
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#if BX_CPU_LEVEL >= 5
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supportMask |= (EFlagsVIPMask | EFlagsVIFMask); // VIP/VIF
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#endif
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// Screen out changing of any unsupported bits.
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changeMask &= supportMask;
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Bit32u newEFlags = (read_eflags() & ~changeMask) | (flags & changeMask);
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setEFlags(newEFlags);
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}
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void BX_CPP_AttrRegparmN(3)
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BX_CPU_C::write_flags(Bit16u flags, bx_bool change_IOPL, bx_bool change_IF)
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{
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// Build a mask of the following bits:
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// x,NT,IOPL,OF,DF,IF,TF,SF,ZF,x,AF,x,PF,x,CF
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Bit32u changeMask = 0x0dd5;
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#if BX_CPU_LEVEL >= 3
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changeMask |= EFlagsNTMask; // NT is modified as requested.
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if (change_IOPL)
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changeMask |= EFlagsIOPLMask; // IOPL is modified as requested.
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#endif
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if (change_IF)
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changeMask |= EFlagsIFMask;
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writeEFlags(Bit32u(flags), changeMask);
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}
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// Cause arithmetic flags to be in known state and cached in val32.
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Bit32u BX_CPU_C::force_flags(void)
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{
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Bit32u newflags = getB_CF();
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newflags |= getB_PF() << 2;
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newflags |= getB_AF() << 4;
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newflags |= getB_ZF() << 6;
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newflags |= getB_SF() << 7;
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newflags |= getB_OF() << 11;
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BX_CPU_THIS_PTR eflags = (BX_CPU_THIS_PTR eflags & ~EFlagsOSZAPCMask)
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| (newflags & EFlagsOSZAPCMask);
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return BX_CPU_THIS_PTR eflags;
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}
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