403 lines
9.0 KiB
C++
403 lines
9.0 KiB
C++
/////////////////////////////////////////////////////////////////////////
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// $Id: data_xfer64.cc,v 1.20 2004-11-26 20:21:27 sshwarts Exp $
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/////////////////////////////////////////////////////////////////////////
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//
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// Copyright (C) 2001 MandrakeSoft S.A.
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//
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// MandrakeSoft S.A.
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// 43, rue d'Aboukir
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// 75002 Paris - France
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// http://www.linux-mandrake.com/
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// http://www.mandrakesoft.com/
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//
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// This library is free software; you can redistribute it and/or
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// modify it under the terms of the GNU Lesser General Public
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// License as published by the Free Software Foundation; either
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// version 2 of the License, or (at your option) any later version.
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//
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// This library is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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// Lesser General Public License for more details.
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//
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// You should have received a copy of the GNU Lesser General Public
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// License along with this library; if not, write to the Free Software
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// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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#define NEED_CPU_REG_SHORTCUTS 1
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#include "bochs.h"
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#define LOG_THIS BX_CPU_THIS_PTR
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#if BX_SUPPORT_X86_64
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void
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BX_CPU_C::XCHG_RRXRAX(bxInstruction_c *i)
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{
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Bit64u temp64 = RAX;
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RAX = BX_READ_64BIT_REG(i->opcodeReg());
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BX_WRITE_64BIT_REG(i->opcodeReg(), temp64);
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}
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void
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BX_CPU_C::MOV_RRXIq(bxInstruction_c *i)
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{
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BX_WRITE_64BIT_REG(i->opcodeReg(), i->Iq());
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}
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void
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BX_CPU_C::MOV_EqGq(bxInstruction_c *i)
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{
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/* op2_64 is a register, op2_addr is an index of a register */
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Bit64u op2_64 = BX_READ_64BIT_REG(i->nnn());
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/* op1_64 is a register or memory reference */
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/* now write op2 to op1 */
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if (i->modC0()) {
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BX_WRITE_64BIT_REG(i->rm(), op2_64);
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}
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else {
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write_virtual_qword(i->seg(), RMAddr(i), &op2_64);
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}
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}
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void
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BX_CPU_C::MOV_GqEq(bxInstruction_c *i)
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{
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Bit64u op2_64;
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if (i->modC0()) {
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op2_64 = BX_READ_64BIT_REG(i->rm());
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}
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else {
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/* pointer, segment address pair */
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read_virtual_qword(i->seg(), RMAddr(i), &op2_64);
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}
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BX_WRITE_64BIT_REG(i->nnn(), op2_64);
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}
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void
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BX_CPU_C::LEA_GqM(bxInstruction_c *i)
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{
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if (i->modC0()) {
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BX_INFO(("LEA_GqM: op2 is a register"));
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UndefinedOpcode(i);
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}
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/* write effective address of op2 in op1 */
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BX_WRITE_64BIT_REG(i->nnn(), RMAddr(i));
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}
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void
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BX_CPU_C::MOV_ALOq(bxInstruction_c *i)
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{
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Bit8u temp_8;
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bx_address addr = i->Iq();
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/* read from memory address */
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if (!BX_NULL_SEG_REG(i->seg())) {
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read_virtual_byte(i->seg(), addr, &temp_8);
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}
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else {
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read_virtual_byte(BX_SEG_REG_DS, addr, &temp_8);
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}
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/* write to register */
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RAX = temp_8;
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}
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void
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BX_CPU_C::MOV_OqAL(bxInstruction_c *i)
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{
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bx_address addr = i->Iq();
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/* read from register */
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Bit8u temp_8 = AL;
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/* write to memory address */
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if (!BX_NULL_SEG_REG(i->seg())) {
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write_virtual_byte(i->seg(), addr, &temp_8);
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}
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else {
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write_virtual_byte(BX_SEG_REG_DS, addr, &temp_8);
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}
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}
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void
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BX_CPU_C::MOV_AXOq(bxInstruction_c *i)
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{
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Bit16u temp_16;
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bx_address addr = i->Iq();
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/* read from memory address */
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if (!BX_NULL_SEG_REG(i->seg())) {
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read_virtual_word(i->seg(), addr, &temp_16);
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}
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else {
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read_virtual_word(BX_SEG_REG_DS, addr, &temp_16);
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}
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/* write to register */
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AX = temp_16;
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}
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void
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BX_CPU_C::MOV_OqAX(bxInstruction_c *i)
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{
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bx_address addr = i->Iq();
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/* read from register */
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Bit16u temp_16 = AX;
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/* write to memory address */
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if (!BX_NULL_SEG_REG(i->seg())) {
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write_virtual_word(i->seg(), addr, &temp_16);
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}
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else {
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write_virtual_word(BX_SEG_REG_DS, addr, &temp_16);
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}
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}
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void
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BX_CPU_C::MOV_EAXOq(bxInstruction_c *i)
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{
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Bit32u temp_32;
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bx_address addr = i->Iq();
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/* read from memory address */
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if (!BX_NULL_SEG_REG(i->seg())) {
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read_virtual_dword(i->seg(), addr, &temp_32);
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}
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else {
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read_virtual_dword(BX_SEG_REG_DS, addr, &temp_32);
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}
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/* write to register */
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RAX = temp_32;
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}
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void
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BX_CPU_C::MOV_OqEAX(bxInstruction_c *i)
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{
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bx_address addr = i->Iq();
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/* read from register */
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Bit32u temp_32 = EAX;
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/* write to memory address */
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if (!BX_NULL_SEG_REG(i->seg())) {
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write_virtual_dword(i->seg(), addr, &temp_32);
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}
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else {
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write_virtual_dword(BX_SEG_REG_DS, addr, &temp_32);
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}
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}
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void
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BX_CPU_C::MOV_RAXOq(bxInstruction_c *i)
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{
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Bit64u temp_64;
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bx_address addr = i->Iq();
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/* read from memory address */
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if (!BX_NULL_SEG_REG(i->seg())) {
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read_virtual_qword(i->seg(), addr, &temp_64);
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}
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else {
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read_virtual_qword(BX_SEG_REG_DS, addr, &temp_64);
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}
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/* write to register */
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RAX = temp_64;
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}
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void
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BX_CPU_C::MOV_OqRAX(bxInstruction_c *i)
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{
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bx_address addr = i->Iq();
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/* read from register */
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Bit64u temp_64 = RAX;
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/* write to memory address */
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if (!BX_NULL_SEG_REG(i->seg())) {
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write_virtual_qword(i->seg(), addr, &temp_64);
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}
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else {
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write_virtual_qword(BX_SEG_REG_DS, addr, &temp_64);
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}
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}
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void
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BX_CPU_C::MOV_EqId(bxInstruction_c *i)
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{
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Bit64u op2_64 = (Bit32s) i->Id();
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/* now write sum back to destination */
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if (i->modC0()) {
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BX_WRITE_64BIT_REG(i->rm(), op2_64);
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}
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else {
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write_virtual_qword(i->seg(), RMAddr(i), &op2_64);
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}
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}
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void
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BX_CPU_C::MOVZX_GqEb(bxInstruction_c *i)
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{
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Bit8u op2_8;
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if (i->modC0()) {
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op2_8 = BX_READ_8BIT_REGx(i->rm(),i->extend8bitL());
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}
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else {
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/* pointer, segment address pair */
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read_virtual_byte(i->seg(), RMAddr(i), &op2_8);
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}
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/* zero extend byte op2 into qword op1 */
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BX_WRITE_64BIT_REG(i->nnn(), (Bit64u) op2_8);
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}
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void
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BX_CPU_C::MOVZX_GqEw(bxInstruction_c *i)
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{
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Bit16u op2_16;
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if (i->modC0()) {
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op2_16 = BX_READ_16BIT_REG(i->rm());
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}
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else {
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/* pointer, segment address pair */
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read_virtual_word(i->seg(), RMAddr(i), &op2_16);
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}
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/* zero extend word op2 into qword op1 */
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BX_WRITE_64BIT_REG(i->nnn(), (Bit64u) op2_16);
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}
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void
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BX_CPU_C::MOVSX_GqEb(bxInstruction_c *i)
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{
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Bit8u op2_8;
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if (i->modC0()) {
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op2_8 = BX_READ_8BIT_REGx(i->rm(),i->extend8bitL());
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}
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else {
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/* pointer, segment address pair */
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read_virtual_byte(i->seg(), RMAddr(i), &op2_8);
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}
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/* sign extend byte op2 into qword op1 */
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BX_WRITE_64BIT_REG(i->nnn(), (Bit8s) op2_8);
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}
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void
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BX_CPU_C::MOVSX_GqEw(bxInstruction_c *i)
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{
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Bit16u op2_16;
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if (i->modC0()) {
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op2_16 = BX_READ_16BIT_REG(i->rm());
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}
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else {
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/* pointer, segment address pair */
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read_virtual_word(i->seg(), RMAddr(i), &op2_16);
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}
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/* sign extend word op2 into qword op1 */
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BX_WRITE_64BIT_REG(i->nnn(), (Bit16s) op2_16);
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}
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void
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BX_CPU_C::MOVSX_GqEd(bxInstruction_c *i)
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{
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Bit32u op2_32;
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if (i->modC0()) {
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op2_32 = BX_READ_32BIT_REG(i->rm());
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}
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else {
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/* pointer, segment address pair */
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read_virtual_dword(i->seg(), RMAddr(i), &op2_32);
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}
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/* sign extend word op2 into qword op1 */
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BX_WRITE_64BIT_REG(i->nnn(), (Bit32s) op2_32);
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}
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void
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BX_CPU_C::XCHG_EqGq(bxInstruction_c *i)
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{
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Bit64u op2_64, op1_64;
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/* op2_64 is a register, op2_addr is an index of a register */
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op2_64 = BX_READ_64BIT_REG(i->nnn());
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/* op1_64 is a register or memory reference */
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if (i->modC0()) {
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op1_64 = BX_READ_64BIT_REG(i->rm());
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BX_WRITE_64BIT_REG(i->rm(), op2_64);
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}
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else {
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/* pointer, segment address pair */
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read_RMW_virtual_qword(i->seg(), RMAddr(i), &op1_64);
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Write_RMW_virtual_qword(op2_64);
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}
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BX_WRITE_64BIT_REG(i->nnn(), op1_64);
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}
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void
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BX_CPU_C::CMOV_GqEq(bxInstruction_c *i)
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{
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// Note: CMOV accesses a memory source operand (read), regardless
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// of whether condition is true or not. Thus, exceptions may
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// occur even if the MOV does not take place.
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bx_bool condition = 0;
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Bit64u op2_64;
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switch (i->b1()) {
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// CMOV opcodes:
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case 0x140: condition = get_OF(); break;
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case 0x141: condition = !get_OF(); break;
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case 0x142: condition = get_CF(); break;
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case 0x143: condition = !get_CF(); break;
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case 0x144: condition = get_ZF(); break;
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case 0x145: condition = !get_ZF(); break;
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case 0x146: condition = get_CF() || get_ZF(); break;
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case 0x147: condition = !get_CF() && !get_ZF(); break;
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case 0x148: condition = get_SF(); break;
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case 0x149: condition = !get_SF(); break;
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case 0x14A: condition = get_PF(); break;
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case 0x14B: condition = !get_PF(); break;
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case 0x14C: condition = getB_SF() != getB_OF(); break;
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case 0x14D: condition = getB_SF() == getB_OF(); break;
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case 0x14E: condition = get_ZF() || (getB_SF() != getB_OF()); break;
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case 0x14F: condition = !get_ZF() && (getB_SF() == getB_OF()); break;
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default:
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BX_PANIC(("CMOV_GqEq: default case"));
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}
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if (i->modC0()) {
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op2_64 = BX_READ_64BIT_REG(i->rm());
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}
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else {
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/* pointer, segment address pair */
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read_virtual_qword(i->seg(), RMAddr(i), &op2_64);
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}
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if (condition)
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BX_WRITE_64BIT_REG(i->nnn(), op2_64);
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}
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#endif /* if BX_SUPPORT_X86_64 */
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