1b9f286945
SMP emulation. New implementation uses dynamic CPU quantum value and takes full advantage of the trace cache. Each emulated processor will execute the whole trace before switching to the next processor. * It is also safe to use large (up to 16 instructions) quantum values for the SMP emulation now and improve performance even further. The same merge also completely fixes SF bug : [3312237] stepN command might be not working properly Handlers chaining speedups are also supported with SMP emulation now.
1062 lines
32 KiB
C++
1062 lines
32 KiB
C++
/////////////////////////////////////////////////////////////////////////
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// $Id$
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/////////////////////////////////////////////////////////////////////////
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//
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// Copyright (C) 2001-2011 The Bochs Project
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//
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// This library is free software; you can redistribute it and/or
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// modify it under the terms of the GNU Lesser General Public
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// License as published by the Free Software Foundation; either
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// version 2 of the License, or (at your option) any later version.
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//
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// This library is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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// Lesser General Public License for more details.
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//
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// You should have received a copy of the GNU Lesser General Public
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// License along with this library; if not, write to the Free Software
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// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA B 02110-1301 USA
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/////////////////////////////////////////////////////////////////////////
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#define NEED_CPU_REG_SHORTCUTS 1
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#include "bochs.h"
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#include "cpu.h"
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#define LOG_THIS BX_CPU_THIS_PTR
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#include "iodev/iodev.h"
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#define InstrumentICACHE 0
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#if InstrumentICACHE
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static unsigned iCacheLookups=0;
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static unsigned iCacheMisses=0;
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#define InstrICache_StatsMask 0xffffff
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#define InstrICache_Stats() {\
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if ((iCacheLookups & InstrICache_StatsMask) == 0) { \
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BX_INFO(("ICACHE lookups: %u, misses: %u, hit rate = %6.2f%% ", \
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iCacheLookups, \
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iCacheMisses, \
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(iCacheLookups-iCacheMisses) * 100.0 / iCacheLookups)); \
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iCacheLookups = iCacheMisses = 0; \
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} \
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}
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#define InstrICache_Increment(v) (v)++
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#else
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#define InstrICache_Stats()
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#define InstrICache_Increment(v)
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#endif
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void BX_CPU_C::cpu_loop(void)
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{
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#if BX_DEBUGGER
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BX_CPU_THIS_PTR break_point = 0;
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BX_CPU_THIS_PTR magic_break = 0;
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BX_CPU_THIS_PTR stop_reason = STOP_NO_REASON;
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#endif
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if (setjmp(BX_CPU_THIS_PTR jmp_buf_env)) {
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// can get here only from exception function or VMEXIT
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#if BX_SUPPORT_HANDLERS_CHAINING_SPEEDUPS
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BX_CPU_THIS_PTR icount++;
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#endif
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BX_SYNC_TIME_IF_SINGLE_PROCESSOR(0);
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#if BX_DEBUGGER || BX_GDBSTUB
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if (dbg_instruction_epilog()) return;
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#endif
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#if BX_GDBSTUB
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if (bx_dbg.gdbstub_enabled) return;
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#endif
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}
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// If the exception() routine has encountered a nasty fault scenario,
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// the debugger may request that control is returned to it so that
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// the situation may be examined.
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#if BX_DEBUGGER
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if (bx_guard.interrupt_requested) return;
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#endif
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// We get here either by a normal function call, or by a longjmp
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// back from an exception() call. In either case, commit the
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// new EIP/ESP, and set up other environmental fields. This code
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// mirrors similar code below, after the interrupt() call.
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BX_CPU_THIS_PTR prev_rip = RIP; // commit new EIP
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BX_CPU_THIS_PTR speculative_rsp = 0;
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BX_CPU_THIS_PTR EXT = 0;
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while (1) {
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// check on events which occurred for previous instructions (traps)
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// and ones which are asynchronous to the CPU (hardware interrupts)
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if (BX_CPU_THIS_PTR async_event) {
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if (handleAsyncEvent()) {
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// If request to return to caller ASAP.
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return;
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}
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}
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bxICacheEntry_c *entry = getICacheEntry();
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bxInstruction_c *i = entry->i;
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#if BX_SUPPORT_HANDLERS_CHAINING_SPEEDUPS
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for(;;) {
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// want to allow changing of the instruction inside instrumentation callback
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BX_INSTR_BEFORE_EXECUTION(BX_CPU_ID, i);
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RIP += i->ilen();
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// when handlers chaining is enabled this single call will execute entire trace
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BX_CPU_CALL_METHOD(i->execute, (i)); // might iterate repeat instruction
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BX_SYNC_TIME_IF_SINGLE_PROCESSOR(0);
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if (BX_CPU_THIS_PTR async_event) break;
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i = getICacheEntry()->i;
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}
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#else // BX_SUPPORT_HANDLERS_CHAINING_SPEEDUPS == 0
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bxInstruction_c *last = i + (entry->tlen);
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for(;;) {
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#if BX_DEBUGGER
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if (BX_CPU_THIS_PTR trace)
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debug_disasm_instruction(BX_CPU_THIS_PTR prev_rip);
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#endif
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// want to allow changing of the instruction inside instrumentation callback
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BX_INSTR_BEFORE_EXECUTION(BX_CPU_ID, i);
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RIP += i->ilen();
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BX_CPU_CALL_METHOD(i->execute, (i)); // might iterate repeat instruction
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BX_CPU_THIS_PTR prev_rip = RIP; // commit new RIP
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BX_INSTR_AFTER_EXECUTION(BX_CPU_ID, i);
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BX_SYNC_TIME_IF_SINGLE_PROCESSOR(0);
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// note instructions generating exceptions never reach this point
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#if BX_DEBUGGER || BX_GDBSTUB
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if (dbg_instruction_epilog()) return;
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#endif
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if (BX_CPU_THIS_PTR async_event) break;
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if (++i == last) {
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entry = getICacheEntry();
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i = entry->i;
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last = i + (entry->tlen);
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}
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}
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#endif
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// clear stop trace magic indication that probably was set by repeat or branch32/64
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BX_CPU_THIS_PTR async_event &= ~BX_ASYNC_EVENT_STOP_TRACE;
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} // while (1)
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}
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#if BX_SUPPORT_SMP
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void BX_CPU_C::cpu_run_trace(void)
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{
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if (setjmp(BX_CPU_THIS_PTR jmp_buf_env)) {
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// can get here only from exception function or VMEXIT
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BX_CPU_THIS_PTR icount++;
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return;
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}
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// check on events which occurred for previous instructions (traps)
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// and ones which are asynchronous to the CPU (hardware interrupts)
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if (BX_CPU_THIS_PTR async_event) {
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if (handleAsyncEvent()) {
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// If request to return to caller ASAP.
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return;
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}
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}
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bxICacheEntry_c *entry = getICacheEntry();
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bxInstruction_c *i = entry->i;
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#if BX_SUPPORT_HANDLERS_CHAINING_SPEEDUPS
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// want to allow changing of the instruction inside instrumentation callback
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BX_INSTR_BEFORE_EXECUTION(BX_CPU_ID, i);
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RIP += i->ilen();
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// when handlers chaining is enabled this single call will execute entire trace
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BX_CPU_CALL_METHOD(i->execute, (i)); // might iterate repeat instruction
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if (BX_CPU_THIS_PTR async_event) {
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// clear stop trace magic indication that probably was set by repeat or branch32/64
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BX_CPU_THIS_PTR async_event &= ~BX_ASYNC_EVENT_STOP_TRACE;
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}
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#else
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bxInstruction_c *last = i + (entry->tlen);
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for(;;) {
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// want to allow changing of the instruction inside instrumentation callback
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BX_INSTR_BEFORE_EXECUTION(BX_CPU_ID, i);
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RIP += i->ilen();
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BX_CPU_CALL_METHOD(i->execute, (i)); // might iterate repeat instruction
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BX_CPU_THIS_PTR prev_rip = RIP; // commit new RIP
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BX_INSTR_AFTER_EXECUTION(BX_CPU_ID, i);
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BX_CPU_THIS_PTR icount++;
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if (BX_CPU_THIS_PTR async_event) {
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// clear stop trace magic indication that probably was set by repeat or branch32/64
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BX_CPU_THIS_PTR async_event &= ~BX_ASYNC_EVENT_STOP_TRACE;
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break;
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}
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if (++i == last) break;
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}
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#endif // BX_SUPPORT_HANDLERS_CHAINING_SPEEDUPS
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}
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#endif
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bxICacheEntry_c* BX_CPU_C::getICacheEntry(void)
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{
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bx_address eipBiased = RIP + BX_CPU_THIS_PTR eipPageBias;
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if (eipBiased >= BX_CPU_THIS_PTR eipPageWindowSize) {
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prefetch();
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eipBiased = RIP + BX_CPU_THIS_PTR eipPageBias;
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}
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bx_phy_address pAddr = BX_CPU_THIS_PTR pAddrPage + eipBiased;
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bxICacheEntry_c *entry = BX_CPU_THIS_PTR iCache.get_entry(pAddr, BX_CPU_THIS_PTR fetchModeMask);
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InstrICache_Increment(iCacheLookups);
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InstrICache_Stats();
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if (entry->pAddr != pAddr)
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{
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// iCache miss. No validated instruction with matching fetch parameters
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// is in the iCache.
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InstrICache_Increment(iCacheMisses);
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entry = serveICacheMiss(entry, (Bit32u) eipBiased, pAddr);
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}
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return entry;
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}
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#define BX_REPEAT_TIME_UPDATE_INTERVAL 15
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void BX_CPP_AttrRegparmN(2) BX_CPU_C::repeat(bxInstruction_c *i, BxRepIterationPtr_tR execute)
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{
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// non repeated instruction
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if (! i->repUsedL()) {
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BX_CPU_CALL_REP_ITERATION(execute, (i));
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return;
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}
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#if BX_X86_DEBUGGER
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BX_CPU_THIS_PTR in_repeat = 0;
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#endif
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#if BX_SUPPORT_X86_64
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if (i->as64L()) {
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while(1) {
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if (RCX != 0) {
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BX_CPU_CALL_REP_ITERATION(execute, (i));
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BX_INSTR_REPEAT_ITERATION(BX_CPU_ID, i);
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RCX --;
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}
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if (RCX == 0) return;
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#if BX_DEBUGGER == 0
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if (BX_CPU_THIS_PTR async_event)
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#endif
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break; // exit always if debugger enabled
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#if BX_SUPPORT_HANDLERS_CHAINING_SPEEDUPS || BX_SUPPORT_SMP
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BX_CPU_THIS_PTR icount++;
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#endif
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BX_SYNC_TIME_IF_SINGLE_PROCESSOR(BX_REPEAT_TIME_UPDATE_INTERVAL);
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}
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}
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else
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#endif
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if (i->as32L()) {
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while(1) {
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if (ECX != 0) {
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BX_CPU_CALL_REP_ITERATION(execute, (i));
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BX_INSTR_REPEAT_ITERATION(BX_CPU_ID, i);
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RCX = ECX - 1;
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}
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if (ECX == 0) return;
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#if BX_DEBUGGER == 0
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if (BX_CPU_THIS_PTR async_event)
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#endif
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break; // exit always if debugger enabled
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#if BX_SUPPORT_HANDLERS_CHAINING_SPEEDUPS || BX_SUPPORT_SMP
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BX_CPU_THIS_PTR icount++;
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#endif
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BX_SYNC_TIME_IF_SINGLE_PROCESSOR(BX_REPEAT_TIME_UPDATE_INTERVAL);
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}
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}
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else // 16bit addrsize
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{
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while(1) {
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if (CX != 0) {
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BX_CPU_CALL_REP_ITERATION(execute, (i));
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BX_INSTR_REPEAT_ITERATION(BX_CPU_ID, i);
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CX --;
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}
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if (CX == 0) return;
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#if BX_DEBUGGER == 0
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if (BX_CPU_THIS_PTR async_event)
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#endif
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break; // exit always if debugger enabled
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#if BX_SUPPORT_HANDLERS_CHAINING_SPEEDUPS || BX_SUPPORT_SMP
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BX_CPU_THIS_PTR icount++;
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#endif
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BX_SYNC_TIME_IF_SINGLE_PROCESSOR(BX_REPEAT_TIME_UPDATE_INTERVAL);
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}
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}
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#if BX_X86_DEBUGGER
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BX_CPU_THIS_PTR in_repeat = 1;
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#endif
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RIP = BX_CPU_THIS_PTR prev_rip; // repeat loop not done, restore RIP
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// assert magic async_event to stop trace execution
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BX_CPU_THIS_PTR async_event |= BX_ASYNC_EVENT_STOP_TRACE;
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}
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void BX_CPP_AttrRegparmN(2) BX_CPU_C::repeat_ZF(bxInstruction_c *i, BxRepIterationPtr_tR execute)
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{
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unsigned rep = i->repUsedValue();
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// non repeated instruction
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if (! rep) {
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BX_CPU_CALL_REP_ITERATION(execute, (i));
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return;
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}
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#if BX_X86_DEBUGGER
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BX_CPU_THIS_PTR in_repeat = 0;
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#endif
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if (rep == 3) { /* repeat prefix 0xF3 */
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#if BX_SUPPORT_X86_64
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if (i->as64L()) {
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while(1) {
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if (RCX != 0) {
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BX_CPU_CALL_REP_ITERATION(execute, (i));
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BX_INSTR_REPEAT_ITERATION(BX_CPU_ID, i);
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RCX --;
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}
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if (! get_ZF() || RCX == 0) return;
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#if BX_DEBUGGER == 0
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if (BX_CPU_THIS_PTR async_event)
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#endif
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break; // exit always if debugger enabled
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#if BX_SUPPORT_HANDLERS_CHAINING_SPEEDUPS || BX_SUPPORT_SMP
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BX_CPU_THIS_PTR icount++;
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#endif
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BX_SYNC_TIME_IF_SINGLE_PROCESSOR(BX_REPEAT_TIME_UPDATE_INTERVAL);
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}
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}
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else
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#endif
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if (i->as32L()) {
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while(1) {
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if (ECX != 0) {
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BX_CPU_CALL_REP_ITERATION(execute, (i));
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BX_INSTR_REPEAT_ITERATION(BX_CPU_ID, i);
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RCX = ECX - 1;
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}
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if (! get_ZF() || ECX == 0) return;
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#if BX_DEBUGGER == 0
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if (BX_CPU_THIS_PTR async_event)
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#endif
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break; // exit always if debugger enabled
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#if BX_SUPPORT_HANDLERS_CHAINING_SPEEDUPS || BX_SUPPORT_SMP
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BX_CPU_THIS_PTR icount++;
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#endif
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BX_SYNC_TIME_IF_SINGLE_PROCESSOR(BX_REPEAT_TIME_UPDATE_INTERVAL);
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}
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}
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else // 16bit addrsize
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{
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while(1) {
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if (CX != 0) {
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BX_CPU_CALL_REP_ITERATION(execute, (i));
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BX_INSTR_REPEAT_ITERATION(BX_CPU_ID, i);
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CX --;
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}
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if (! get_ZF() || CX == 0) return;
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#if BX_DEBUGGER == 0
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if (BX_CPU_THIS_PTR async_event)
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#endif
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break; // exit always if debugger enabled
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#if BX_SUPPORT_HANDLERS_CHAINING_SPEEDUPS || BX_SUPPORT_SMP
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BX_CPU_THIS_PTR icount++;
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#endif
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BX_SYNC_TIME_IF_SINGLE_PROCESSOR(BX_REPEAT_TIME_UPDATE_INTERVAL);
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}
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}
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}
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else { /* repeat prefix 0xF2 */
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#if BX_SUPPORT_X86_64
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if (i->as64L()) {
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while(1) {
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if (RCX != 0) {
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BX_CPU_CALL_REP_ITERATION(execute, (i));
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BX_INSTR_REPEAT_ITERATION(BX_CPU_ID, i);
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RCX --;
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}
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if (get_ZF() || RCX == 0) return;
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#if BX_DEBUGGER == 0
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if (BX_CPU_THIS_PTR async_event)
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#endif
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break; // exit always if debugger enabled
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#if BX_SUPPORT_HANDLERS_CHAINING_SPEEDUPS || BX_SUPPORT_SMP
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BX_CPU_THIS_PTR icount++;
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#endif
|
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BX_SYNC_TIME_IF_SINGLE_PROCESSOR(BX_REPEAT_TIME_UPDATE_INTERVAL);
|
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}
|
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}
|
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else
|
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#endif
|
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if (i->as32L()) {
|
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while(1) {
|
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if (ECX != 0) {
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BX_CPU_CALL_REP_ITERATION(execute, (i));
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BX_INSTR_REPEAT_ITERATION(BX_CPU_ID, i);
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RCX = ECX - 1;
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}
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if (get_ZF() || ECX == 0) return;
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|
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#if BX_DEBUGGER == 0
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if (BX_CPU_THIS_PTR async_event)
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#endif
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break; // exit always if debugger enabled
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#if BX_SUPPORT_HANDLERS_CHAINING_SPEEDUPS || BX_SUPPORT_SMP
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BX_CPU_THIS_PTR icount++;
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#endif
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BX_SYNC_TIME_IF_SINGLE_PROCESSOR(BX_REPEAT_TIME_UPDATE_INTERVAL);
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}
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}
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else // 16bit addrsize
|
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{
|
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while(1) {
|
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if (CX != 0) {
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BX_CPU_CALL_REP_ITERATION(execute, (i));
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BX_INSTR_REPEAT_ITERATION(BX_CPU_ID, i);
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CX --;
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}
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if (get_ZF() || CX == 0) return;
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#if BX_DEBUGGER == 0
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if (BX_CPU_THIS_PTR async_event)
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#endif
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break; // exit always if debugger enabled
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#if BX_SUPPORT_HANDLERS_CHAINING_SPEEDUPS || BX_SUPPORT_SMP
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BX_CPU_THIS_PTR icount++;
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#endif
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BX_SYNC_TIME_IF_SINGLE_PROCESSOR(BX_REPEAT_TIME_UPDATE_INTERVAL);
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}
|
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}
|
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}
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#if BX_X86_DEBUGGER
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BX_CPU_THIS_PTR in_repeat = 1;
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#endif
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RIP = BX_CPU_THIS_PTR prev_rip; // repeat loop not done, restore RIP
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// assert magic async_event to stop trace execution
|
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BX_CPU_THIS_PTR async_event |= BX_ASYNC_EVENT_STOP_TRACE;
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}
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|
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unsigned BX_CPU_C::handleAsyncEvent(void)
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{
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//
|
|
// This area is where we process special conditions and events.
|
|
//
|
|
if (BX_CPU_THIS_PTR activity_state) {
|
|
// For one processor, pass the time as quickly as possible until
|
|
// an interrupt wakes up the CPU.
|
|
while (1)
|
|
{
|
|
if ((BX_CPU_INTR && (BX_CPU_THIS_PTR get_IF() || BX_CPU_THIS_PTR activity_state == BX_ACTIVITY_STATE_MWAIT_IF)) ||
|
|
#if BX_SUPPORT_VMX >= 2
|
|
BX_CPU_THIS_PTR pending_vmx_timer_expired ||
|
|
#endif
|
|
BX_CPU_THIS_PTR pending_NMI || BX_CPU_THIS_PTR pending_SMI || BX_CPU_THIS_PTR pending_INIT)
|
|
{
|
|
// interrupt ends the HALT condition
|
|
#if BX_SUPPORT_MONITOR_MWAIT
|
|
if (BX_CPU_THIS_PTR activity_state >= BX_ACTIVITY_STATE_MWAIT)
|
|
BX_CPU_THIS_PTR monitor.reset_monitor();
|
|
#endif
|
|
BX_CPU_THIS_PTR activity_state = 0;
|
|
BX_CPU_THIS_PTR inhibit_mask = 0; // clear inhibits for after resume
|
|
break;
|
|
}
|
|
|
|
if (BX_CPU_THIS_PTR activity_state == BX_ACTIVITY_STATE_ACTIVE) {
|
|
BX_INFO(("handleAsyncEvent: reset detected in HLT state"));
|
|
break;
|
|
}
|
|
|
|
if (BX_HRQ && BX_DBG_ASYNC_DMA) {
|
|
// handle DMA also when CPU is halted
|
|
DEV_dma_raise_hlda();
|
|
}
|
|
|
|
// for multiprocessor simulation, even if this CPU is halted we still
|
|
// must give the others a chance to simulate. If an interrupt has
|
|
// arrived, then clear the HALT condition; otherwise just return from
|
|
// the CPU loop with stop_reason STOP_CPU_HALTED.
|
|
#if BX_SUPPORT_SMP
|
|
if (BX_SMP_PROCESSORS > 1) {
|
|
// HALT condition remains, return so other CPUs have a chance
|
|
#if BX_DEBUGGER
|
|
BX_CPU_THIS_PTR stop_reason = STOP_CPU_HALTED;
|
|
#endif
|
|
return 1; // Return to caller of cpu_loop.
|
|
}
|
|
#endif
|
|
|
|
#if BX_DEBUGGER
|
|
if (bx_guard.interrupt_requested)
|
|
return 1; // Return to caller of cpu_loop.
|
|
#endif
|
|
|
|
BX_TICKN(10); // when in HLT run time faster for single CPU
|
|
}
|
|
} else if (bx_pc_system.kill_bochs_request) {
|
|
// setting kill_bochs_request causes the cpu loop to return ASAP.
|
|
return 1; // Return to caller of cpu_loop.
|
|
}
|
|
|
|
// VMLAUNCH/VMRESUME cannot be executed with interrupts inhibited.
|
|
// Save inhibit interrupts state into shadow bits after clearing
|
|
BX_CPU_THIS_PTR inhibit_mask = (BX_CPU_THIS_PTR inhibit_mask << 2) & 0xF;
|
|
|
|
// Priority 1: Hardware Reset and Machine Checks
|
|
// RESET
|
|
// Machine Check
|
|
// (bochs doesn't support these)
|
|
|
|
// Priority 2: Trap on Task Switch
|
|
// T flag in TSS is set
|
|
if (BX_CPU_THIS_PTR debug_trap & BX_DEBUG_TRAP_TASK_SWITCH_BIT)
|
|
exception(BX_DB_EXCEPTION, 0); // no error, not interrupt
|
|
|
|
// Priority 3: External Hardware Interventions
|
|
// FLUSH
|
|
// STOPCLK
|
|
// SMI
|
|
// INIT
|
|
if (BX_CPU_THIS_PTR pending_SMI && ! BX_CPU_THIS_PTR smm_mode())
|
|
{
|
|
// clear SMI pending flag and disable NMI when SMM was accepted
|
|
BX_CPU_THIS_PTR pending_SMI = 0;
|
|
enter_system_management_mode();
|
|
}
|
|
|
|
if (BX_CPU_THIS_PTR pending_INIT && ! BX_CPU_THIS_PTR disable_INIT) {
|
|
#if BX_SUPPORT_VMX
|
|
if (BX_CPU_THIS_PTR in_vmx_guest) {
|
|
BX_ERROR(("VMEXIT: INIT pin asserted"));
|
|
VMexit(0, VMX_VMEXIT_INIT, 0);
|
|
}
|
|
#endif
|
|
// reset will clear pending INIT
|
|
reset(BX_RESET_SOFTWARE);
|
|
|
|
#if BX_SUPPORT_SMP
|
|
if (BX_SMP_PROCESSORS > 1) {
|
|
// if HALT condition remains, return so other CPUs have a chance
|
|
if (BX_CPU_THIS_PTR activity_state) {
|
|
#if BX_DEBUGGER
|
|
BX_CPU_THIS_PTR stop_reason = STOP_CPU_HALTED;
|
|
#endif
|
|
return 1; // Return to caller of cpu_loop.
|
|
}
|
|
}
|
|
#endif
|
|
}
|
|
|
|
// Priority 4: Traps on Previous Instruction
|
|
// Breakpoints
|
|
// Debug Trap Exceptions (TF flag set or data/IO breakpoint)
|
|
if (! (BX_CPU_THIS_PTR inhibit_mask & BX_INHIBIT_DEBUG_SHADOW)) {
|
|
// A trap may be inhibited on this boundary due to an instruction
|
|
// which loaded SS. If so we clear the inhibit_mask below
|
|
// and don't execute this code until the next boundary.
|
|
#if BX_X86_DEBUGGER
|
|
code_breakpoint_match(get_laddr(BX_SEG_REG_CS, BX_CPU_THIS_PTR prev_rip));
|
|
#endif
|
|
if (BX_CPU_THIS_PTR debug_trap)
|
|
exception(BX_DB_EXCEPTION, 0); // no error, not interrupt
|
|
}
|
|
|
|
// Priority 4.5: VMX Preemption Timer Expired. FIXME: is it a kind of external interrupt?
|
|
#if BX_SUPPORT_VMX >= 2
|
|
if (BX_CPU_THIS_PTR in_vmx_guest) {
|
|
if (BX_CPU_THIS_PTR pending_vmx_timer_expired) {
|
|
BX_CPU_THIS_PTR pending_vmx_timer_expired = 0;
|
|
VMexit_PreemptionTimerExpired();
|
|
}
|
|
}
|
|
#endif
|
|
|
|
// Priority 5: External Interrupts
|
|
// NMI Interrupts
|
|
// Maskable Hardware Interrupts
|
|
if (BX_CPU_THIS_PTR inhibit_mask & BX_INHIBIT_INTERRUPTS_SHADOW) {
|
|
// Processing external interrupts is inhibited on this
|
|
// boundary because of certain instructions like STI.
|
|
// inhibit_mask is cleared below, in which case we will have
|
|
// an opportunity to check interrupts on the next instruction
|
|
// boundary.
|
|
}
|
|
#if BX_SUPPORT_VMX
|
|
else if (! BX_CPU_THIS_PTR disable_NMI && BX_CPU_THIS_PTR in_vmx_guest &&
|
|
VMEXIT(VMX_VM_EXEC_CTRL2_NMI_WINDOW_VMEXIT))
|
|
{
|
|
// NMI-window exiting
|
|
BX_ERROR(("VMEXIT: NMI window exiting"));
|
|
VMexit(0, VMX_VMEXIT_NMI_WINDOW, 0);
|
|
}
|
|
#endif
|
|
else if (BX_CPU_THIS_PTR pending_NMI && ! BX_CPU_THIS_PTR disable_NMI) {
|
|
BX_CPU_THIS_PTR pending_NMI = 0;
|
|
BX_CPU_THIS_PTR disable_NMI = 1;
|
|
BX_CPU_THIS_PTR EXT = 1; /* external event */
|
|
#if BX_SUPPORT_VMX
|
|
VMexit_Event(0, BX_NMI, 2, 0, 0);
|
|
#endif
|
|
BX_INSTR_HWINTERRUPT(BX_CPU_ID, 2, BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].selector.value, RIP);
|
|
interrupt(2, BX_NMI, 0, 0);
|
|
}
|
|
#if BX_SUPPORT_VMX
|
|
else if (BX_CPU_THIS_PTR vmx_interrupt_window && BX_CPU_THIS_PTR get_IF()) {
|
|
// interrupt-window exiting
|
|
BX_ERROR(("VMEXIT: interrupt window exiting"));
|
|
VMexit(0, VMX_VMEXIT_INTERRUPT_WINDOW, 0);
|
|
}
|
|
#endif
|
|
else if (BX_CPU_INTR && BX_DBG_ASYNC_INTR &&
|
|
(BX_CPU_THIS_PTR get_IF()
|
|
#if BX_SUPPORT_VMX
|
|
|| (BX_CPU_THIS_PTR in_vmx_guest && PIN_VMEXIT(VMX_VM_EXEC_CTRL1_EXTERNAL_INTERRUPT_VMEXIT))
|
|
#endif
|
|
))
|
|
{
|
|
Bit8u vector;
|
|
#if BX_SUPPORT_VMX
|
|
VMexit_ExtInterrupt();
|
|
#endif
|
|
// NOTE: similar code in ::take_irq()
|
|
#if BX_SUPPORT_APIC
|
|
if (BX_CPU_THIS_PTR lapic.INTR)
|
|
vector = BX_CPU_THIS_PTR lapic.acknowledge_int();
|
|
else
|
|
#endif
|
|
// if no local APIC, always acknowledge the PIC.
|
|
vector = DEV_pic_iac(); // may set INTR with next interrupt
|
|
BX_CPU_THIS_PTR EXT = 1; /* external event */
|
|
#if BX_SUPPORT_VMX
|
|
VMexit_Event(0, BX_EXTERNAL_INTERRUPT, vector, 0, 0);
|
|
#endif
|
|
BX_INSTR_HWINTERRUPT(BX_CPU_ID, vector,
|
|
BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].selector.value, RIP);
|
|
interrupt(vector, BX_EXTERNAL_INTERRUPT, 0, 0);
|
|
// Set up environment, as would be when this main cpu loop gets
|
|
// invoked. At the end of normal instructions, we always commmit
|
|
// the new EIP. But here, we call interrupt() much like
|
|
// it was a sofware interrupt instruction, and need to effect the
|
|
// commit here. This code mirrors similar code above.
|
|
BX_CPU_THIS_PTR prev_rip = RIP; // commit new RIP
|
|
BX_CPU_THIS_PTR EXT = 0;
|
|
}
|
|
else if (BX_HRQ && BX_DBG_ASYNC_DMA) {
|
|
// NOTE: similar code in ::take_dma()
|
|
// assert Hold Acknowledge (HLDA) and go into a bus hold state
|
|
DEV_dma_raise_hlda();
|
|
}
|
|
|
|
if (BX_CPU_THIS_PTR get_TF())
|
|
{
|
|
// TF is set before execution of next instruction. Schedule
|
|
// a debug trap (#DB) after execution. After completion of
|
|
// next instruction, the code above will invoke the trap.
|
|
BX_CPU_THIS_PTR debug_trap |= BX_DEBUG_SINGLE_STEP_BIT;
|
|
}
|
|
|
|
// Priority 6: Faults from fetching next instruction
|
|
// Code breakpoint fault
|
|
// Code segment limit violation (priority 7 on 486/Pentium)
|
|
// Code page fault (priority 7 on 486/Pentium)
|
|
// (handled in main decode loop)
|
|
|
|
// Priority 7: Faults from decoding next instruction
|
|
// Instruction length > 15 bytes
|
|
// Illegal opcode
|
|
// Coprocessor not available
|
|
// (handled in main decode loop etc)
|
|
|
|
// Priority 8: Faults on executing an instruction
|
|
// Floating point execution
|
|
// Overflow
|
|
// Bound error
|
|
// Invalid TSS
|
|
// Segment not present
|
|
// Stack fault
|
|
// General protection
|
|
// Data page fault
|
|
// Alignment check
|
|
// (handled by rest of the code)
|
|
|
|
if (!((BX_CPU_INTR && BX_CPU_THIS_PTR get_IF()) ||
|
|
BX_CPU_THIS_PTR debug_trap ||
|
|
// BX_CPU_THIS_PTR get_TF() // implies debug_trap is set
|
|
BX_HRQ
|
|
#if BX_SUPPORT_VMX
|
|
|| BX_CPU_THIS_PTR vmx_interrupt_window || BX_CPU_THIS_PTR inhibit_mask
|
|
#endif
|
|
#if BX_SUPPORT_VMX >= 2
|
|
|| BX_CPU_THIS_PTR pending_vmx_timer_expired
|
|
#endif
|
|
#if BX_X86_DEBUGGER
|
|
// a debug code breakpoint is set in current page
|
|
|| BX_CPU_THIS_PTR codebp
|
|
#endif
|
|
))
|
|
BX_CPU_THIS_PTR async_event = 0;
|
|
|
|
return 0; // Continue executing cpu_loop.
|
|
}
|
|
|
|
|
|
// boundaries of consideration:
|
|
//
|
|
// * physical memory boundary: 1024k (1Megabyte) (increments of...)
|
|
// * A20 boundary: 1024k (1Megabyte)
|
|
// * page boundary: 4k
|
|
// * ROM boundary: 2k (dont care since we are only reading)
|
|
// * segment boundary: any
|
|
|
|
void BX_CPU_C::prefetch(void)
|
|
{
|
|
bx_address laddr;
|
|
unsigned pageOffset;
|
|
|
|
#if BX_SUPPORT_X86_64
|
|
if (long64_mode()) {
|
|
if (! IsCanonical(RIP)) {
|
|
BX_ERROR(("prefetch: #GP(0): RIP crossed canonical boundary"));
|
|
exception(BX_GP_EXCEPTION, 0);
|
|
}
|
|
|
|
// linear address is equal to RIP in 64-bit long mode
|
|
pageOffset = PAGE_OFFSET(EIP);
|
|
laddr = RIP;
|
|
|
|
// Calculate RIP at the beginning of the page.
|
|
BX_CPU_THIS_PTR eipPageBias = pageOffset - RIP;
|
|
BX_CPU_THIS_PTR eipPageWindowSize = 4096;
|
|
}
|
|
else
|
|
#endif
|
|
{
|
|
BX_CLEAR_64BIT_HIGH(BX_64BIT_REG_RIP); /* avoid 32-bit EIP wrap */
|
|
laddr = BX_CPU_THIS_PTR get_laddr32(BX_SEG_REG_CS, EIP);
|
|
pageOffset = PAGE_OFFSET(laddr);
|
|
|
|
// Calculate RIP at the beginning of the page.
|
|
BX_CPU_THIS_PTR eipPageBias = (bx_address) pageOffset - EIP;
|
|
|
|
Bit32u limit = BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.u.segment.limit_scaled;
|
|
if (EIP > limit) {
|
|
BX_ERROR(("prefetch: EIP [%08x] > CS.limit [%08x]", EIP, limit));
|
|
exception(BX_GP_EXCEPTION, 0);
|
|
}
|
|
|
|
BX_CPU_THIS_PTR eipPageWindowSize = 4096;
|
|
if (limit + BX_CPU_THIS_PTR eipPageBias < 4096) {
|
|
BX_CPU_THIS_PTR eipPageWindowSize = (Bit32u)(limit + BX_CPU_THIS_PTR eipPageBias + 1);
|
|
}
|
|
}
|
|
|
|
#if BX_X86_DEBUGGER
|
|
if (hwbreakpoint_check(laddr, BX_HWDebugInstruction, BX_HWDebugInstruction)) {
|
|
BX_CPU_THIS_PTR async_event = 1;
|
|
BX_CPU_THIS_PTR codebp = 1;
|
|
if (! (BX_CPU_THIS_PTR inhibit_mask & BX_INHIBIT_DEBUG_SHADOW)) {
|
|
// The next instruction could already hit a code breakpoint but
|
|
// async_event won't take effect immediatelly.
|
|
// Check if the next executing instruction hits code breakpoint
|
|
|
|
// check only if not fetching page cross instruction
|
|
// this check is 32-bit wrap safe as well
|
|
if (EIP == (Bit32u) BX_CPU_THIS_PTR prev_rip) {
|
|
if (code_breakpoint_match(laddr)) exception(BX_DB_EXCEPTION, 0);
|
|
}
|
|
}
|
|
}
|
|
else {
|
|
BX_CPU_THIS_PTR codebp = 0;
|
|
}
|
|
#endif
|
|
|
|
BX_CPU_THIS_PTR clear_RF();
|
|
|
|
bx_address lpf = LPFOf(laddr);
|
|
unsigned TLB_index = BX_TLB_INDEX_OF(lpf, 0);
|
|
bx_TLB_entry *tlbEntry = &BX_CPU_THIS_PTR TLB.entry[TLB_index];
|
|
Bit8u *fetchPtr = 0;
|
|
|
|
if ((tlbEntry->lpf == lpf) && !(tlbEntry->accessBits & (0x4 | USER_PL))) {
|
|
BX_CPU_THIS_PTR pAddrPage = tlbEntry->ppf;
|
|
fetchPtr = (Bit8u*) tlbEntry->hostPageAddr;
|
|
}
|
|
else {
|
|
bx_phy_address pAddr = translate_linear(laddr, USER_PL, BX_EXECUTE);
|
|
BX_CPU_THIS_PTR pAddrPage = PPFOf(pAddr);
|
|
}
|
|
|
|
if (fetchPtr) {
|
|
BX_CPU_THIS_PTR eipFetchPtr = fetchPtr;
|
|
}
|
|
else {
|
|
BX_CPU_THIS_PTR eipFetchPtr = (const Bit8u*) getHostMemAddr(BX_CPU_THIS_PTR pAddrPage, BX_EXECUTE);
|
|
|
|
// Sanity checks
|
|
if (! BX_CPU_THIS_PTR eipFetchPtr) {
|
|
bx_phy_address pAddr = BX_CPU_THIS_PTR pAddrPage + pageOffset;
|
|
if (pAddr >= BX_MEM(0)->get_memory_len()) {
|
|
BX_PANIC(("prefetch: running in bogus memory, pAddr=0x" FMT_PHY_ADDRX, pAddr));
|
|
}
|
|
else {
|
|
BX_PANIC(("prefetch: getHostMemAddr vetoed direct read, pAddr=0x" FMT_PHY_ADDRX, pAddr));
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
void BX_CPU_C::deliver_SIPI(unsigned vector)
|
|
{
|
|
if (BX_CPU_THIS_PTR activity_state == BX_ACTIVITY_STATE_WAIT_FOR_SIPI) {
|
|
BX_CPU_THIS_PTR activity_state = BX_ACTIVITY_STATE_ACTIVE;
|
|
RIP = 0;
|
|
load_seg_reg(&BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS], vector*0x100);
|
|
BX_CPU_THIS_PTR disable_INIT = 0; // enable INIT pin back
|
|
BX_INFO(("CPU %d started up at %04X:%08X by APIC",
|
|
BX_CPU_THIS_PTR bx_cpuid, vector*0x100, EIP));
|
|
} else {
|
|
BX_INFO(("CPU %d started up by APIC, but was not halted at the time", BX_CPU_THIS_PTR bx_cpuid));
|
|
}
|
|
}
|
|
|
|
void BX_CPU_C::deliver_INIT(void)
|
|
{
|
|
if (! BX_CPU_THIS_PTR disable_INIT) {
|
|
BX_CPU_THIS_PTR pending_INIT = 1;
|
|
BX_CPU_THIS_PTR async_event = 1;
|
|
}
|
|
}
|
|
|
|
void BX_CPU_C::deliver_NMI(void)
|
|
{
|
|
BX_CPU_THIS_PTR pending_NMI = 1;
|
|
BX_CPU_THIS_PTR async_event = 1;
|
|
}
|
|
|
|
void BX_CPU_C::deliver_SMI(void)
|
|
{
|
|
BX_CPU_THIS_PTR pending_SMI = 1;
|
|
BX_CPU_THIS_PTR async_event = 1;
|
|
}
|
|
|
|
void BX_CPU_C::set_INTR(bx_bool value)
|
|
{
|
|
BX_CPU_THIS_PTR INTR = value;
|
|
BX_CPU_THIS_PTR async_event = 1;
|
|
}
|
|
|
|
#if BX_DEBUGGER || BX_GDBSTUB
|
|
bx_bool BX_CPU_C::dbg_instruction_epilog(void)
|
|
{
|
|
#if BX_DEBUGGER
|
|
Bit64u tt = bx_pc_system.time_ticks();
|
|
bx_address debug_eip = RIP;
|
|
Bit16u cs = BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].selector.value;
|
|
|
|
BX_CPU_THIS_PTR icount++;
|
|
|
|
BX_CPU_THIS_PTR guard_found.cs = cs;
|
|
BX_CPU_THIS_PTR guard_found.eip = debug_eip;
|
|
BX_CPU_THIS_PTR guard_found.laddr = BX_CPU_THIS_PTR get_laddr(BX_SEG_REG_CS, debug_eip);
|
|
BX_CPU_THIS_PTR guard_found.code_32_64 = BX_CPU_THIS_PTR fetchModeMask;
|
|
|
|
//
|
|
// Take care of break point conditions generated during instruction execution
|
|
//
|
|
|
|
// Check if we hit read/write or time breakpoint
|
|
if (BX_CPU_THIS_PTR break_point) {
|
|
switch (BX_CPU_THIS_PTR break_point) {
|
|
case BREAK_POINT_TIME:
|
|
BX_INFO(("[" FMT_LL "d] Caught time breakpoint", tt));
|
|
BX_CPU_THIS_PTR stop_reason = STOP_TIME_BREAK_POINT;
|
|
return(1); // on a breakpoint
|
|
case BREAK_POINT_READ:
|
|
BX_INFO(("[" FMT_LL "d] Caught read watch point", tt));
|
|
BX_CPU_THIS_PTR stop_reason = STOP_READ_WATCH_POINT;
|
|
return(1); // on a breakpoint
|
|
case BREAK_POINT_WRITE:
|
|
BX_INFO(("[" FMT_LL "d] Caught write watch point", tt));
|
|
BX_CPU_THIS_PTR stop_reason = STOP_WRITE_WATCH_POINT;
|
|
return(1); // on a breakpoint
|
|
default:
|
|
BX_PANIC(("Weird break point condition"));
|
|
}
|
|
}
|
|
|
|
if (BX_CPU_THIS_PTR magic_break) {
|
|
BX_INFO(("[" FMT_LL "d] Stopped on MAGIC BREAKPOINT", bx_pc_system.time_ticks()));
|
|
BX_CPU_THIS_PTR stop_reason = STOP_MAGIC_BREAK_POINT;
|
|
return(1); // on a breakpoint
|
|
}
|
|
|
|
// see if debugger requesting icount guard
|
|
if (bx_guard.guard_for & BX_DBG_GUARD_ICOUNT) {
|
|
if (BX_CPU_THIS_PTR icount >= BX_CPU_THIS_PTR guard_found.icount_max) {
|
|
return(1);
|
|
}
|
|
}
|
|
|
|
// convenient point to see if user requested debug break or typed Ctrl-C
|
|
if (bx_guard.interrupt_requested) {
|
|
return(1);
|
|
}
|
|
|
|
// support for 'show' command in debugger
|
|
extern unsigned dbg_show_mask;
|
|
if(dbg_show_mask) {
|
|
int rv = bx_dbg_show_symbolic();
|
|
if (rv) return(rv);
|
|
}
|
|
|
|
// Just committed an instruction, before fetching a new one
|
|
// see if debugger is looking for iaddr breakpoint of any type
|
|
if (bx_guard.guard_for & BX_DBG_GUARD_IADDR_ALL) {
|
|
#if (BX_DBG_MAX_VIR_BPOINTS > 0)
|
|
if (bx_guard.guard_for & BX_DBG_GUARD_IADDR_VIR) {
|
|
for (unsigned n=0; n<bx_guard.iaddr.num_virtual; n++) {
|
|
if (bx_guard.iaddr.vir[n].enabled &&
|
|
(bx_guard.iaddr.vir[n].cs == cs) &&
|
|
(bx_guard.iaddr.vir[n].eip == debug_eip))
|
|
{
|
|
BX_CPU_THIS_PTR guard_found.guard_found = BX_DBG_GUARD_IADDR_VIR;
|
|
BX_CPU_THIS_PTR guard_found.iaddr_index = n;
|
|
return(1); // on a breakpoint
|
|
}
|
|
}
|
|
}
|
|
#endif
|
|
#if (BX_DBG_MAX_LIN_BPOINTS > 0)
|
|
if (bx_guard.guard_for & BX_DBG_GUARD_IADDR_LIN) {
|
|
for (unsigned n=0; n<bx_guard.iaddr.num_linear; n++) {
|
|
if (bx_guard.iaddr.lin[n].enabled &&
|
|
(bx_guard.iaddr.lin[n].addr == BX_CPU_THIS_PTR guard_found.laddr))
|
|
{
|
|
BX_CPU_THIS_PTR guard_found.guard_found = BX_DBG_GUARD_IADDR_LIN;
|
|
BX_CPU_THIS_PTR guard_found.iaddr_index = n;
|
|
return(1); // on a breakpoint
|
|
}
|
|
}
|
|
}
|
|
#endif
|
|
#if (BX_DBG_MAX_PHY_BPOINTS > 0)
|
|
if (bx_guard.guard_for & BX_DBG_GUARD_IADDR_PHY) {
|
|
bx_phy_address phy;
|
|
bx_bool valid = dbg_xlate_linear2phy(BX_CPU_THIS_PTR guard_found.laddr, &phy);
|
|
if (valid) {
|
|
for (unsigned n=0; n<bx_guard.iaddr.num_physical; n++) {
|
|
if (bx_guard.iaddr.phy[n].enabled && (bx_guard.iaddr.phy[n].addr == phy))
|
|
{
|
|
BX_CPU_THIS_PTR guard_found.guard_found = BX_DBG_GUARD_IADDR_PHY;
|
|
BX_CPU_THIS_PTR guard_found.iaddr_index = n;
|
|
return(1); // on a breakpoint
|
|
}
|
|
}
|
|
}
|
|
}
|
|
#endif
|
|
}
|
|
#endif
|
|
|
|
#if BX_GDBSTUB
|
|
if (bx_dbg.gdbstub_enabled) {
|
|
unsigned reason = bx_gdbstub_check(EIP);
|
|
if (reason != GDBSTUB_STOP_NO_REASON) return(1);
|
|
}
|
|
#endif
|
|
|
|
return(0);
|
|
}
|
|
#endif // BX_DEBUGGER || BX_GDBSTUB
|
|
|
|
#if BX_DEBUGGER
|
|
|
|
void BX_CPU_C::dbg_take_irq(void)
|
|
{
|
|
// NOTE: similar code in ::cpu_loop()
|
|
|
|
if (BX_CPU_INTR && BX_CPU_THIS_PTR get_IF()) {
|
|
if (setjmp(BX_CPU_THIS_PTR jmp_buf_env) == 0) {
|
|
// normal return from setjmp setup
|
|
unsigned vector = DEV_pic_iac(); // may set INTR with next interrupt
|
|
BX_CPU_THIS_PTR EXT = 1; // external event
|
|
BX_CPU_THIS_PTR async_event = 1; // set in case INTR is triggered
|
|
interrupt(vector, BX_EXTERNAL_INTERRUPT, 0, 0);
|
|
}
|
|
}
|
|
}
|
|
|
|
void BX_CPU_C::dbg_force_interrupt(unsigned vector)
|
|
{
|
|
// Used to force simulator to take an interrupt, without
|
|
// regard to IF
|
|
|
|
if (setjmp(BX_CPU_THIS_PTR jmp_buf_env) == 0) {
|
|
// normal return from setjmp setup
|
|
BX_CPU_THIS_PTR EXT = 1; // external event
|
|
BX_CPU_THIS_PTR async_event = 1; // probably don't need this
|
|
interrupt(vector, BX_EXTERNAL_INTERRUPT, 0, 0);
|
|
}
|
|
}
|
|
|
|
void BX_CPU_C::dbg_take_dma(void)
|
|
{
|
|
// NOTE: similar code in ::cpu_loop()
|
|
if (BX_HRQ) {
|
|
BX_CPU_THIS_PTR async_event = 1; // set in case INTR is triggered
|
|
DEV_dma_raise_hlda();
|
|
}
|
|
}
|
|
|
|
#endif // #if BX_DEBUGGER
|