ff79cbd596
The end goal will be also merging of disasm and cpu decoder to one module and remove the disasm. Two bug fixes on the way: TBM: fixed 64-bit TBM instructions with memory access (did 32-bit load instead of 64-bit) BMI2: fixed operands order for PEXT/PDEP instructions AVX2: fixed gather instruction decoding bug from decoder alias commit
623 lines
15 KiB
C++
623 lines
15 KiB
C++
/////////////////////////////////////////////////////////////////////////
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// $Id$
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/////////////////////////////////////////////////////////////////////////
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//
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// Copyright (C) 2001-2012 The Bochs Project
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//
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// This library is free software; you can redistribute it and/or
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// modify it under the terms of the GNU Lesser General Public
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// License as published by the Free Software Foundation; either
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// version 2 of the License, or (at your option) any later version.
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//
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// This library is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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// Lesser General Public License for more details.
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//
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// You should have received a copy of the GNU Lesser General Public
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// License along with this library; if not, write to the Free Software
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// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA B 02110-1301 USA
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/////////////////////////////////////////////////////////////////////////
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#define NEED_CPU_REG_SHORTCUTS 1
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#include "bochs.h"
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#include "cpu.h"
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#define LOG_THIS BX_CPU_THIS_PTR
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BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::INC_EdR(bxInstruction_c *i)
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{
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Bit32u erx = ++BX_READ_32BIT_REG(i->dst());
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SET_FLAGS_OSZAP_ADD_32(erx - 1, 0, erx);
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BX_CLEAR_64BIT_HIGH(i->dst());
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BX_NEXT_INSTR(i);
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}
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BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::DEC_EdR(bxInstruction_c *i)
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{
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Bit32u erx = --BX_READ_32BIT_REG(i->dst());
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SET_FLAGS_OSZAP_SUB_32(erx + 1, 0, erx);
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BX_CLEAR_64BIT_HIGH(i->dst());
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BX_NEXT_INSTR(i);
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}
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BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::ADD_EdGdM(bxInstruction_c *i)
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{
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Bit32u op1_32, op2_32, sum_32;
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bx_address eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
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op1_32 = read_RMW_virtual_dword(i->seg(), eaddr);
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op2_32 = BX_READ_32BIT_REG(i->src());
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sum_32 = op1_32 + op2_32;
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write_RMW_virtual_dword(sum_32);
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SET_FLAGS_OSZAPC_ADD_32(op1_32, op2_32, sum_32);
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BX_NEXT_INSTR(i);
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}
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BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::ADD_GdEdR(bxInstruction_c *i)
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{
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Bit32u op1_32, op2_32, sum_32;
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op1_32 = BX_READ_32BIT_REG(i->dst());
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op2_32 = BX_READ_32BIT_REG(i->src());
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sum_32 = op1_32 + op2_32;
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BX_WRITE_32BIT_REGZ(i->dst(), sum_32);
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SET_FLAGS_OSZAPC_ADD_32(op1_32, op2_32, sum_32);
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BX_NEXT_INSTR(i);
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}
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BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::ADD_GdEdM(bxInstruction_c *i)
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{
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Bit32u op1_32, op2_32, sum_32;
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bx_address eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
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op1_32 = BX_READ_32BIT_REG(i->dst());
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op2_32 = read_virtual_dword(i->seg(), eaddr);
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sum_32 = op1_32 + op2_32;
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BX_WRITE_32BIT_REGZ(i->dst(), sum_32);
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SET_FLAGS_OSZAPC_ADD_32(op1_32, op2_32, sum_32);
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BX_NEXT_INSTR(i);
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}
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BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::ADC_EdGdM(bxInstruction_c *i)
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{
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bx_bool temp_CF = getB_CF();
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Bit32u op1_32, op2_32, sum_32;
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bx_address eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
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op1_32 = read_RMW_virtual_dword(i->seg(), eaddr);
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op2_32 = BX_READ_32BIT_REG(i->src());
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sum_32 = op1_32 + op2_32 + temp_CF;
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write_RMW_virtual_dword(sum_32);
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SET_FLAGS_OSZAPC_ADD_32(op1_32, op2_32, sum_32);
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BX_NEXT_INSTR(i);
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}
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BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::ADC_GdEdR(bxInstruction_c *i)
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{
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bx_bool temp_CF = getB_CF();
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Bit32u op1_32, op2_32, sum_32;
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op1_32 = BX_READ_32BIT_REG(i->dst());
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op2_32 = BX_READ_32BIT_REG(i->src());
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sum_32 = op1_32 + op2_32 + temp_CF;
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BX_WRITE_32BIT_REGZ(i->dst(), sum_32);
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SET_FLAGS_OSZAPC_ADD_32(op1_32, op2_32, sum_32);
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BX_NEXT_INSTR(i);
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}
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BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::ADC_GdEdM(bxInstruction_c *i)
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{
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bx_bool temp_CF = getB_CF();
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Bit32u op1_32, op2_32, sum_32;
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bx_address eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
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op1_32 = BX_READ_32BIT_REG(i->dst());
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op2_32 = read_virtual_dword(i->seg(), eaddr);
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sum_32 = op1_32 + op2_32 + temp_CF;
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BX_WRITE_32BIT_REGZ(i->dst(), sum_32);
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SET_FLAGS_OSZAPC_ADD_32(op1_32, op2_32, sum_32);
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BX_NEXT_INSTR(i);
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}
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BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::SBB_EdGdM(bxInstruction_c *i)
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{
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bx_bool temp_CF = getB_CF();
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Bit32u op1_32, op2_32, diff_32;
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bx_address eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
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op1_32 = read_RMW_virtual_dword(i->seg(), eaddr);
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op2_32 = BX_READ_32BIT_REG(i->src());
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diff_32 = op1_32 - (op2_32 + temp_CF);
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write_RMW_virtual_dword(diff_32);
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SET_FLAGS_OSZAPC_SUB_32(op1_32, op2_32, diff_32);
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BX_NEXT_INSTR(i);
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}
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BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::SBB_GdEdR(bxInstruction_c *i)
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{
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bx_bool temp_CF = getB_CF();
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Bit32u op1_32, op2_32, diff_32;
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op1_32 = BX_READ_32BIT_REG(i->dst());
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op2_32 = BX_READ_32BIT_REG(i->src());
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diff_32 = op1_32 - (op2_32 + temp_CF);
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BX_WRITE_32BIT_REGZ(i->dst(), diff_32);
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SET_FLAGS_OSZAPC_SUB_32(op1_32, op2_32, diff_32);
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BX_NEXT_INSTR(i);
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}
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BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::SBB_GdEdM(bxInstruction_c *i)
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{
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bx_bool temp_CF = getB_CF();
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Bit32u op1_32, op2_32, diff_32;
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bx_address eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
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op1_32 = BX_READ_32BIT_REG(i->dst());
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op2_32 = read_virtual_dword(i->seg(), eaddr);
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diff_32 = op1_32 - (op2_32 + temp_CF);
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BX_WRITE_32BIT_REGZ(i->dst(), diff_32);
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SET_FLAGS_OSZAPC_SUB_32(op1_32, op2_32, diff_32);
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BX_NEXT_INSTR(i);
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}
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BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::SBB_EdIdM(bxInstruction_c *i)
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{
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bx_bool temp_CF = getB_CF();
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Bit32u op1_32, op2_32 = i->Id(), diff_32;
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bx_address eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
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op1_32 = read_RMW_virtual_dword(i->seg(), eaddr);
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diff_32 = op1_32 - (op2_32 + temp_CF);
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write_RMW_virtual_dword(diff_32);
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SET_FLAGS_OSZAPC_SUB_32(op1_32, op2_32, diff_32);
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BX_NEXT_INSTR(i);
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}
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BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::SBB_EdIdR(bxInstruction_c *i)
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{
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bx_bool temp_CF = getB_CF();
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Bit32u op1_32, op2_32 = i->Id(), diff_32;
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op1_32 = BX_READ_32BIT_REG(i->dst());
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diff_32 = op1_32 - (op2_32 + temp_CF);
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BX_WRITE_32BIT_REGZ(i->dst(), diff_32);
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SET_FLAGS_OSZAPC_SUB_32(op1_32, op2_32, diff_32);
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BX_NEXT_INSTR(i);
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}
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BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::SUB_EdGdM(bxInstruction_c *i)
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{
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Bit32u op1_32, op2_32, diff_32;
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bx_address eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
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op1_32 = read_RMW_virtual_dword(i->seg(), eaddr);
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op2_32 = BX_READ_32BIT_REG(i->src());
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diff_32 = op1_32 - op2_32;
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write_RMW_virtual_dword(diff_32);
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SET_FLAGS_OSZAPC_SUB_32(op1_32, op2_32, diff_32);
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BX_NEXT_INSTR(i);
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}
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BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::SUB_GdEdR(bxInstruction_c *i)
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{
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Bit32u op1_32, op2_32, diff_32;
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op1_32 = BX_READ_32BIT_REG(i->dst());
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op2_32 = BX_READ_32BIT_REG(i->src());
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diff_32 = op1_32 - op2_32;
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BX_WRITE_32BIT_REGZ(i->dst(), diff_32);
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SET_FLAGS_OSZAPC_SUB_32(op1_32, op2_32, diff_32);
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BX_NEXT_INSTR(i);
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}
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BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::SUB_GdEdM(bxInstruction_c *i)
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{
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Bit32u op1_32, op2_32, diff_32;
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bx_address eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
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op1_32 = BX_READ_32BIT_REG(i->dst());
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op2_32 = read_virtual_dword(i->seg(), eaddr);
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diff_32 = op1_32 - op2_32;
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BX_WRITE_32BIT_REGZ(i->dst(), diff_32);
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SET_FLAGS_OSZAPC_SUB_32(op1_32, op2_32, diff_32);
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BX_NEXT_INSTR(i);
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}
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BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::CMP_EdGdM(bxInstruction_c *i)
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{
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Bit32u op1_32, op2_32, diff_32;
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bx_address eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
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op1_32 = read_virtual_dword(i->seg(), eaddr);
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op2_32 = BX_READ_32BIT_REG(i->src());
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diff_32 = op1_32 - op2_32;
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SET_FLAGS_OSZAPC_SUB_32(op1_32, op2_32, diff_32);
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BX_NEXT_INSTR(i);
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}
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BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::CMP_GdEdR(bxInstruction_c *i)
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{
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Bit32u op1_32, op2_32, diff_32;
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op1_32 = BX_READ_32BIT_REG(i->dst());
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op2_32 = BX_READ_32BIT_REG(i->src());
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diff_32 = op1_32 - op2_32;
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SET_FLAGS_OSZAPC_SUB_32(op1_32, op2_32, diff_32);
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BX_NEXT_INSTR(i);
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}
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BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::CMP_GdEdM(bxInstruction_c *i)
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{
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Bit32u op1_32, op2_32, diff_32;
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bx_address eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
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op1_32 = BX_READ_32BIT_REG(i->dst());
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op2_32 = read_virtual_dword(i->seg(), eaddr);
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diff_32 = op1_32 - op2_32;
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SET_FLAGS_OSZAPC_SUB_32(op1_32, op2_32, diff_32);
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BX_NEXT_INSTR(i);
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}
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BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::CWDE(bxInstruction_c *i)
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{
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/* CWDE: no flags are effected */
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Bit32u tmp = (Bit16s) AX;
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RAX = tmp;
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BX_NEXT_INSTR(i);
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}
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BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::CDQ(bxInstruction_c *i)
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{
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/* CDQ: no flags are affected */
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if (EAX & 0x80000000) {
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RDX = 0xFFFFFFFF;
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}
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else {
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RDX = 0x00000000;
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}
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BX_NEXT_INSTR(i);
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}
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BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::XADD_EdGdM(bxInstruction_c *i)
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{
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Bit32u op1_32, op2_32, sum_32;
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/* XADD dst(r/m), src(r)
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* temp <-- src + dst | sum = op2 + op1
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* src <-- dst | op2 = op1
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* dst <-- tmp | op1 = sum
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*/
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bx_address eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
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op1_32 = read_RMW_virtual_dword(i->seg(), eaddr);
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op2_32 = BX_READ_32BIT_REG(i->src());
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sum_32 = op1_32 + op2_32;
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write_RMW_virtual_dword(sum_32);
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/* and write destination into source */
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BX_WRITE_32BIT_REGZ(i->src(), op1_32);
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SET_FLAGS_OSZAPC_ADD_32(op1_32, op2_32, sum_32);
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BX_NEXT_INSTR(i);
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}
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BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::XADD_EdGdR(bxInstruction_c *i)
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{
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Bit32u op1_32, op2_32, sum_32;
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/* XADD dst(r/m), src(r)
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* temp <-- src + dst | sum = op2 + op1
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* src <-- dst | op2 = op1
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* dst <-- tmp | op1 = sum
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*/
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op1_32 = BX_READ_32BIT_REG(i->dst());
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op2_32 = BX_READ_32BIT_REG(i->src());
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sum_32 = op1_32 + op2_32;
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// and write destination into source
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// Note: if both op1 & op2 are registers, the last one written
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// should be the sum, as op1 & op2 may be the same register.
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// For example: XADD AL, AL
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BX_WRITE_32BIT_REGZ(i->src(), op1_32);
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BX_WRITE_32BIT_REGZ(i->dst(), sum_32);
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SET_FLAGS_OSZAPC_ADD_32(op1_32, op2_32, sum_32);
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BX_NEXT_INSTR(i);
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}
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BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::ADD_EdIdM(bxInstruction_c *i)
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{
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Bit32u op1_32, op2_32, sum_32;
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bx_address eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
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op1_32 = read_RMW_virtual_dword(i->seg(), eaddr);
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op2_32 = i->Id();
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sum_32 = op1_32 + op2_32;
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write_RMW_virtual_dword(sum_32);
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SET_FLAGS_OSZAPC_ADD_32(op1_32, op2_32, sum_32);
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BX_NEXT_INSTR(i);
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}
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BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::ADD_EdIdR(bxInstruction_c *i)
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{
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Bit32u op1_32, op2_32, sum_32;
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op1_32 = BX_READ_32BIT_REG(i->dst());
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op2_32 = i->Id();
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sum_32 = op1_32 + op2_32;
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BX_WRITE_32BIT_REGZ(i->dst(), sum_32);
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SET_FLAGS_OSZAPC_ADD_32(op1_32, op2_32, sum_32);
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BX_NEXT_INSTR(i);
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}
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BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::ADC_EdIdM(bxInstruction_c *i)
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{
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bx_bool temp_CF = getB_CF();
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Bit32u op1_32, op2_32 = i->Id(), sum_32;
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bx_address eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
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op1_32 = read_RMW_virtual_dword(i->seg(), eaddr);
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sum_32 = op1_32 + op2_32 + temp_CF;
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write_RMW_virtual_dword(sum_32);
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SET_FLAGS_OSZAPC_ADD_32(op1_32, op2_32, sum_32);
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BX_NEXT_INSTR(i);
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}
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BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::ADC_EdIdR(bxInstruction_c *i)
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{
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bx_bool temp_CF = getB_CF();
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Bit32u op1_32, op2_32 = i->Id(), sum_32;
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op1_32 = BX_READ_32BIT_REG(i->dst());
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sum_32 = op1_32 + op2_32 + temp_CF;
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BX_WRITE_32BIT_REGZ(i->dst(), sum_32);
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SET_FLAGS_OSZAPC_ADD_32(op1_32, op2_32, sum_32);
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BX_NEXT_INSTR(i);
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}
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BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::SUB_EdIdM(bxInstruction_c *i)
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{
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Bit32u op1_32, op2_32 = i->Id(), diff_32;
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bx_address eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
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op1_32 = read_RMW_virtual_dword(i->seg(), eaddr);
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diff_32 = op1_32 - op2_32;
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write_RMW_virtual_dword(diff_32);
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SET_FLAGS_OSZAPC_SUB_32(op1_32, op2_32, diff_32);
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BX_NEXT_INSTR(i);
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}
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BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::SUB_EdIdR(bxInstruction_c *i)
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{
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Bit32u op1_32, op2_32 = i->Id(), diff_32;
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op1_32 = BX_READ_32BIT_REG(i->dst());
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diff_32 = op1_32 - op2_32;
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BX_WRITE_32BIT_REGZ(i->dst(), diff_32);
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SET_FLAGS_OSZAPC_SUB_32(op1_32, op2_32, diff_32);
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BX_NEXT_INSTR(i);
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}
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BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::CMP_EdIdM(bxInstruction_c *i)
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{
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Bit32u op1_32, op2_32, diff_32;
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bx_address eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
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op1_32 = read_virtual_dword(i->seg(), eaddr);
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op2_32 = i->Id();
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diff_32 = op1_32 - op2_32;
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SET_FLAGS_OSZAPC_SUB_32(op1_32, op2_32, diff_32);
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BX_NEXT_INSTR(i);
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}
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BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::CMP_EdIdR(bxInstruction_c *i)
|
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{
|
|
Bit32u op1_32, op2_32, diff_32;
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op1_32 = BX_READ_32BIT_REG(i->dst());
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op2_32 = i->Id();
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diff_32 = op1_32 - op2_32;
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SET_FLAGS_OSZAPC_SUB_32(op1_32, op2_32, diff_32);
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BX_NEXT_INSTR(i);
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}
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BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::NEG_EdM(bxInstruction_c *i)
|
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{
|
|
bx_address eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
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Bit32u op1_32 = read_RMW_virtual_dword(i->seg(), eaddr);
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op1_32 = - (Bit32s)(op1_32);
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write_RMW_virtual_dword(op1_32);
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SET_FLAGS_OSZAPC_SUB_32(0, 0 - op1_32, op1_32);
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BX_NEXT_INSTR(i);
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}
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BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::NEG_EdR(bxInstruction_c *i)
|
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{
|
|
Bit32u op1_32 = BX_READ_32BIT_REG(i->dst());
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op1_32 = - (Bit32s)(op1_32);
|
|
BX_WRITE_32BIT_REGZ(i->dst(), op1_32);
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|
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SET_FLAGS_OSZAPC_SUB_32(0, 0 - op1_32, op1_32);
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|
|
|
BX_NEXT_INSTR(i);
|
|
}
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|
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BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::INC_EdM(bxInstruction_c *i)
|
|
{
|
|
bx_address eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
|
|
|
|
Bit32u op1_32 = read_RMW_virtual_dword(i->seg(), eaddr);
|
|
op1_32++;
|
|
write_RMW_virtual_dword(op1_32);
|
|
|
|
SET_FLAGS_OSZAP_ADD_32(op1_32 - 1, 0, op1_32);
|
|
|
|
BX_NEXT_INSTR(i);
|
|
}
|
|
|
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BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::DEC_EdM(bxInstruction_c *i)
|
|
{
|
|
bx_address eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
|
|
|
|
Bit32u op1_32 = read_RMW_virtual_dword(i->seg(), eaddr);
|
|
op1_32--;
|
|
write_RMW_virtual_dword(op1_32);
|
|
|
|
SET_FLAGS_OSZAP_SUB_32(op1_32 + 1, 0, op1_32);
|
|
|
|
BX_NEXT_INSTR(i);
|
|
}
|
|
|
|
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::CMPXCHG_EdGdM(bxInstruction_c *i)
|
|
{
|
|
bx_address eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
|
|
|
|
Bit32u op1_32 = read_RMW_virtual_dword(i->seg(), eaddr);
|
|
Bit32u diff_32 = EAX - op1_32;
|
|
SET_FLAGS_OSZAPC_SUB_32(EAX, op1_32, diff_32);
|
|
|
|
if (diff_32 == 0) { // if accumulator == dest
|
|
// dest <-- src
|
|
write_RMW_virtual_dword(BX_READ_32BIT_REG(i->src()));
|
|
}
|
|
else {
|
|
// accumulator <-- dest
|
|
write_RMW_virtual_dword(op1_32);
|
|
RAX = op1_32;
|
|
}
|
|
|
|
BX_NEXT_INSTR(i);
|
|
}
|
|
|
|
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::CMPXCHG_EdGdR(bxInstruction_c *i)
|
|
{
|
|
Bit32u op1_32 = BX_READ_32BIT_REG(i->dst());
|
|
Bit32u diff_32 = EAX - op1_32;
|
|
SET_FLAGS_OSZAPC_SUB_32(EAX, op1_32, diff_32);
|
|
|
|
if (diff_32 == 0) { // if accumulator == dest
|
|
// dest <-- src
|
|
BX_WRITE_32BIT_REGZ(i->dst(), BX_READ_32BIT_REG(i->src()));
|
|
}
|
|
else {
|
|
// accumulator <-- dest
|
|
RAX = op1_32;
|
|
}
|
|
|
|
BX_NEXT_INSTR(i);
|
|
}
|
|
|
|
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::CMPXCHG8B(bxInstruction_c *i)
|
|
{
|
|
bx_address eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
|
|
|
|
// check write permission for following write
|
|
Bit64u op1_64 = read_RMW_virtual_qword(i->seg(), eaddr);
|
|
Bit64u op2_64 = ((Bit64u) EDX << 32) | EAX;
|
|
|
|
if (op1_64 == op2_64) { // if accumulator == dest
|
|
// dest <-- src (ECX:EBX)
|
|
op2_64 = ((Bit64u) ECX << 32) | EBX;
|
|
write_RMW_virtual_qword(op2_64);
|
|
assert_ZF();
|
|
}
|
|
else {
|
|
// accumulator <-- dest
|
|
write_RMW_virtual_qword(op1_64);
|
|
RAX = GET32L(op1_64);
|
|
RDX = GET32H(op1_64);
|
|
clear_ZF();
|
|
}
|
|
|
|
BX_NEXT_INSTR(i);
|
|
}
|