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Bochs/bochs/cpu
History
Volker Ruppert a4bc4cc9e0 - fixed cpu parameter handling in SMP mode
2006-02-18 17:28:18 +00:00
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3dnow.cc
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access.cc
Another fix for INIT/RESET state
2005-11-19 19:38:45 +00:00
apic.cc
Define SMM mode for future implementation.
2006-02-14 19:00:08 +00:00
apic.h
Fix set 'ah,bh,ch,dh' registers from debugger
2006-01-27 19:50:00 +00:00
arith8.cc
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arith16.cc
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arith32.cc
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arith64.cc
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bcd.cc
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bit.cc
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call_far.cc
Generate #GP exception instead of #TS when TSS selector points to bad TSS
2005-12-12 19:44:06 +00:00
cpu.cc
SMM mode could leave together with pmode or any other (according to amd docs)
2006-02-14 20:03:14 +00:00
cpu.h
Fixed opcode names according to Intel docs
2006-02-17 13:34:31 +00:00
cpuid.cc
- fixed cpu parameter handling in SMP mode
2006-02-18 17:28:18 +00:00
ctrl_xfer8.cc
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ctrl_xfer16.cc
Fix 'show' command in Boch debugger.
2006-02-12 20:21:36 +00:00
ctrl_xfer32.cc
Fix 'show' command in Boch debugger.
2006-02-12 20:21:36 +00:00
ctrl_xfer64.cc
Fix 'show' command in Boch debugger.
2006-02-12 20:21:36 +00:00
ctrl_xfer_pro.cc
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data_xfer8.cc
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data_xfer16.cc
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data_xfer32.cc
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data_xfer64.cc
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debugstuff.cc
print CPU mode correctly again
2006-02-14 20:14:18 +00:00
descriptor.h
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exception.cc
- cpu options rewritten to a parameter tree
2006-02-18 16:53:18 +00:00
extdb.cc
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extdb.h
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fetchdecode64.cc
Enabled LAHF/SAHF for x86-64 mode
2006-01-17 19:50:42 +00:00
fetchdecode.cc
0f 0d (3dnow prefetch instruction) should execute as NOP when running on Intel EM64T CPU and as prefetch on AMD
2005-11-11 21:09:02 +00:00
fetchdecode.h
Fixed opcode names according to Intel docs
2006-02-17 13:34:31 +00:00
flag_ctrl_pro.cc
Rewritten task_switch mechnism according to AMD docs
2005-11-21 21:10:59 +00:00
flag_ctrl.cc
VME support - beta #1
2005-10-17 13:06:09 +00:00
fpu_emu.cc
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hostasm.h
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i387.h
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icache.h
Print FS_MSR_BASE and GS_MSR_BASE to debug registers dump (requested in bug report [ 1406387 ] JMP instruction should display absolute address)
2006-01-16 19:22:28 +00:00
init.cc
SMM mode could leave together with pmode or any other (according to amd docs)
2006-02-14 20:03:14 +00:00
io_pro.cc
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io.cc
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iret.cc
Small debug fixes
2005-12-12 22:01:22 +00:00
jmp_far.cc
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lazy_flags.cc
Totally remove the cosimulation code from Bochs.
2006-01-25 22:20:00 +00:00
lazy_flags.h
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logical8.cc
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logical16.cc
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logical32.cc
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logical64.cc
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Makefile.in
Define SMM mode for future implementation.
2006-02-14 19:00:08 +00:00
mmx.cc
Fixed opcode names according to Intel docs
2006-02-17 13:34:31 +00:00
mult8.cc
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mult16.cc
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mult32.cc
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mult64.cc
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paging.cc
Redefine registers accessors in cpu.h
2005-11-26 21:36:51 +00:00
proc_ctrl.cc
Define SMM mode for future implementation.
2006-02-14 19:00:08 +00:00
protect_ctrl.cc
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resolve16.cc
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resolve32.cc
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resolve64.cc
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ret_far.cc
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segment_ctrl_pro.cc
Fix validate_seg_regs check
2006-01-09 19:34:52 +00:00
segment_ctrl.cc
Save/restore RIP/RSP only on FAULT type exceptions, not on traps
2006-02-11 09:08:02 +00:00
shift8.cc
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shift16.cc
Missed ;
2006-01-22 18:18:19 +00:00
shift32.cc
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shift64.cc
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smm.cc
Define SMM mode for future implementation.
2006-02-14 19:00:08 +00:00
soft_int.cc
Fix 'show' command in Boch debugger.
2006-02-12 20:21:36 +00:00
sse_move.cc
This is cumulative patch for bochs debugger, it is only very first step towards working debugger supporting all new simulator functionalitieS.
2006-01-24 19:03:55 +00:00
sse_pfp.cc
Redefine registers accessors in cpu.h
2005-11-26 21:36:51 +00:00
sse_rcp.cc
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sse.cc
Fixed opcode names according to Intel docs
2006-02-17 13:34:31 +00:00
stack16.cc
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stack32.cc
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stack64.cc
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stack_pro.cc
VME support - beta #1
2005-10-17 13:06:09 +00:00
string.cc
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tasking.cc
Print FS_MSR_BASE and GS_MSR_BASE to debug registers dump (requested in bug report [ 1406387 ] JMP instruction should display absolute address)
2006-01-16 19:22:28 +00:00
todo
Remove code duplication in CPU and memory objects initialization
2006-01-11 18:22:12 +00:00
vm8086.cc
Print FS_MSR_BASE and GS_MSR_BASE to debug registers dump (requested in bug report [ 1406387 ] JMP instruction should display absolute address)
2006-01-16 19:22:28 +00:00
xmm.h
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