269 lines
8.1 KiB
C++
269 lines
8.1 KiB
C++
/////////////////////////////////////////////////////////////////////////
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// $Id$
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/////////////////////////////////////////////////////////////////////////
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//
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// Copyright (c) 2005-2011 Stanislav Shwartsman
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// Written by Stanislav Shwartsman [sshwarts at sourceforge net]
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//
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// This library is free software; you can redistribute it and/or
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// modify it under the terms of the GNU Lesser General Public
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// License as published by the Free Software Foundation; either
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// version 2 of the License, or (at your option) any later version.
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//
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// This library is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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// Lesser General Public License for more details.
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//
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// You should have received a copy of the GNU Lesser General Public
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// License along with this library; if not, write to the Free Software
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// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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//
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/////////////////////////////////////////////////////////////////////////
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#include <stdio.h>
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#include "disasm.h"
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//////////////////
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// Intel STYLE
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//////////////////
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static const char *intel_general_16bit_regname[16] = {
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"ax", "cx", "dx", "bx", "sp", "bp", "si", "di",
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"r8w", "r9w", "r10w", "r11w", "r12w", "r13w", "r14w", "r15w"
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};
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static const char *intel_general_32bit_regname[16] = {
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"eax", "ecx", "edx", "ebx", "esp", "ebp", "esi", "edi",
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"r8d", "r9d", "r10d", "r11d", "r12d", "r13d", "r14d", "r15d"
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};
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static const char *intel_general_64bit_regname[16] = {
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"rax", "rcx", "rdx", "rbx", "rsp", "rbp", "rsi", "rdi",
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"r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
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};
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static const char *intel_general_8bit_regname_rex[16] = {
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"al", "cl", "dl", "bl", "spl", "bpl", "sil", "dil",
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"r8b", "r9b", "r10b", "r11b", "r12b", "r13b", "r14b", "r15b"
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};
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static const char *intel_general_8bit_regname[8] = {
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"al", "cl", "dl", "bl", "ah", "ch", "dh", "bh"
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};
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static const char *intel_segment_name[8] = {
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"es", "cs", "ss", "ds", "fs", "gs", "??", "??"
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};
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static const char *intel_index16[8] = {
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"bx+si",
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"bx+di",
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"bp+si",
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"bp+di",
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"si",
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"di",
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"bp",
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"bx"
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};
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static const char *intel_vector_reg_name[2] = {
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"xmm", "ymm"
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};
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//////////////////
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// AT&T STYLE
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//////////////////
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static const char *att_general_16bit_regname[16] = {
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"%ax", "%cx", "%dx", "%bx", "%sp", "%bp", "%si", "%di",
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"%r8w", "%r9w", "%r10w", "%r11w", "%r12w", "%r13w", "%r14w", "%r15w"
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};
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static const char *att_general_32bit_regname[16] = {
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"%eax", "%ecx", "%edx", "%ebx", "%esp", "%ebp", "%esi", "%edi",
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"%r8d", "%r9d", "%r10d", "%r11d", "%r12d", "%r13d", "%r14d", "%r15d"
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};
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static const char *att_general_64bit_regname[16] = {
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"%rax", "%rcx", "%rdx", "%rbx", "%rsp", "%rbp", "%rsi", "%rdi",
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"%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15"
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};
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static const char *att_general_8bit_regname_rex[16] = {
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"%al", "%cl", "%dl", "%bl", "%spl", "%bpl", "%sil", "%dil",
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"%r8b", "%r9b", "%r10b", "%r11b", "%r12b", "%r13b", "%r14b", "%r15b"
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};
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static const char *att_general_8bit_regname[8] = {
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"%al", "%cl", "%dl", "%bl", "%ah", "%ch", "%dh", "%bh"
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};
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static const char *att_segment_name[8] = {
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"%es", "%cs", "%ss", "%ds", "%fs", "%gs", "%??", "%??"
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};
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static const char *att_index16[8] = {
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"%bx,%si",
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"%bx,%di",
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"%bp,%si",
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"%bp,%di",
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"%si",
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"%di",
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"%bp",
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"%bx"
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};
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static const char *att_vector_reg_name[2] = {
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"%xmm", "%ymm"
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};
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#define NULL_SEGMENT_REGISTER 7
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void disassembler::initialize_modrm_segregs()
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{
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sreg_mod00_rm16[0] = segment_name[DS_REG];
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sreg_mod00_rm16[1] = segment_name[DS_REG];
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sreg_mod00_rm16[2] = segment_name[SS_REG];
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sreg_mod00_rm16[3] = segment_name[SS_REG];
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sreg_mod00_rm16[4] = segment_name[DS_REG];
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sreg_mod00_rm16[5] = segment_name[DS_REG];
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sreg_mod00_rm16[6] = segment_name[DS_REG];
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sreg_mod00_rm16[7] = segment_name[DS_REG];
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sreg_mod01or10_rm16[0] = segment_name[DS_REG];
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sreg_mod01or10_rm16[1] = segment_name[DS_REG];
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sreg_mod01or10_rm16[2] = segment_name[SS_REG];
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sreg_mod01or10_rm16[3] = segment_name[SS_REG];
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sreg_mod01or10_rm16[4] = segment_name[DS_REG];
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sreg_mod01or10_rm16[5] = segment_name[DS_REG];
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sreg_mod01or10_rm16[6] = segment_name[SS_REG];
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sreg_mod01or10_rm16[7] = segment_name[DS_REG];
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sreg_mod00_base32[0] = segment_name[DS_REG];
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sreg_mod00_base32[1] = segment_name[DS_REG];
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sreg_mod00_base32[2] = segment_name[DS_REG];
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sreg_mod00_base32[3] = segment_name[DS_REG];
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sreg_mod00_base32[4] = segment_name[SS_REG];
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sreg_mod00_base32[5] = segment_name[DS_REG];
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sreg_mod00_base32[6] = segment_name[DS_REG];
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sreg_mod00_base32[7] = segment_name[DS_REG];
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sreg_mod00_base32[8] = segment_name[DS_REG];
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sreg_mod00_base32[9] = segment_name[DS_REG];
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sreg_mod00_base32[10] = segment_name[DS_REG];
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sreg_mod00_base32[11] = segment_name[DS_REG];
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sreg_mod00_base32[12] = segment_name[DS_REG];
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sreg_mod00_base32[13] = segment_name[DS_REG];
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sreg_mod00_base32[14] = segment_name[DS_REG];
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sreg_mod00_base32[15] = segment_name[DS_REG];
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sreg_mod01or10_base32[0] = segment_name[DS_REG];
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sreg_mod01or10_base32[1] = segment_name[DS_REG];
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sreg_mod01or10_base32[2] = segment_name[DS_REG];
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sreg_mod01or10_base32[3] = segment_name[DS_REG];
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sreg_mod01or10_base32[4] = segment_name[SS_REG];
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sreg_mod01or10_base32[5] = segment_name[SS_REG];
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sreg_mod01or10_base32[6] = segment_name[DS_REG];
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sreg_mod01or10_base32[7] = segment_name[DS_REG];
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sreg_mod01or10_base32[8] = segment_name[DS_REG];
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sreg_mod01or10_base32[9] = segment_name[DS_REG];
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sreg_mod01or10_base32[10] = segment_name[DS_REG];
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sreg_mod01or10_base32[11] = segment_name[DS_REG];
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sreg_mod01or10_base32[12] = segment_name[DS_REG];
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sreg_mod01or10_base32[13] = segment_name[DS_REG];
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sreg_mod01or10_base32[14] = segment_name[DS_REG];
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sreg_mod01or10_base32[15] = segment_name[DS_REG];
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}
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//////////////////
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// Intel STYLE
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//////////////////
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void disassembler::set_syntax_intel()
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{
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intel_mode = 1;
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general_16bit_regname = intel_general_16bit_regname;
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general_8bit_regname = intel_general_8bit_regname;
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general_32bit_regname = intel_general_32bit_regname;
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general_8bit_regname_rex = intel_general_8bit_regname_rex;
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general_64bit_regname = intel_general_64bit_regname;
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segment_name = intel_segment_name;
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index16 = intel_index16;
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vector_reg_name = intel_vector_reg_name;
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initialize_modrm_segregs();
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}
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void disassembler::print_disassembly_intel(const x86_insn *insn, const BxDisasmOpcodeInfo_t *entry)
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{
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// print opcode
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dis_sprintf("%s ", entry->IntelOpcode);
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if (entry->Operand1) {
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(this->*entry->Operand1)(insn);
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}
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if (entry->Operand2) {
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dis_sprintf(", ");
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(this->*entry->Operand2)(insn);
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}
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if (entry->Operand3) {
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dis_sprintf(", ");
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(this->*entry->Operand3)(insn);
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}
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if (entry->Operand4) {
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dis_sprintf(", ");
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(this->*entry->Operand4)(insn);
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}
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}
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//////////////////
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// AT&T STYLE
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//////////////////
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void disassembler::set_syntax_att()
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{
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intel_mode = 0;
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general_16bit_regname = att_general_16bit_regname;
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general_8bit_regname = att_general_8bit_regname;
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general_32bit_regname = att_general_32bit_regname;
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general_8bit_regname_rex = att_general_8bit_regname_rex;
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general_64bit_regname = att_general_64bit_regname;
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segment_name = att_segment_name;
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index16 = att_index16;
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vector_reg_name = att_vector_reg_name;
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initialize_modrm_segregs();
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}
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void disassembler::toggle_syntax_mode()
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{
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if (intel_mode) set_syntax_att();
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else set_syntax_intel();
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}
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void disassembler::print_disassembly_att(const x86_insn *insn, const BxDisasmOpcodeInfo_t *entry)
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{
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// print opcode
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dis_sprintf("%s ", entry->AttOpcode);
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if (entry->Operand4) {
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(this->*entry->Operand4)(insn);
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dis_sprintf(", ");
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}
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if (entry->Operand3) {
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(this->*entry->Operand3)(insn);
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dis_sprintf(", ");
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}
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if (entry->Operand2) {
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(this->*entry->Operand2)(insn);
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dis_sprintf(", ");
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}
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if (entry->Operand1) {
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(this->*entry->Operand1)(insn);
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}
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}
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