cc694377b9
Bochs instruction emulation handlers won't refer to direct fields of instructions like MODRM.NNN or MODRM.RM anymore. Use generic source/destination indications like SRC1, SRC2 and DST. All handlers are modified to support new notation. In addition fetchDecode module was modified to assign sources to instructions properly. Immediate benefits: - Removal of several duplicated handlers (FMA3 duplicated with FMA4 is a trivial example) - Simpler to understand fetch-decode code Future benefits: - Integration of disassembler into Bochs CPU module, ability to disasm bx_instruction_c instance (planned) Huge patch. Almost all source files wre modified.
274 lines
6.9 KiB
C++
274 lines
6.9 KiB
C++
/////////////////////////////////////////////////////////////////////////
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// $Id$
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/////////////////////////////////////////////////////////////////////////
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//
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// Copyright (c) 2011-2012 Stanislav Shwartsman
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// Written by Stanislav Shwartsman [sshwarts at sourceforge net]
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//
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// This library is free software; you can redistribute it and/or
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// modify it under the terms of the GNU Lesser General Public
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// License as published by the Free Software Foundation; either
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// version 2 of the License, or (at your option) any later version.
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//
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// This library is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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// Lesser General Public License for more details.
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//
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// You should have received a copy of the GNU Lesser General Public
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// License along with this library; if not, write to the Free Software
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// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA B 02110-1301 USA
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/////////////////////////////////////////////////////////////////////////
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#define NEED_CPU_REG_SHORTCUTS 1
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#include "bochs.h"
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#include "cpu.h"
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#define LOG_THIS BX_CPU_THIS_PTR
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#if BX_SUPPORT_AVX
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BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::ANDN_GdBdEdR(bxInstruction_c *i)
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{
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Bit32u op1_32 = BX_READ_32BIT_REG(i->src1());
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Bit32u op2_32 = BX_READ_32BIT_REG(i->src2());
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op1_32 = ~op1_32 & op2_32;
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SET_FLAGS_OSZAxC_LOGIC_32(op1_32); // keep PF unchanged
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BX_WRITE_32BIT_REGZ(i->dst(), op1_32);
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BX_NEXT_INSTR(i);
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}
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BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::MULX_GdBdEdR(bxInstruction_c *i)
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{
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Bit32u op1_32 = EDX;
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Bit32u op2_32 = BX_READ_32BIT_REG(i->src2());
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Bit64u product_64 = ((Bit64u) op1_32) * ((Bit64u) op2_32);
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BX_WRITE_32BIT_REGZ(i->src1(), GET32L(product_64));
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BX_WRITE_32BIT_REGZ(i->dst(), GET32H(product_64));
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BX_NEXT_INSTR(i);
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}
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BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::BLSI_BdEdR(bxInstruction_c *i)
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{
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Bit32u op1_32 = BX_READ_32BIT_REG(i->src());
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bx_bool tmpCF = (op1_32 != 0);
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op1_32 = (-op1_32) & op1_32;
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SET_FLAGS_OSZAxC_LOGIC_32(op1_32); // keep PF unchanged
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set_CF(tmpCF);
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BX_WRITE_32BIT_REGZ(i->dst(), op1_32);
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BX_NEXT_INSTR(i);
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}
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BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::BLSMSK_BdEdR(bxInstruction_c *i)
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{
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Bit32u op1_32 = BX_READ_32BIT_REG(i->src());
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bx_bool tmpCF = (op1_32 == 0);
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op1_32 = (op1_32-1) ^ op1_32;
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SET_FLAGS_OSZAxC_LOGIC_32(op1_32); // keep PF unchanged
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set_CF(tmpCF);
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BX_WRITE_32BIT_REGZ(i->dst(), op1_32);
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BX_NEXT_INSTR(i);
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}
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BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::BLSR_BdEdR(bxInstruction_c *i)
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{
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Bit32u op1_32 = BX_READ_32BIT_REG(i->src());
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bx_bool tmpCF = (op1_32 == 0);
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op1_32 = (op1_32-1) & op1_32;
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SET_FLAGS_OSZAxC_LOGIC_32(op1_32); // keep PF unchanged
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set_CF(tmpCF);
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BX_WRITE_32BIT_REGZ(i->dst(), op1_32);
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BX_NEXT_INSTR(i);
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}
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BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::RORX_GdEdIbR(bxInstruction_c *i)
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{
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Bit32u op1_32 = BX_READ_32BIT_REG(i->src());
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unsigned count = i->Ib() & 0x1f;
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if (count) {
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op1_32 = (op1_32 >> count) | (op1_32 << (32 - count));
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}
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BX_WRITE_32BIT_REGZ(i->dst(), op1_32);
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BX_NEXT_INSTR(i);
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}
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BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::SHRX_GdEdBdR(bxInstruction_c *i)
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{
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Bit32u op1_32 = BX_READ_32BIT_REG(i->src1());
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unsigned count = BX_READ_32BIT_REG(i->src2()) & 0x1f;
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if (count)
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op1_32 >>= count;
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BX_WRITE_32BIT_REGZ(i->dst(), op1_32);
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BX_NEXT_INSTR(i);
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}
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BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::SARX_GdEdBdR(bxInstruction_c *i)
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{
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Bit32u op1_32 = BX_READ_32BIT_REG(i->src1());
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unsigned count = BX_READ_32BIT_REG(i->src2()) & 0x1f;
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if (count) {
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/* count < 32, since only lower 5 bits used */
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op1_32 = ((Bit32s) op1_32) >> count;
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}
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BX_WRITE_32BIT_REGZ(i->dst(), op1_32);
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BX_NEXT_INSTR(i);
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}
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BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::SHLX_GdEdBdR(bxInstruction_c *i)
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{
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Bit32u op1_32 = BX_READ_32BIT_REG(i->src1());
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unsigned count = BX_READ_32BIT_REG(i->src2()) & 0x1f;
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if (count)
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op1_32 <<= count;
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BX_WRITE_32BIT_REGZ(i->dst(), op1_32);
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BX_NEXT_INSTR(i);
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}
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BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::BEXTR_GdEdBdR(bxInstruction_c *i)
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{
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Bit16u control = BX_READ_16BIT_REG(i->src2());
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unsigned start = control & 0xff;
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unsigned len = control >> 8;
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Bit32u op1_32 = 0;
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if (start < 32 && len > 0) {
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op1_32 = BX_READ_32BIT_REG(i->src1());
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op1_32 >>= start;
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if (len < 32) {
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Bit32u extract_mask = (1 << len) - 1;
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op1_32 &= extract_mask;
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}
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}
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SET_FLAGS_OSZAPC_LOGIC_32(op1_32);
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BX_WRITE_32BIT_REGZ(i->dst(), op1_32);
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BX_NEXT_INSTR(i);
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}
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BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::BZHI_GdEdBdR(bxInstruction_c *i)
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{
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unsigned control = BX_READ_16BIT_REG(i->src1()) & 0xff;
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bx_bool tmpCF = 0;
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Bit32u op1_32 = BX_READ_32BIT_REG(i->src2());
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if (control < 32) {
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Bit32u mask = (1 << control) - 1;
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op1_32 &= mask;
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}
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else {
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tmpCF = 1;
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}
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SET_FLAGS_OSZAxC_LOGIC_32(op1_32); // keep PF unchanged
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set_CF(tmpCF);
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BX_WRITE_32BIT_REGZ(i->dst(), op1_32);
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BX_NEXT_INSTR(i);
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}
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BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::PEXT_GdEdBdR(bxInstruction_c *i)
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{
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Bit32u op1_32 = BX_READ_32BIT_REG(i->src1());
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Bit32u op2_32 = BX_READ_32BIT_REG(i->src2()), result_32 = 0;
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Bit32u wr_mask = 0x1;
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for (; op2_32 != 0; op2_32 >>= 1)
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{
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if (op2_32 & 0x1) {
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if (op1_32 & 0x1) result_32 |= wr_mask;
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wr_mask <<= 1;
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}
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op1_32 >>= 1;
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}
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BX_WRITE_32BIT_REGZ(i->dst(), result_32);
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BX_NEXT_INSTR(i);
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}
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BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::PDEP_GdEdBdR(bxInstruction_c *i)
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{
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Bit32u op1_32 = BX_READ_32BIT_REG(i->src1());
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Bit32u op2_32 = BX_READ_32BIT_REG(i->src2()), result_32 = 0;
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Bit32u wr_mask = 0x1;
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for (; op2_32 != 0; op2_32 >>= 1)
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{
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if (op2_32 & 0x1) {
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if (op1_32 & 0x1) result_32 |= wr_mask;
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op1_32 >>= 1;
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}
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wr_mask <<= 1;
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}
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BX_WRITE_32BIT_REGZ(i->dst(), result_32);
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BX_NEXT_INSTR(i);
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}
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#endif
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BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::ADCX_GdEdR(bxInstruction_c *i)
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{
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Bit32u op1_32 = BX_READ_32BIT_REG(i->dst());
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Bit32u op2_32 = BX_READ_32BIT_REG(i->src());
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Bit32u sum_32 = op1_32 + op2_32 + getB_CF();
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BX_WRITE_32BIT_REGZ(i->dst(), sum_32);
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Bit32u carry_out = ADD_COUT_VEC(op1_32, op2_32, sum_32);
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set_CF(carry_out >> 31);
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BX_NEXT_INSTR(i);
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}
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BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::ADOX_GdEdR(bxInstruction_c *i)
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{
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Bit32u op1_32 = BX_READ_32BIT_REG(i->dst());
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Bit32u op2_32 = BX_READ_32BIT_REG(i->src());
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Bit32u sum_32 = op1_32 + op2_32 + getB_OF();
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BX_WRITE_32BIT_REGZ(i->dst(), sum_32);
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Bit32u overflow = GET_ADD_OVERFLOW(op1_32, op2_32, sum_32, 0x80000000);
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set_OF(!!overflow);
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BX_NEXT_INSTR(i);
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}
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