2f3c7ff8e4
fixed enabling of ADX extensions in generic CPUID when enabled through .bochsrc Small code cleanups on the way to implementation of APIC Registers Virtualization features disclosed in recent Intel SDM rev043
420 lines
9.8 KiB
C++
420 lines
9.8 KiB
C++
/////////////////////////////////////////////////////////////////////////
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// $Id$
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/////////////////////////////////////////////////////////////////////////
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//
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// Copyright (C) 2002-2012 The Bochs Project
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//
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// This library is free software; you can redistribute it and/or
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// modify it under the terms of the GNU Lesser General Public
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// License as published by the Free Software Foundation; either
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// version 2 of the License, or (at your option) any later version.
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//
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// This library is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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// Lesser General Public License for more details.
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//
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// You should have received a copy of the GNU Lesser General Public
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// License along with this library; if not, write to the Free Software
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// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA B 02110-1301 USA
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/////////////////////////////////////////////////////////////////////////
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#define NEED_CPU_REG_SHORTCUTS 1
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#include "bochs.h"
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#include "cpu.h"
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#define LOG_THIS BX_CPU_THIS_PTR
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BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::SAHF(bxInstruction_c *i)
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{
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set_SF((AH & 0x80) >> 7);
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set_ZF((AH & 0x40) >> 6);
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set_AF((AH & 0x10) >> 4);
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set_CF (AH & 0x01);
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set_PF((AH & 0x04) >> 2);
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BX_NEXT_INSTR(i);
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}
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BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::LAHF(bxInstruction_c *i)
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{
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AH = read_eflags() & 0xFF;
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BX_NEXT_INSTR(i);
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}
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BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::CLC(bxInstruction_c *i)
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{
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clear_CF();
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BX_NEXT_INSTR(i);
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}
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BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::STC(bxInstruction_c *i)
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{
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assert_CF();
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BX_NEXT_INSTR(i);
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}
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BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::CLI(bxInstruction_c *i)
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{
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Bit32u IOPL = BX_CPU_THIS_PTR get_IOPL();
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if (protected_mode())
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{
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#if BX_CPU_LEVEL >= 5
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if (BX_CPU_THIS_PTR cr4.get_PVI() && (CPL == 3))
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{
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if (IOPL < 3) {
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BX_CPU_THIS_PTR clear_VIF();
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BX_NEXT_INSTR(i);
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}
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}
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else
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#endif
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{
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if (IOPL < CPL) {
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BX_DEBUG(("CLI: IOPL < CPL in protected mode"));
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exception(BX_GP_EXCEPTION, 0);
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}
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}
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}
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else if (v8086_mode())
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{
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if (IOPL != 3) {
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#if BX_CPU_LEVEL >= 5
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if (BX_CPU_THIS_PTR cr4.get_VME()) {
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BX_CPU_THIS_PTR clear_VIF();
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BX_NEXT_INSTR(i);
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}
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#endif
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BX_DEBUG(("CLI: IOPL != 3 in v8086 mode"));
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exception(BX_GP_EXCEPTION, 0);
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}
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}
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BX_CPU_THIS_PTR clear_IF();
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BX_NEXT_INSTR(i);
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}
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BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::STI(bxInstruction_c *i)
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{
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Bit32u IOPL = BX_CPU_THIS_PTR get_IOPL();
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if (protected_mode())
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{
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#if BX_CPU_LEVEL >= 5
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if (BX_CPU_THIS_PTR cr4.get_PVI())
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{
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if (CPL == 3 && IOPL < 3) {
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if (! BX_CPU_THIS_PTR get_VIP())
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{
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BX_CPU_THIS_PTR assert_VIF();
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BX_NEXT_INSTR(i);
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}
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BX_DEBUG(("STI: #GP(0) in VME mode"));
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exception(BX_GP_EXCEPTION, 0);
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}
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}
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#endif
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if (CPL > IOPL) {
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BX_DEBUG(("STI: CPL > IOPL in protected mode"));
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exception(BX_GP_EXCEPTION, 0);
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}
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}
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else if (v8086_mode())
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{
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if (IOPL != 3) {
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#if BX_CPU_LEVEL >= 5
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if (BX_CPU_THIS_PTR cr4.get_VME() && BX_CPU_THIS_PTR get_VIP() == 0)
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{
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BX_CPU_THIS_PTR assert_VIF();
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BX_NEXT_INSTR(i);
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}
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#endif
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BX_DEBUG(("STI: IOPL != 3 in v8086 mode"));
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exception(BX_GP_EXCEPTION, 0);
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}
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}
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if (! BX_CPU_THIS_PTR get_IF()) {
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BX_CPU_THIS_PTR assert_IF();
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inhibit_interrupts(BX_INHIBIT_INTERRUPTS);
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BX_CPU_THIS_PTR async_event = 1;
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}
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BX_NEXT_INSTR(i);
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}
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BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::CLD(bxInstruction_c *i)
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{
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BX_CPU_THIS_PTR clear_DF();
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BX_NEXT_INSTR(i);
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}
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BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::STD(bxInstruction_c *i)
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{
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BX_CPU_THIS_PTR assert_DF();
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BX_NEXT_INSTR(i);
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}
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BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::CMC(bxInstruction_c *i)
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{
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set_CF(! get_CF());
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BX_NEXT_INSTR(i);
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}
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BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::PUSHF_Fw(bxInstruction_c *i)
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{
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#if BX_SUPPORT_SVM
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if (BX_CPU_THIS_PTR in_svm_guest) {
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if (SVM_INTERCEPT(SVM_INTERCEPT0_PUSHF)) Svm_Vmexit(SVM_VMEXIT_PUSHF);
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}
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#endif
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Bit16u flags = (Bit16u) read_eflags();
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if (v8086_mode()) {
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if (BX_CPU_THIS_PTR get_IOPL() < 3) {
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#if BX_CPU_LEVEL >= 5
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if (BX_CPU_THIS_PTR cr4.get_VME()) {
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flags |= EFlagsIOPLMask;
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if (BX_CPU_THIS_PTR get_VIF())
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flags |= EFlagsIFMask;
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else
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flags &= ~EFlagsIFMask;
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}
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else
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#endif
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{
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BX_DEBUG(("PUSHFW: #GP(0) in v8086 (no VME) mode"));
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exception(BX_GP_EXCEPTION, 0);
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}
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}
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}
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push_16(flags);
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BX_NEXT_INSTR(i);
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}
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BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::POPF_Fw(bxInstruction_c *i)
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{
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#if BX_SUPPORT_SVM
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if (BX_CPU_THIS_PTR in_svm_guest) {
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if (SVM_INTERCEPT(SVM_INTERCEPT0_POPF)) Svm_Vmexit(SVM_VMEXIT_POPF);
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}
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#endif
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// Build a mask of the following bits:
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// x,NT,IOPL,OF,DF,IF,TF,SF,ZF,x,AF,x,PF,x,CF
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Bit32u changeMask = EFlagsOSZAPCMask | EFlagsTFMask | EFlagsDFMask | EFlagsNTMask;
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RSP_SPECULATIVE;
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Bit16u flags16 = pop_16();
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if (protected_mode()) {
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if (CPL==0)
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changeMask |= EFlagsIOPLMask;
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if (CPL <= BX_CPU_THIS_PTR get_IOPL())
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changeMask |= EFlagsIFMask;
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}
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else if (v8086_mode()) {
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if (BX_CPU_THIS_PTR get_IOPL() < 3) {
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#if BX_CPU_LEVEL >= 5
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if (BX_CPU_THIS_PTR cr4.get_VME()) {
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if (((flags16 & EFlagsIFMask) && BX_CPU_THIS_PTR get_VIP()) ||
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(flags16 & EFlagsTFMask))
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{
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BX_ERROR(("POPFW: #GP(0) in VME mode"));
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exception(BX_GP_EXCEPTION, 0);
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}
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// IF, IOPL unchanged, EFLAGS.VIF = TMP_FLAGS.IF
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changeMask |= EFlagsVIFMask;
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Bit32u flags32 = (Bit32u) flags16;
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if (flags32 & EFlagsIFMask) flags32 |= EFlagsVIFMask;
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writeEFlags(flags32, changeMask);
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RSP_COMMIT;
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BX_NEXT_INSTR(i);
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}
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#endif
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BX_DEBUG(("POPFW: #GP(0) in v8086 (no VME) mode"));
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exception(BX_GP_EXCEPTION, 0);
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}
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changeMask |= EFlagsIFMask;
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}
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else {
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// All non-reserved flags can be modified
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changeMask |= (EFlagsIOPLMask | EFlagsIFMask);
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}
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writeEFlags((Bit32u) flags16, changeMask);
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RSP_COMMIT;
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BX_NEXT_INSTR(i);
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}
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#if BX_CPU_LEVEL >= 3
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BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::PUSHF_Fd(bxInstruction_c *i)
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{
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#if BX_SUPPORT_SVM
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if (BX_CPU_THIS_PTR in_svm_guest) {
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if (SVM_INTERCEPT(SVM_INTERCEPT0_PUSHF)) Svm_Vmexit(SVM_VMEXIT_PUSHF);
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}
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#endif
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if (v8086_mode() && (BX_CPU_THIS_PTR get_IOPL()<3)) {
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BX_DEBUG(("PUSHFD: #GP(0) in v8086 mode"));
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exception(BX_GP_EXCEPTION, 0);
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}
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// VM & RF flags cleared in image stored on the stack
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push_32(read_eflags() & 0x00fcffff);
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BX_NEXT_INSTR(i);
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}
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BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::POPF_Fd(bxInstruction_c *i)
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{
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#if BX_SUPPORT_SVM
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if (BX_CPU_THIS_PTR in_svm_guest) {
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if (SVM_INTERCEPT(SVM_INTERCEPT0_POPF)) Svm_Vmexit(SVM_VMEXIT_POPF);
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}
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#endif
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// Build a mask of the following bits:
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// ID,VIP,VIF,AC,VM,RF,x,NT,IOPL,OF,DF,IF,TF,SF,ZF,x,AF,x,PF,x,CF
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Bit32u changeMask = EFlagsOSZAPCMask | EFlagsTFMask |
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EFlagsDFMask | EFlagsNTMask | EFlagsRFMask;
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#if BX_CPU_LEVEL >= 4
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changeMask |= (EFlagsIDMask | EFlagsACMask); // ID/AC
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#endif
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RSP_SPECULATIVE;
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Bit32u flags32 = pop_32();
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if (protected_mode()) {
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// IOPL changed only if (CPL == 0),
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// IF changed only if (CPL <= EFLAGS.IOPL),
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// VIF, VIP, VM are unaffected
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if (CPL==0)
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changeMask |= EFlagsIOPLMask;
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if (CPL <= BX_CPU_THIS_PTR get_IOPL())
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changeMask |= EFlagsIFMask;
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}
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else if (v8086_mode()) {
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if (BX_CPU_THIS_PTR get_IOPL() < 3) {
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BX_ERROR(("POPFD: #GP(0) in v8086 mode"));
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exception(BX_GP_EXCEPTION, 0);
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}
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// v8086-mode: VM, IOPL, VIP, VIF are unaffected
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changeMask |= EFlagsIFMask;
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}
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else { // Real-mode
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// VIF, VIP, VM are unaffected
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changeMask |= (EFlagsIOPLMask | EFlagsIFMask);
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}
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writeEFlags(flags32, changeMask);
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RSP_COMMIT;
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BX_NEXT_INSTR(i);
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}
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#if BX_SUPPORT_X86_64
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BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::PUSHF_Fq(bxInstruction_c *i)
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{
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#if BX_SUPPORT_SVM
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if (BX_CPU_THIS_PTR in_svm_guest) {
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if (SVM_INTERCEPT(SVM_INTERCEPT0_PUSHF)) Svm_Vmexit(SVM_VMEXIT_PUSHF);
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}
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#endif
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// VM & RF flags cleared in image stored on the stack
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push_64(read_eflags() & 0x00fcffff);
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BX_NEXT_INSTR(i);
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}
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BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::POPF_Fq(bxInstruction_c *i)
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{
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#if BX_SUPPORT_SVM
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if (BX_CPU_THIS_PTR in_svm_guest) {
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if (SVM_INTERCEPT(SVM_INTERCEPT0_POPF)) Svm_Vmexit(SVM_VMEXIT_POPF);
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}
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#endif
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// Build a mask of the following bits:
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// ID,VIP,VIF,AC,VM,RF,x,NT,IOPL,OF,DF,IF,TF,SF,ZF,x,AF,x,PF,x,CF
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Bit32u changeMask = EFlagsOSZAPCMask | EFlagsTFMask | EFlagsDFMask
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| EFlagsNTMask | EFlagsRFMask | EFlagsACMask
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| EFlagsIDMask;
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BX_ASSERT (protected_mode());
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Bit32u eflags32 = (Bit32u) pop_64();
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if (CPL==0)
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changeMask |= EFlagsIOPLMask;
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if (CPL <= BX_CPU_THIS_PTR get_IOPL())
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changeMask |= EFlagsIFMask;
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// VIF, VIP, VM are unaffected
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writeEFlags(eflags32, changeMask);
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BX_NEXT_INSTR(i);
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}
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#endif
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#endif // BX_CPU_LEVEL >= 3
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BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::SALC(bxInstruction_c *i)
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{
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if (get_CF()) {
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AL = 0xff;
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}
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else {
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AL = 0x00;
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}
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BX_NEXT_INSTR(i);
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}
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BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::STAC(bxInstruction_c *i)
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{
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if (CPL != 0) {
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BX_ERROR(("STAC is not recognized when CPL != 0"));
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exception(BX_UD_EXCEPTION, 0);
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}
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assert_AC();
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BX_NEXT_INSTR(i);
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}
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BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::CLAC(bxInstruction_c *i)
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{
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if (CPL != 0) {
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BX_ERROR(("CLAC is not recognized when CPL != 0"));
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exception(BX_UD_EXCEPTION, 0);
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}
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clear_AC();
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BX_NEXT_INSTR(i);
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}
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