376 lines
12 KiB
C++
Executable File
376 lines
12 KiB
C++
Executable File
/////////////////////////////////////////////////////////////////////////
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// $Id: xsave.cc,v 1.5 2008-03-22 21:29:41 sshwarts Exp $
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/////////////////////////////////////////////////////////////////////////
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//
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// Copyright (c) 2008 Stanislav Shwartsman
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// Written by Stanislav Shwartsman [sshwarts at sourceforge net]
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//
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// This library is free software; you can redistribute it and/or
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// modify it under the terms of the GNU Lesser General Public
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// License as published by the Free Software Foundation; either
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// version 2 of the License, or (at your option) any later version.
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//
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// This library is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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// Lesser General Public License for more details.
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//
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// You should have received a copy of the GNU Lesser General Public
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// License along with this library; if not, write to the Free Software
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// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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//
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/////////////////////////////////////////////////////////////////////////
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#define NEED_CPU_REG_SHORTCUTS 1
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#include "bochs.h"
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#include "cpu.h"
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#define LOG_THIS BX_CPU_THIS_PTR
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// Make code more tidy with a few macros.
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#if BX_SUPPORT_X86_64==0
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#define RAX EAX
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#define RDX EDX
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#endif
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#if BX_SUPPORT_XSAVE
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void BX_CPU_C::prepareXSAVE(void)
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{
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if(! (BX_CPU_THIS_PTR cr4.get_OSXSAVE()))
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exception(BX_UD_EXCEPTION, 0, 0);
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if(BX_CPU_THIS_PTR cr0.get_TS())
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exception(BX_NM_EXCEPTION, 0, 0);
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}
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#endif
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/* 0F AE /4 */
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void BX_CPP_AttrRegparmN(1) BX_CPU_C::XSAVE(bxInstruction_c *i)
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{
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#if BX_SUPPORT_XSAVE
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unsigned index;
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BxPackedXmmRegister xmm;
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BX_CPU_THIS_PTR prepareXSAVE();
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BX_DEBUG(("XSAVE: save processor state XCR0=0x%08x", BX_CPU_THIS_PTR xcr0.getRegister()));
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BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
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bx_address laddr = BX_CPU_THIS_PTR get_segment_base(i->seg()) + RMAddr(i);
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if (laddr & 0x3f) {
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BX_ERROR(("XSAVE: access not aligned to 64-byte"));
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exception(BX_GP_EXCEPTION, 0, 0);
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}
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//
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// We will go feature-by-feature and not run over all XCR0 bits
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//
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/////////////////////////////////////////////////////////////////////////////
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if (BX_CPU_THIS_PTR xcr0.get_FPU() && (EAX & BX_XCR0_FPU_MASK) != 0)
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{
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xmm.xmm16u(0) = BX_CPU_THIS_PTR the_i387.get_control_word();
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xmm.xmm16u(1) = BX_CPU_THIS_PTR the_i387.get_status_word ();
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Bit16u twd = BX_CPU_THIS_PTR the_i387.get_tag_word(), tag_byte = 0;
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if((twd & 0x0003) != 0x0003) tag_byte |= 0x01;
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if((twd & 0x000c) != 0x000c) tag_byte |= 0x02;
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if((twd & 0x0030) != 0x0030) tag_byte |= 0x04;
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if((twd & 0x00c0) != 0x00c0) tag_byte |= 0x08;
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if((twd & 0x0300) != 0x0300) tag_byte |= 0x10;
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if((twd & 0x0c00) != 0x0c00) tag_byte |= 0x20;
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if((twd & 0x3000) != 0x3000) tag_byte |= 0x40;
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if((twd & 0xc000) != 0xc000) tag_byte |= 0x80;
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xmm.xmm16u(2) = tag_byte;
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/* x87 FPU Opcode (16 bits) */
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/* The lower 11 bits contain the FPU opcode, upper 5 bits are reserved */
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xmm.xmm16u(3) = BX_CPU_THIS_PTR the_i387.foo;
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/*
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* x87 FPU IP Offset (32/64 bits)
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* The contents of this field differ depending on the current
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* addressing mode (16/32/64 bit) when the FXSAVE instruction was executed:
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* + 64-bit mode - 64-bit IP offset
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* + 32-bit mode - 32-bit IP offset
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* + 16-bit mode - low 16 bits are IP offset; high 16 bits are reserved.
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* x87 CS FPU IP Selector
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* + 16 bit, in 16/32 bit mode only
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*/
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#if BX_SUPPORT_X86_64
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if (i->os64L()) {
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xmm.xmm64u(1) = (BX_CPU_THIS_PTR the_i387.fip);
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}
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else
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#endif
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{
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xmm.xmm32u(2) = (Bit32u)(BX_CPU_THIS_PTR the_i387.fip) & 0xffffffff;
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xmm.xmm32u(3) = (BX_CPU_THIS_PTR the_i387.fcs);
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}
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write_virtual_dqword(i->seg(), RMAddr(i), (Bit8u *) &xmm);
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/*
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* x87 FPU Instruction Operand (Data) Pointer Offset (32/64 bits)
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* The contents of this field differ depending on the current
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* addressing mode (16/32 bit) when the FXSAVE instruction was executed:
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* + 64-bit mode - 64-bit offset
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* + 32-bit mode - 32-bit offset
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* + 16-bit mode - low 16 bits are offset; high 16 bits are reserved.
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* x87 DS FPU Instruction Operand (Data) Pointer Selector
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* + 16 bit, in 16/32 bit mode only
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*/
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#if BX_SUPPORT_X86_64
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if (i->os64L()) {
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write_virtual_qword(i->seg(), RMAddr(i) + 16, BX_CPU_THIS_PTR the_i387.fdp);
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}
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else
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#endif
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{
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write_virtual_dword(i->seg(), RMAddr(i) + 16,
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(Bit32u)(BX_CPU_THIS_PTR the_i387.fdp & 0xffffffff));
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write_virtual_dword(i->seg(), RMAddr(i) + 20,
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(Bit32u)(BX_CPU_THIS_PTR the_i387.fds));
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}
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/* do not touch MXCSR state */
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/* store i387 register file */
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for(index=0; index < 8; index++)
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{
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const floatx80 &fp = BX_FPU_REG(index);
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xmm.xmm64u(0) = fp.fraction;
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xmm.xmm64u(1) = 0;
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xmm.xmm16u(4) = fp.exp;
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write_virtual_dqword(i->seg(), RMAddr(i)+index*16+32, (Bit8u *) &xmm);
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}
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}
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/////////////////////////////////////////////////////////////////////////////
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if (BX_CPU_THIS_PTR xcr0.get_SSE() && (EAX & BX_XCR0_SSE_MASK) != 0)
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{
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write_virtual_dword(i->seg(), RMAddr(i) + 24, BX_MXCSR_REGISTER);
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write_virtual_dword(i->seg(), RMAddr(i) + 28, MXCSR_MASK);
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/* store XMM register file */
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for(index=0; index < BX_XMM_REGISTERS; index++)
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{
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// save XMM8-XMM15 only in 64-bit mode
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if (index < 8 || Is64BitMode()) {
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write_virtual_dqword(i->seg(),
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RMAddr(i)+index*16+160, (Bit8u *) &(BX_CPU_THIS_PTR xmm[index]));
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}
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}
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}
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// skip header update for now, required to know if a CPU feature is in its initial state
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#else
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BX_INFO(("XSAVE: required XSAVE support, use --enable-xsave option"));
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UndefinedOpcode(i);
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#endif
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}
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/* 0F AE /5 */
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void BX_CPP_AttrRegparmN(1) BX_CPU_C::XRSTOR(bxInstruction_c *i)
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{
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#if BX_SUPPORT_XSAVE
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unsigned index;
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BxPackedXmmRegister xmm;
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BX_CPU_THIS_PTR prepareXSAVE();
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BX_DEBUG(("XRSTOR: restore processor state XCR0=0x%08x", BX_CPU_THIS_PTR xcr0.getRegister()));
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BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
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bx_address laddr = BX_CPU_THIS_PTR get_segment_base(i->seg()) + RMAddr(i);
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if (laddr & 0x3f) {
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BX_ERROR(("XRSTOR: access not aligned to 64-byte"));
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exception(BX_GP_EXCEPTION, 0, 0);
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}
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Bit64u header1 = read_virtual_qword(i->seg(), RMAddr(i) + 512);
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Bit64u header2 = read_virtual_qword(i->seg(), RMAddr(i) + 520);
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Bit64u header3 = read_virtual_qword(i->seg(), RMAddr(i) + 528);
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if ((~BX_CPU_THIS_PTR xcr0.getRegister() & header1) != 0) {
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BX_ERROR(("XRSTOR: Broken header state"));
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exception(BX_GP_EXCEPTION, 0, 0);
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}
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if (header2 != 0 || header3 != 0) {
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BX_ERROR(("XRSTOR: Reserved header state is not '0"));
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exception(BX_GP_EXCEPTION, 0, 0);
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}
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//
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// We will go feature-by-feature and not run over all XCR0 bits
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//
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/////////////////////////////////////////////////////////////////////////////
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if (BX_CPU_THIS_PTR xcr0.get_FPU() && (EAX & BX_XCR0_FPU_MASK) != 0)
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{
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if (header1 & BX_XCR0_FPU_MASK) {
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// load FPU state from XSAVE area
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read_virtual_dqword(i->seg(), RMAddr(i), (Bit8u *) &xmm);
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BX_CPU_THIS_PTR the_i387.cwd = xmm.xmm16u(0);
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BX_CPU_THIS_PTR the_i387.swd = xmm.xmm16u(1);
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BX_CPU_THIS_PTR the_i387.tos = (xmm.xmm16u(1) >> 11) & 0x07;
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/* Restore x87 FPU Opcode */
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/* The lower 11 bits contain the FPU opcode, upper 5 bits are reserved */
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BX_CPU_THIS_PTR the_i387.foo = xmm.xmm16u(3) & 0x7FF;
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/* Restore x87 FPU IP */
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#if BX_SUPPORT_X86_64
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if (i->os64L()) {
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BX_CPU_THIS_PTR the_i387.fip = xmm.xmm64u(1);
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BX_CPU_THIS_PTR the_i387.fcs = 0;
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}
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else
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#endif
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{
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BX_CPU_THIS_PTR the_i387.fip = xmm.xmm32u(2);
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BX_CPU_THIS_PTR the_i387.fcs = xmm.xmm16u(5);
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}
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Bit32u tag_byte = xmm.xmmubyte(4);
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/* Restore x87 FPU DP */
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read_virtual_dqword(i->seg(), RMAddr(i) + 16, (Bit8u *) &xmm);
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#if BX_SUPPORT_X86_64
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if (i->os64L()) {
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BX_CPU_THIS_PTR the_i387.fdp = xmm.xmm64u(0);
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BX_CPU_THIS_PTR the_i387.fds = 0;
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}
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else
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#endif
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{
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BX_CPU_THIS_PTR the_i387.fdp = xmm.xmm32u(0);
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BX_CPU_THIS_PTR the_i387.fds = xmm.xmm16u(2);
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}
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/* load i387 register file */
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for(index=0; index < 8; index++)
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{
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read_virtual_tword(i->seg(), RMAddr(i)+index*16+32, &(BX_FPU_REG(index)));
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}
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/* Restore floating point tag word - see desription for FXRSTOR instruction */
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BX_CPU_THIS_PTR the_i387.twd = unpack_FPU_TW(tag_byte);
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}
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else {
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// initialize FPU with reset values
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BX_CPU_THIS_PTR the_i387.init();
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for (index=0;index<8;index++) {
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BX_CPU_THIS_PTR the_i387.st_space[index].exp = 0;
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BX_CPU_THIS_PTR the_i387.st_space[index].fraction = 0;
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}
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}
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}
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/////////////////////////////////////////////////////////////////////////////
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if (BX_CPU_THIS_PTR xcr0.get_SSE() && (EAX & BX_XCR0_SSE_MASK) != 0)
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{
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Bit32u new_mxcsr = read_virtual_dword(i->seg(), RMAddr(i) + 24);
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if(new_mxcsr & ~MXCSR_MASK)
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exception(BX_GP_EXCEPTION, 0, 0);
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if (header1 & BX_XCR0_SSE_MASK) {
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// load SSE state from XSAVE area
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for(index=0; index < BX_XMM_REGISTERS; index++)
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{
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// restore XMM8-XMM15 only in 64-bit mode
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if (index < 8 || Is64BitMode()) {
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read_virtual_dqword(i->seg(),
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RMAddr(i)+index*16+160, (Bit8u *) &(BX_CPU_THIS_PTR xmm[index]));
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}
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}
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}
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else {
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// initialize SSE with reset values
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for(index=0; index < BX_XMM_REGISTERS; index++) {
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// set XMM8-XMM15 only in 64-bit mode
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if (index < 8 || Is64BitMode()) {
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BX_CPU_THIS_PTR xmm[index].xmm64u(0) = 0;
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BX_CPU_THIS_PTR xmm[index].xmm64u(1) = 0;
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}
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}
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}
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}
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#else
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BX_INFO(("XRSTOR: required XSAVE support, use --enable-xsave option"));
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UndefinedOpcode(i);
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#endif
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}
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/* 0F 01 D0 */
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void BX_CPP_AttrRegparmN(1) BX_CPU_C::XGETBV(bxInstruction_c *i)
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{
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#if BX_SUPPORT_XSAVE
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if(! (BX_CPU_THIS_PTR cr4.get_OSXSAVE())) {
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BX_ERROR(("XGETBV: OSXSAVE feature is not enabled in CR4!"));
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exception(BX_UD_EXCEPTION, 0, 0);
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}
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// For now hardcoded handle only XCR0 register, it should take a few
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// years until extension will be required
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if (ECX != 0) {
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BX_ERROR(("XGETBV: Invalid XCR register %d", ECX));
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exception(BX_GP_EXCEPTION, 0, 0);
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}
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RDX = 0;
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RAX = BX_CPU_THIS_PTR xcr0.getRegister();
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#else
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BX_INFO(("XGETBV: required XSAVE support, use --enable-xsave option"));
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UndefinedOpcode(i);
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#endif
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}
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/* 0F 01 D1 */
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void BX_CPP_AttrRegparmN(1) BX_CPU_C::XSETBV(bxInstruction_c *i)
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{
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#if BX_SUPPORT_XSAVE
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if (real_mode() || v8086_mode()) {
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BX_ERROR(("XSETBV: not recognized in real or virtual-8086 mode"));
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exception(BX_UD_EXCEPTION, 0, 0);
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}
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if(! (BX_CPU_THIS_PTR cr4.get_OSXSAVE())) {
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BX_ERROR(("XSETBV: OSXSAVE feature is not enabled in CR4!"));
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exception(BX_UD_EXCEPTION, 0, 0);
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}
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if (CPL != 0) {
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BX_ERROR(("XSETBV: The current priveledge level is not 0"));
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exception(BX_GP_EXCEPTION, 0, 0);
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}
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// For now hardcoded handle only XCR0 register, it should take a few
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// years until extension will be required
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if (ECX != 0) {
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BX_ERROR(("XSETBV: Invalid XCR register %d", ECX));
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exception(BX_GP_EXCEPTION, 0, 0);
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}
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if (EDX != 0 || (EAX & ~BX_XCR0_SUPPORT_BITS) != 0 || (EAX & 1) == 0) {
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BX_ERROR(("XSETBV: Attempting to change reserved bits!"));
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exception(BX_GP_EXCEPTION, 0, 0);
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}
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BX_CPU_THIS_PTR xcr0.setRegister(EAX);
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#else
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BX_INFO(("XSETBV: required XSAVE support, use --enable-xsave option"));
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UndefinedOpcode(i);
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#endif
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}
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