b84f0bd0f2
there to offer a way to substitute more efficient code to do the RMW cases. At the moment, they just map to the normal functions. Sorry, restored the previous version ...
342 lines
7.7 KiB
C++
342 lines
7.7 KiB
C++
/////////////////////////////////////////////////////////////////////////
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// $Id: data_xfer32.cc,v 1.21 2002-10-25 18:26:27 sshwarts Exp $
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/////////////////////////////////////////////////////////////////////////
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//
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// Copyright (C) 2001 MandrakeSoft S.A.
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//
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// MandrakeSoft S.A.
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// 43, rue d'Aboukir
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// 75002 Paris - France
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// http://www.linux-mandrake.com/
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// http://www.mandrakesoft.com/
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//
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// This library is free software; you can redistribute it and/or
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// modify it under the terms of the GNU Lesser General Public
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// License as published by the Free Software Foundation; either
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// version 2 of the License, or (at your option) any later version.
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//
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// This library is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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// Lesser General Public License for more details.
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//
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// You should have received a copy of the GNU Lesser General Public
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// License along with this library; if not, write to the Free Software
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// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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#define NEED_CPU_REG_SHORTCUTS 1
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#include "bochs.h"
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#define LOG_THIS BX_CPU_THIS_PTR
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void
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BX_CPU_C::XCHG_ERXEAX(bxInstruction_c *i)
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{
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Bit32u temp32;
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temp32 = EAX;
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#if BX_SUPPORT_X86_64
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RAX = BX_CPU_THIS_PTR gen_reg[i->opcodeReg()].dword.erx;
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BX_CPU_THIS_PTR gen_reg[i->opcodeReg()].dword.erx = temp32;
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#else
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EAX = BX_CPU_THIS_PTR gen_reg[i->opcodeReg()].dword.erx;
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BX_CPU_THIS_PTR gen_reg[i->opcodeReg()].dword.erx = temp32;
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#endif
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}
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void
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BX_CPU_C::MOV_ERXId(bxInstruction_c *i)
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{
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#if BX_SUPPORT_X86_64
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BX_CPU_THIS_PTR gen_reg[i->opcodeReg()].rrx = i->Id();
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#else
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BX_CPU_THIS_PTR gen_reg[i->opcodeReg()].dword.erx = i->Id();
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#endif
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}
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void
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BX_CPU_C::MOV_EEdGd(bxInstruction_c *i)
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{
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Bit32u op2_32;
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op2_32 = BX_READ_32BIT_REG(i->nnn());
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write_virtual_dword(i->seg(), RMAddr(i), &op2_32);
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}
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void
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BX_CPU_C::MOV_EGdGd(bxInstruction_c *i)
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{
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Bit32u op2_32;
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op2_32 = BX_READ_32BIT_REG(i->nnn());
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BX_WRITE_32BIT_REGZ(i->rm(), op2_32);
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}
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void
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BX_CPU_C::MOV_GdEGd(bxInstruction_c *i)
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{
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// 2nd modRM operand Ex, is known to be a general register Gd.
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Bit32u op2_32;
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op2_32 = BX_READ_32BIT_REG(i->rm());
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BX_WRITE_32BIT_REGZ(i->nnn(), op2_32);
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}
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void
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BX_CPU_C::MOV_GdEEd(bxInstruction_c *i)
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{
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// 2nd modRM operand Ex, is known to be a memory operand, Ed.
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Bit32u op2_32;
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read_virtual_dword(i->seg(), RMAddr(i), &op2_32);
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BX_WRITE_32BIT_REGZ(i->nnn(), op2_32);
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}
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void
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BX_CPU_C::LEA_GdM(bxInstruction_c *i)
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{
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if (i->modC0()) {
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BX_PANIC(("LEA_GvM: op2 is a register"));
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UndefinedOpcode(i);
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return;
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}
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/* write effective address of op2 in op1 */
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BX_WRITE_32BIT_REGZ(i->nnn(), RMAddr(i));
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}
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void
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BX_CPU_C::MOV_EAXOd(bxInstruction_c *i)
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{
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Bit32u temp_32;
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bx_address addr;
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addr = i->Id();
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/* read from memory address */
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if (!BX_NULL_SEG_REG(i->seg())) {
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read_virtual_dword(i->seg(), addr, &temp_32);
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}
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else {
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read_virtual_dword(BX_SEG_REG_DS, addr, &temp_32);
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}
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/* write to register */
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#if BX_SUPPORT_X86_64
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RAX = temp_32;
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#else
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EAX = temp_32;
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#endif
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}
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void
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BX_CPU_C::MOV_OdEAX(bxInstruction_c *i)
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{
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Bit32u temp_32;
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bx_address addr;
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addr = i->Id();
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/* read from register */
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temp_32 = EAX;
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/* write to memory address */
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if (!BX_NULL_SEG_REG(i->seg())) {
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write_virtual_dword(i->seg(), addr, &temp_32);
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}
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else {
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write_virtual_dword(BX_SEG_REG_DS, addr, &temp_32);
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}
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}
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void
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BX_CPU_C::MOV_EdId(bxInstruction_c *i)
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{
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Bit32u op2_32;
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op2_32 = i->Id();
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/* now write sum back to destination */
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if (i->modC0()) {
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BX_WRITE_32BIT_REGZ(i->rm(), op2_32);
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}
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else {
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write_virtual_dword(i->seg(), RMAddr(i), &op2_32);
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}
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}
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void
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BX_CPU_C::MOVZX_GdEb(bxInstruction_c *i)
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{
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#if BX_CPU_LEVEL < 3
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BX_PANIC(("MOVZX_GvEb: not supported on < 386"));
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#else
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Bit8u op2_8;
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if (i->modC0()) {
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op2_8 = BX_READ_8BIT_REGx(i->rm(),i->extend8bitL());
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}
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else {
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/* pointer, segment address pair */
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read_virtual_byte(i->seg(), RMAddr(i), &op2_8);
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}
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/* zero extend byte op2 into dword op1 */
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BX_WRITE_32BIT_REGZ(i->nnn(), (Bit32u) op2_8);
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#endif /* BX_CPU_LEVEL < 3 */
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}
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void
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BX_CPU_C::MOVZX_GdEw(bxInstruction_c *i)
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{
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#if BX_CPU_LEVEL < 3
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BX_PANIC(("MOVZX_GvEw: not supported on < 386"));
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#else
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Bit16u op2_16;
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if (i->modC0()) {
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op2_16 = BX_READ_16BIT_REG(i->rm());
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}
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else {
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/* pointer, segment address pair */
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read_virtual_word(i->seg(), RMAddr(i), &op2_16);
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}
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/* zero extend word op2 into dword op1 */
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BX_WRITE_32BIT_REGZ(i->nnn(), (Bit32u) op2_16);
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#endif /* BX_CPU_LEVEL < 3 */
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}
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void
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BX_CPU_C::MOVSX_GdEb(bxInstruction_c *i)
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{
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#if BX_CPU_LEVEL < 3
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BX_PANIC(("MOVSX_GvEb: not supported on < 386"));
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#else
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Bit8u op2_8;
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if (i->modC0()) {
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op2_8 = BX_READ_8BIT_REGx(i->rm(),i->extend8bitL());
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}
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else {
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/* pointer, segment address pair */
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read_virtual_byte(i->seg(), RMAddr(i), &op2_8);
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}
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/* sign extend byte op2 into dword op1 */
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BX_WRITE_32BIT_REGZ(i->nnn(), (Bit8s) op2_8);
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#endif /* BX_CPU_LEVEL < 3 */
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}
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void
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BX_CPU_C::MOVSX_GdEw(bxInstruction_c *i)
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{
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#if BX_CPU_LEVEL < 3
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BX_PANIC(("MOVSX_GvEw: not supported on < 386"));
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#else
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Bit16u op2_16;
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if (i->modC0()) {
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op2_16 = BX_READ_16BIT_REG(i->rm());
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}
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else {
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/* pointer, segment address pair */
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read_virtual_word(i->seg(), RMAddr(i), &op2_16);
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}
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/* sign extend word op2 into dword op1 */
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BX_WRITE_32BIT_REGZ(i->nnn(), (Bit16s) op2_16);
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#endif /* BX_CPU_LEVEL < 3 */
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}
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void
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BX_CPU_C::XCHG_EdGd(bxInstruction_c *i)
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{
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Bit32u op2_32, op1_32;
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/* op2_32 is a register, op2_addr is an index of a register */
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op2_32 = BX_READ_32BIT_REG(i->nnn());
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/* op1_32 is a register or memory reference */
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if (i->modC0()) {
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op1_32 = BX_READ_32BIT_REG(i->rm());
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BX_WRITE_32BIT_REGZ(i->rm(), op2_32);
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}
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else {
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/* pointer, segment address pair */
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read_RMW_virtual_dword(i->seg(), RMAddr(i), &op1_32);
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Write_RMW_virtual_dword(op2_32);
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}
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BX_WRITE_32BIT_REGZ(i->nnn(), op1_32);
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}
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void
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BX_CPU_C::CMOV_GdEd(bxInstruction_c *i)
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{
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#if (BX_CPU_LEVEL >= 6) || (BX_CPU_LEVEL_HACKED >= 6)
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// Note: CMOV accesses a memory source operand (read), regardless
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// of whether condition is true or not. Thus, exceptions may
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// occur even if the MOV does not take place.
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bx_bool condition;
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Bit32u op2_32;
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switch (i->b1()) {
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// CMOV opcodes:
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case 0x140: condition = get_OF(); break;
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case 0x141: condition = !get_OF(); break;
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case 0x142: condition = get_CF(); break;
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case 0x143: condition = !get_CF(); break;
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case 0x144: condition = get_ZF(); break;
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case 0x145: condition = !get_ZF(); break;
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case 0x146: condition = get_CF() || get_ZF(); break;
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case 0x147: condition = !get_CF() && !get_ZF(); break;
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case 0x148: condition = get_SF(); break;
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case 0x149: condition = !get_SF(); break;
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case 0x14A: condition = get_PF(); break;
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case 0x14B: condition = !get_PF(); break;
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case 0x14C: condition = getB_SF() != getB_OF(); break;
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case 0x14D: condition = getB_SF() == getB_OF(); break;
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case 0x14E: condition = get_ZF() || (getB_SF() != getB_OF()); break;
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case 0x14F: condition = !get_ZF() && (getB_SF() == getB_OF()); break;
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default:
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condition = 0;
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BX_PANIC(("CMOV_GdEd: default case"));
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}
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if (i->modC0()) {
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op2_32 = BX_READ_32BIT_REG(i->rm());
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}
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else {
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/* pointer, segment address pair */
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read_virtual_dword(i->seg(), RMAddr(i), &op2_32);
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}
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if (condition) {
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BX_WRITE_32BIT_REGZ(i->nnn(), op2_32);
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}
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#else
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BX_INFO(("cmov_gded called"));
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UndefinedOpcode(i);
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#endif
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}
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