153 lines
4.5 KiB
Plaintext
153 lines
4.5 KiB
Plaintext
----------------------------------------------------------------------
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Patch name: patch.tsc-zwane
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Author: Zwane Mwaikambo <zwane@linuxpower.ca>, Bryce Denney <bryce@tlw.com>
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Date: Tue, 24 Sep 2002 19:44:51 -0400 (EDT)
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Detailed description:
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Zwane's original comments:
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This patch will seperate the TSC from the other timers, this helps a lot
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in speeding up SMP boot and allows TSC synch to be possible. Seperation is
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definitely necessary for writing to the TSC (e.g. via WRMSR)
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Bryce's comments:
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I took Zwane's patch and modified it so that
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1) the TSCs for each cpu increment with ticks, not with ticks/COUNTER_INTERVAL
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2) updating the TSC values do not cost any time per instruction. The
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TSC value for each CPU is computed only when it is needed.
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Patch was created with:
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cvs diff -u
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Apply patch to what version:
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cvs checked out on DATE, release version VER
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Instructions:
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To patch, go to main bochs directory.
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Type "patch -p0 < THIS_PATCH_FILE".
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----------------------------------------------------------------------
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Index: cpu/cpu.h
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===================================================================
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RCS file: /cvsroot/bochs/bochs/cpu/cpu.h,v
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retrieving revision 1.78
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diff -u -r1.78 cpu.h
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--- cpu/cpu.h 24 Sep 2002 18:33:37 -0000 1.78
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+++ cpu/cpu.h 25 Sep 2002 02:59:01 -0000
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@@ -575,12 +575,18 @@
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typedef struct {
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Bit8u p5_mc_addr;
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Bit8u p5_mc_type;
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- Bit8u tsc;
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Bit8u cesr;
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Bit8u ctr0;
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Bit8u ctr1;
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Bit64u apicbase;
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+ // TSC: Time Stamp Counter
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+ // Instead of storing a counter and incrementing it every instruction, we
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+ // remember the time in ticks that it was reset to zero. With a little
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+ // algebra, we can also support setting it to something other than zero.
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+ // Don't read this directly; use get_tsc and set_tsc to access the TSC.
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+ Bit64u tsc_last_reset_time;
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+
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#if BX_SUPPORT_X86_64
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// x86-64 EFER bits
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Boolean sce;
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@@ -1386,6 +1392,10 @@
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#if BX_CPU_LEVEL >= 5
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bx_regs_msr_t msr;
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+
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+ // these methods are implemented in proc_ctrl.cc
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+ Bit64u get_TSC ();
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+ void set_TSC (Bit64u newval);
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#endif
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i387_t the_i387;
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Index: cpu/init.cc
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===================================================================
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RCS file: /cvsroot/bochs/bochs/cpu/init.cc,v
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retrieving revision 1.32
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diff -u -r1.32 init.cc
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--- cpu/init.cc 22 Sep 2002 18:22:24 -0000 1.32
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+++ cpu/init.cc 25 Sep 2002 02:59:02 -0000
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@@ -818,6 +818,9 @@
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/* initialise MSR registers to defaults */
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#if BX_CPU_LEVEL >= 5
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+ // initialize tsc to zero
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+ BX_CPU_THIS_PTR set_TSC (0);
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+
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/* APIC Address, APIC enabled and BSP is default, we'll fill in the rest later */
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BX_CPU_THIS_PTR msr.apicbase = (APIC_BASE_ADDR << 12) + 0x900;
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#if BX_SUPPORT_X86_64
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Index: cpu/proc_ctrl.cc
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===================================================================
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RCS file: /cvsroot/bochs/bochs/cpu/proc_ctrl.cc,v
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retrieving revision 1.50
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diff -u -r1.50 proc_ctrl.cc
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--- cpu/proc_ctrl.cc 24 Sep 2002 13:57:37 -0000 1.50
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+++ cpu/proc_ctrl.cc 25 Sep 2002 02:59:04 -0000
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@@ -1644,6 +1644,20 @@
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#endif
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}
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+
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+
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+Bit64u BX_CPU_C::get_TSC () {
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+ return bx_pc_system.time_ticks() - BX_CPU_THIS_PTR msr.tsc_last_reset_time;
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+}
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+
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+void BX_CPU_C::set_TSC (Bit64u newval) {
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+ // compute the correct setting of tsc_last_reset_time so that a get_TSC()
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+ // will return newval.
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+ BX_CPU_THIS_PTR msr.tsc_last_reset_time = bx_pc_system.time_ticks() - newval;
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+ // verify
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+ BX_ASSERT (get_TSC() == newval);
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+}
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+
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void
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BX_CPU_C::RDTSC(bxInstruction_c *i)
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{
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@@ -1652,9 +1666,10 @@
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Boolean cpl = CPL;
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if ((tsd==0) || (tsd==1 && cpl==0)) {
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// return ticks
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- Bit64u ticks = bx_pc_system.time_ticks ();
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+ Bit64u ticks = BX_CPU_THIS_PTR get_TSC ();
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RAX = (Bit32u) (ticks & 0xffffffff);
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- RDX = (Bit32u) ((ticks >> 32) & 0xffffffff);
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+ RDX = (Bit32u) (ticks >> 32);
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+
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//BX_INFO(("RDTSC: returning EDX:EAX = %08x:%08x", EDX, EAX));
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} else {
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// not allowed to use RDTSC!
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@@ -1812,7 +1827,6 @@
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/* The following registers are defined for Pentium only */
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case BX_MSR_P5_MC_ADDR:
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case BX_MSR_MC_TYPE:
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- case BX_MSR_TSC:
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case BX_MSR_CESR:
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/* TODO */
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return;
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@@ -1820,7 +1834,6 @@
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/* These are noops on i686... */
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case BX_MSR_P5_MC_ADDR:
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case BX_MSR_MC_TYPE:
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- case BX_MSR_TSC:
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/* do nothing */
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return;
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@@ -1830,6 +1843,12 @@
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case BX_MSR_CTR1:
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goto do_exception;
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#endif /* BX_CPU_LEVEL == 5 */
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+
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+ case BX_MSR_TSC:
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+ /* we ignore the high 32bits */
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+ BX_CPU_THIS_PTR set_TSC (RAX & 0xffffffff);
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+ BX_INFO(("WRMSR: wrote %08x:%08x to MSR_TSC\n", 0, EAX));
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+ return;
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/* MSR_APICBASE
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0:7 Reserved
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