280 lines
6.5 KiB
C++
280 lines
6.5 KiB
C++
// Copyright (C) 2000 MandrakeSoft S.A.
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//
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// MandrakeSoft S.A.
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// 43, rue d'Aboukir
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// 75002 Paris - France
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// http://www.linux-mandrake.com/
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// http://www.mandrakesoft.com/
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//
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// This library is free software; you can redistribute it and/or
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// modify it under the terms of the GNU Lesser General Public
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// License as published by the Free Software Foundation; either
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// version 2 of the License, or (at your option) any later version.
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//
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// This library is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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// Lesser General Public License for more details.
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//
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// You should have received a copy of the GNU Lesser General Public
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// License along with this library; if not, write to the Free Software
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// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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#include "bochs.h"
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void
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BX_CPU_C::MUL_EAXEd(BxInstruction_t *i)
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{
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Bit32u op1_32, op2_32, product_32h, product_32l;
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Bit64u product_64;
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Boolean temp_flag;
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op1_32 = EAX;
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/* op2 is a register or memory reference */
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if (i->mod == 0xc0) {
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op2_32 = BX_READ_32BIT_REG(i->rm);
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}
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else {
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/* pointer, segment address pair */
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read_virtual_dword(i->seg, i->rm_addr, &op2_32);
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}
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product_64 = ((Bit64u) op1_32) * ((Bit64u) op2_32);
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product_32l = (Bit32u) (product_64 & 0xFFFFFFFF);
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product_32h = (Bit32u) (product_64 >> 32);
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/* now write product back to destination */
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EAX = product_32l;
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EDX = product_32h;
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/* set eflags:
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* MUL affects the following flags: C,O
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*/
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temp_flag = (product_32h != 0);
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SET_FLAGS_OxxxxC(temp_flag, temp_flag);
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}
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void
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BX_CPU_C::IMUL_EAXEd(BxInstruction_t *i)
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{
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Bit32s op1_32, op2_32;
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Bit64s product_64;
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Bit32u product_32h, product_32l;
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op1_32 = EAX;
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/* op2 is a register or memory reference */
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if (i->mod == 0xc0) {
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op2_32 = BX_READ_32BIT_REG(i->rm);
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}
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else {
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/* pointer, segment address pair */
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read_virtual_dword(i->seg, i->rm_addr, (Bit32u *) &op2_32);
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}
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product_64 = ((Bit64s) op1_32) * ((Bit64s) op2_32);
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product_32l = (Bit32u) (product_64 & 0xFFFFFFFF);
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product_32h = (Bit32u) (product_64 >> 32);
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/* now write product back to destination */
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EAX = product_32l;
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EDX = product_32h;
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/* set eflags:
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* IMUL affects the following flags: C,O
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* IMUL r/m16: condition for clearing CF & OF:
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* EDX:EAX = sign-extend of EAX
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*/
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if ( (EDX==0xffffffff) && (EAX & 0x80000000) ) {
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SET_FLAGS_OxxxxC(0, 0);
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}
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else if ( (EDX==0x00000000) && (EAX < 0x80000000) ) {
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SET_FLAGS_OxxxxC(0, 0);
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}
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else {
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SET_FLAGS_OxxxxC(1, 1);
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}
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}
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void
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BX_CPU_C::DIV_EAXEd(BxInstruction_t *i)
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{
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Bit32u op2_32, remainder_32, quotient_32l;
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Bit64u op1_64, quotient_64;
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op1_64 = (((Bit64u) EDX) << 32) + ((Bit64u) EAX);
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/* op2 is a register or memory reference */
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if (i->mod == 0xc0) {
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op2_32 = BX_READ_32BIT_REG(i->rm);
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}
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else {
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/* pointer, segment address pair */
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read_virtual_dword(i->seg, i->rm_addr, &op2_32);
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}
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if (op2_32 == 0) {
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exception(BX_DE_EXCEPTION, 0, 0);
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}
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quotient_64 = op1_64 / op2_32;
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remainder_32 = (Bit32u) (op1_64 % op2_32);
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quotient_32l = (Bit32u) (quotient_64 & 0xFFFFFFFF);
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if (quotient_64 != quotient_32l) {
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exception(BX_DE_EXCEPTION, 0, 0);
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}
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/* set EFLAGS:
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* DIV affects the following flags: O,S,Z,A,P,C are undefined
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*/
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/* now write quotient back to destination */
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EAX = quotient_32l;
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EDX = remainder_32;
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}
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void
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BX_CPU_C::IDIV_EAXEd(BxInstruction_t *i)
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{
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Bit32s op2_32, remainder_32, quotient_32l;
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Bit64s op1_64, quotient_64;
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op1_64 = (((Bit64u) EDX) << 32) | ((Bit64u) EAX);
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/* op2 is a register or memory reference */
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if (i->mod == 0xc0) {
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op2_32 = BX_READ_32BIT_REG(i->rm);
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}
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else {
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/* pointer, segment address pair */
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read_virtual_dword(i->seg, i->rm_addr, (Bit32u *) &op2_32);
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}
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if (op2_32 == 0) {
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exception(BX_DE_EXCEPTION, 0, 0);
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}
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quotient_64 = op1_64 / op2_32;
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remainder_32 = (Bit32s) (op1_64 % op2_32);
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quotient_32l = (Bit32s) (quotient_64 & 0xFFFFFFFF);
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if (quotient_64 != quotient_32l) {
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exception(BX_DE_EXCEPTION, 0, 0);
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}
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/* set EFLAGS:
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* IDIV affects the following flags: O,S,Z,A,P,C are undefined
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*/
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/* now write quotient back to destination */
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EAX = quotient_32l;
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EDX = remainder_32;
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}
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void
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BX_CPU_C::IMUL_GdEdId(BxInstruction_t *i)
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{
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#if BX_CPU_LEVEL < 2
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bx_panic("IMUL_GdEdId() unsupported on 8086!\n");
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#else
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Bit32s op2_32, op3_32, product_32;
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Bit64s product_64;
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op3_32 = i->Id;
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/* op2 is a register or memory reference */
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if (i->mod == 0xc0) {
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op2_32 = BX_READ_32BIT_REG(i->rm);
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}
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else {
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/* pointer, segment address pair */
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read_virtual_dword(i->seg, i->rm_addr, (Bit32u *) &op2_32);
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}
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product_32 = op2_32 * op3_32;
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product_64 = ((Bit64s) op2_32) * ((Bit64s) op3_32);
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/* now write product back to destination */
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BX_WRITE_32BIT_REG(i->nnn, product_32);
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/* set eflags:
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* IMUL affects the following flags: C,O
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* IMUL r16,r/m16,imm16: condition for clearing CF & OF:
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* result exactly fits within r16
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*/
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if (product_64 == product_32) {
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SET_FLAGS_OxxxxC(0, 0);
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}
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else {
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SET_FLAGS_OxxxxC(1, 1);
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}
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#endif
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}
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void
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BX_CPU_C::IMUL_GdEd(BxInstruction_t *i)
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{
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#if BX_CPU_LEVEL < 3
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bx_panic("IMUL_GvEv() unsupported on 8086!\n");
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#else
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Bit32s op1_32, op2_32, product_32;
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Bit64s product_64;
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/* op2 is a register or memory reference */
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if (i->mod == 0xc0) {
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op2_32 = BX_READ_32BIT_REG(i->rm);
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}
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else {
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/* pointer, segment address pair */
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read_virtual_dword(i->seg, i->rm_addr, (Bit32u *) &op2_32);
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}
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op1_32 = BX_READ_32BIT_REG(i->nnn);
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product_32 = op1_32 * op2_32;
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product_64 = ((Bit64s) op1_32) * ((Bit64s) op2_32);
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/* now write product back to destination */
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BX_WRITE_32BIT_REG(i->nnn, product_32);
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/* set eflags:
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* IMUL affects the following flags: C,O
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* IMUL r16,r/m16,imm16: condition for clearing CF & OF:
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* result exactly fits within r16
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*/
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if (product_64 == product_32) {
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SET_FLAGS_OxxxxC(0, 0);
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}
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else {
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SET_FLAGS_OxxxxC(1, 1);
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}
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#endif
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}
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