473 lines
13 KiB
C++
473 lines
13 KiB
C++
/////////////////////////////////////////////////////////////////////////
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// $Id: pci.cc,v 1.25 2002-11-14 20:02:57 vruppert Exp $
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/////////////////////////////////////////////////////////////////////////
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//
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// Copyright (C) 2002 MandrakeSoft S.A.
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//
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// MandrakeSoft S.A.
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// 43, rue d'Aboukir
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// 75002 Paris - France
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// http://www.linux-mandrake.com/
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// http://www.mandrakesoft.com/
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//
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// This library is free software; you can redistribute it and/or
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// modify it under the terms of the GNU Lesser General Public
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// License as published by the Free Software Foundation; either
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// version 2 of the License, or (at your option) any later version.
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//
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// This library is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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// Lesser General Public License for more details.
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//
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// You should have received a copy of the GNU Lesser General Public
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// License along with this library; if not, write to the Free Software
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// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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//
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// i440FX Support - PMC/DBX
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//
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// Define BX_PLUGGABLE in files that can be compiled into plugins. For
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// platforms that require a special tag on exported symbols, BX_PLUGGABLE
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// is used to know when we are exporting symbols and when we are importing.
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#define BX_PLUGGABLE
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#include "bochs.h"
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#define LOG_THIS thePciBridge->
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bx_pci_c *thePciBridge = NULL;
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int
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libpci_LTX_plugin_init(plugin_t *plugin, plugintype_t type, int argc, char *argv[])
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{
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thePciBridge = new bx_pci_c ();
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bx_devices.pluginPciBridge = thePciBridge;
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BX_REGISTER_DEVICE_DEVMODEL(plugin, type, thePciBridge, BX_PLUGIN_PCI);
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return(0); // Success
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}
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void
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libpci_LTX_plugin_fini(void)
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{
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}
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bx_pci_c::bx_pci_c(void)
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{
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put("PCI");
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settype(PCILOG);
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}
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bx_pci_c::~bx_pci_c(void)
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{
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// nothing for now
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BX_DEBUG(("Exit."));
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}
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void
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bx_pci_c::init(void)
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{
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// called once when bochs initializes
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BX_PCI_THIS num_pci_handles = 0;
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/* set unused elements to appropriate values */
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for (unsigned i=0; i < BX_MAX_PCI_DEVICES; i++) {
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BX_PCI_THIS pci_handler[i].read = NULL;
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BX_PCI_THIS pci_handler[i].write = NULL;
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}
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for (unsigned i=0; i < 0x100; i++) {
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BX_PCI_THIS pci_handler_id[i] = BX_MAX_PCI_DEVICES; // not assigned
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}
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DEV_register_ioread_handler(this, read_handler, 0x0CF8, "i440FX", 4);
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for (unsigned i=0x0CFC; i<=0x0CFF; i++) {
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DEV_register_ioread_handler(this, read_handler, i, "i440FX", 7);
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}
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DEV_register_iowrite_handler(this, write_handler, 0x0CF8, "i440FX", 4);
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for (unsigned i=0x0CFC; i<=0x0CFF; i++) {
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DEV_register_iowrite_handler(this, write_handler, i, "i440FX", 7);
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}
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DEV_register_pci_handlers(this, pci_read_handler, pci_write_handler,
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0x00, "440FX Host bridge");
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for (unsigned i=0; i<256; i++)
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BX_PCI_THIS s.i440fx.pci_conf[i] = 0x0;
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// readonly registers
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BX_PCI_THIS s.i440fx.pci_conf[0x00] = 0x86;
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BX_PCI_THIS s.i440fx.pci_conf[0x01] = 0x80;
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BX_PCI_THIS s.i440fx.pci_conf[0x02] = 0x37;
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BX_PCI_THIS s.i440fx.pci_conf[0x03] = 0x12;
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BX_PCI_THIS s.i440fx.pci_conf[0x0b] = 0x06;
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}
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void
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bx_pci_c::reset(unsigned type)
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{
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BX_PCI_THIS s.i440fx.confAddr = 0;
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BX_PCI_THIS s.i440fx.confData = 0;
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BX_PCI_THIS s.i440fx.pci_conf[0x04] = 0x06;
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BX_PCI_THIS s.i440fx.pci_conf[0x05] = 0x00;
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BX_PCI_THIS s.i440fx.pci_conf[0x06] = 0x80;
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BX_PCI_THIS s.i440fx.pci_conf[0x07] = 0x02;
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BX_PCI_THIS s.i440fx.pci_conf[0x0d] = 0x00;
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BX_PCI_THIS s.i440fx.pci_conf[0x0f] = 0x00;
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BX_PCI_THIS s.i440fx.pci_conf[0x50] = 0x00;
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BX_PCI_THIS s.i440fx.pci_conf[0x51] = 0x01;
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BX_PCI_THIS s.i440fx.pci_conf[0x52] = 0x00;
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BX_PCI_THIS s.i440fx.pci_conf[0x53] = 0x80;
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BX_PCI_THIS s.i440fx.pci_conf[0x54] = 0x00;
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BX_PCI_THIS s.i440fx.pci_conf[0x55] = 0x00;
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BX_PCI_THIS s.i440fx.pci_conf[0x56] = 0x00;
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BX_PCI_THIS s.i440fx.pci_conf[0x57] = 0x01;
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BX_PCI_THIS s.i440fx.pci_conf[0x58] = 0x10;
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for (unsigned i=0x59; i<0x60; i++)
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BX_PCI_THIS s.i440fx.pci_conf[i] = 0x00;
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}
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// static IO port read callback handler
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// redirects to non-static class handler to avoid virtual functions
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Bit32u
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bx_pci_c::read_handler(void *this_ptr, Bit32u address, unsigned io_len)
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{
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#if !BX_USE_PCI_SMF
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bx_pci_c *class_ptr = (bx_pci_c *) this_ptr;
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return( class_ptr->read(address, io_len) );
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}
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Bit32u
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bx_pci_c::read(Bit32u address, unsigned io_len)
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{
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#else
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UNUSED(this_ptr);
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#endif // !BX_USE_PCI_SMF
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switch (address) {
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case 0x0CF8:
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{
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if (io_len == 4) {
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return BX_PCI_THIS s.i440fx.confAddr;
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}
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else {
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return 0xFFFF;
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}
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}
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break;
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case 0x0CFC:
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case 0x0CFD:
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case 0x0CFE:
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case 0x0CFF:
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{
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Bit32u handle, retval;
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Bit8u devfunc, regnum;
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if ((BX_PCI_THIS s.i440fx.confAddr & 0x80FF0000) == 0x80000000) {
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devfunc = (BX_PCI_THIS s.i440fx.confAddr >> 8) & 0xff;
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regnum = (BX_PCI_THIS s.i440fx.confAddr & 0xfc) + (address & 0x03);
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handle = BX_PCI_THIS pci_handler_id[devfunc];
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if ((io_len <= 4) && (handle < BX_MAX_PCI_DEVICES))
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retval = (* BX_PCI_THIS pci_handler[handle].read)
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(BX_PCI_THIS pci_handler[handle].this_ptr, regnum, io_len);
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else
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retval = 0xFFFFFFFF;
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}
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else
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retval = 0xFFFFFFFF;
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BX_PCI_THIS s.i440fx.confData = retval;
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return retval;
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}
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}
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BX_PANIC(("unsupported IO read to port 0x%x",
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(unsigned) address));
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return(0xffffffff);
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}
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// static IO port write callback handler
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// redirects to non-static class handler to avoid virtual functions
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void
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bx_pci_c::write_handler(void *this_ptr, Bit32u address, Bit32u value, unsigned io_len)
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{
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#if !BX_USE_PCI_SMF
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bx_pci_c *class_ptr = (bx_pci_c *) this_ptr;
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class_ptr->write(address, value, io_len);
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}
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void
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bx_pci_c::write(Bit32u address, Bit32u value, unsigned io_len)
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{
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#else
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UNUSED(this_ptr);
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#endif // !BX_USE_PCI_SMF
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switch (address) {
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case 0xCF8:
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{
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// confAddr accepts a dword value only
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if (io_len == 4) {
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BX_PCI_THIS s.i440fx.confAddr = value;
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if ((value & 0x80FFFF00) == 0x80000000) {
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BX_DEBUG(("440FX PMC register 0x%02x selected", value & 0xfc));
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}
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else if ((value & 0x80000000) == 0x80000000) {
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BX_DEBUG(("440FX request for bus 0x%02x device 0x%02x function 0x%02x",
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(value >> 16) & 0xFF, (value >> 11) & 0x1F, (value >> 8) & 0x07));
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}
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}
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}
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break;
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case 0xCFC:
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case 0xCFD:
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case 0xCFE:
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case 0xCFF:
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{
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Bit32u handle;
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Bit8u devfunc, regnum;
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if ((BX_PCI_THIS s.i440fx.confAddr & 0x80FF0000) == 0x80000000) {
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devfunc = (BX_PCI_THIS s.i440fx.confAddr >> 8) & 0xff;
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regnum = (BX_PCI_THIS s.i440fx.confAddr & 0xfc) + (address & 0x03);
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handle = BX_PCI_THIS pci_handler_id[devfunc];
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if ((io_len <= 4) && (handle < BX_MAX_PCI_DEVICES)) {
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if (((regnum>=4) && (regnum<=7)) || (regnum==12) || (regnum==13) || (regnum>14)) {
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(* BX_PCI_THIS pci_handler[handle].write)
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(BX_PCI_THIS pci_handler[handle].this_ptr, regnum, value, io_len);
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BX_PCI_THIS s.i440fx.confData = value << (8 * (address & 0x03));
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}
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else
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BX_DEBUG(("read only register, write ignored"));
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}
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}
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}
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break;
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default:
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BX_PANIC(("IO write to port 0x%x", (unsigned) address));
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}
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}
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// static pci configuration space read callback handler
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// redirects to non-static class handler to avoid virtual functions
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Bit32u
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bx_pci_c::pci_read_handler(void *this_ptr, Bit8u address, unsigned io_len)
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{
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#if !BX_USE_PCI_SMF
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bx_pci_c *class_ptr = (bx_pci_c *) this_ptr;
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return( class_ptr->pci_read(address, io_len) );
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}
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Bit32u
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bx_pci_c::pci_read(Bit8u address, unsigned io_len)
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{
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#else
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UNUSED(this_ptr);
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#endif // !BX_USE_PCI_SMF
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Bit32u val440fx = 0;
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if (io_len <= 4) {
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for (unsigned i=0; i<io_len; i++) {
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val440fx |= (BX_PCI_THIS s.i440fx.pci_conf[address+i] << (i*8));
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}
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BX_DEBUG(("440FX PMC read register 0x%02x value 0x%08x", address, val440fx));
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return val440fx;
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}
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else
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return(0xffffffff);
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}
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// static pci configuration space write callback handler
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// redirects to non-static class handler to avoid virtual functions
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void
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bx_pci_c::pci_write_handler(void *this_ptr, Bit8u address, Bit32u value, unsigned io_len)
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{
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#if !BX_USE_PCI_SMF
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bx_pci_c *class_ptr = (bx_pci_c *) this_ptr;
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class_ptr->pci_write(address, value, io_len);
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}
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void
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bx_pci_c::pci_write(Bit8u address, Bit32u value, unsigned io_len)
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{
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#else
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UNUSED(this_ptr);
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#endif // !BX_USE_PCI_SMF
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Bit8u value8;
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if (io_len <= 4) {
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for (unsigned i=0; i<io_len; i++) {
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value8 = (value >> (i*8)) & 0xFF;
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switch (address+i) {
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case 0x06:
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case 0x0c:
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break;
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default:
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BX_PCI_THIS s.i440fx.pci_conf[address+i] = value8;
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BX_DEBUG(("440FX PMC write register 0x%02x value 0x%02x", address,
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value8));
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}
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}
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}
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}
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Bit8u
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bx_pci_c::rd_memType (Bit32u addr)
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{
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switch ((addr & 0xFC000) >> 12) {
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case 0xC0:
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return (BX_PCI_THIS s.i440fx.pci_conf[0x5A] & 0x1);
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case 0xC4:
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return ( (BX_PCI_THIS s.i440fx.pci_conf[0x5A] >> 4) & 0x1);
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case 0xC8:
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return (BX_PCI_THIS s.i440fx.pci_conf[0x5B] & 0x1);
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case 0xCC:
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return ( (BX_PCI_THIS s.i440fx.pci_conf[0x5B] >> 4) & 0x1);
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case 0xD0:
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return (BX_PCI_THIS s.i440fx.pci_conf[0x5C] & 0x1);
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case 0xD4:
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return ( (BX_PCI_THIS s.i440fx.pci_conf[0x5C] >> 4) & 0x1);
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case 0xD8:
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return (BX_PCI_THIS s.i440fx.pci_conf[0x5D] & 0x1);
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case 0xDC:
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return ( (BX_PCI_THIS s.i440fx.pci_conf[0x5D] >> 4) & 0x1);
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case 0xE0:
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return (BX_PCI_THIS s.i440fx.pci_conf[0x5E] & 0x1);
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case 0xE4:
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return ( (BX_PCI_THIS s.i440fx.pci_conf[0x5E] >> 4) & 0x1);
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case 0xE8:
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return (BX_PCI_THIS s.i440fx.pci_conf[0x5F] & 0x1);
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case 0xEC:
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return ( (BX_PCI_THIS s.i440fx.pci_conf[0x5F] >> 4) & 0x1);
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case 0xF0:
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case 0xF4:
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case 0xF8:
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case 0xFC:
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return ( (BX_PCI_THIS s.i440fx.pci_conf[0x59] >> 4) & 0x1);
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default:
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BX_PANIC(("rd_memType () Error: Memory Type not known !"));
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return(0); // keep compiler happy
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break;
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}
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}
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Bit8u
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bx_pci_c::wr_memType (Bit32u addr)
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{
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switch ((addr & 0xFC000) >> 12) {
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case 0xC0:
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return ( (BX_PCI_THIS s.i440fx.pci_conf[0x5A] >> 1) & 0x1);
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case 0xC4:
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return ( (BX_PCI_THIS s.i440fx.pci_conf[0x5A] >> 5) & 0x1);
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case 0xC8:
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return ( (BX_PCI_THIS s.i440fx.pci_conf[0x5B] >> 1) & 0x1);
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case 0xCC:
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return ( (BX_PCI_THIS s.i440fx.pci_conf[0x5B] >> 5) & 0x1);
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case 0xD0:
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return ( (BX_PCI_THIS s.i440fx.pci_conf[0x5C] >> 1) & 0x1);
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case 0xD4:
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return ( (BX_PCI_THIS s.i440fx.pci_conf[0x5C] >> 5) & 0x1);
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case 0xD8:
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return ( (BX_PCI_THIS s.i440fx.pci_conf[0x5D] >> 1) & 0x1);
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case 0xDC:
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return ( (BX_PCI_THIS s.i440fx.pci_conf[0x5D] >> 5) & 0x1);
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case 0xE0:
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return ( (BX_PCI_THIS s.i440fx.pci_conf[0x5E] >> 1) & 0x1);
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case 0xE4:
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return ( (BX_PCI_THIS s.i440fx.pci_conf[0x5E] >> 5) & 0x1);
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case 0xE8:
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return ( (BX_PCI_THIS s.i440fx.pci_conf[0x5F] >> 1) & 0x1);
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case 0xEC:
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return ( (BX_PCI_THIS s.i440fx.pci_conf[0x5F] >> 5) & 0x1);
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case 0xF0:
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case 0xF4:
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case 0xF8:
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case 0xFC:
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return ( (BX_PCI_THIS s.i440fx.pci_conf[0x59] >> 5) & 0x1);
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default:
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BX_PANIC(("wr_memType () Error: Memory Type not known !"));
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return(0); // keep compiler happy
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break;
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}
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}
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void
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bx_pci_c::print_i440fx_state()
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{
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int i;
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BX_DEBUG(( "i440fxConfAddr:0x%08x", BX_PCI_THIS s.i440fx.confAddr ));
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BX_DEBUG(( "i440fxConfData:0x%08x", BX_PCI_THIS s.i440fx.confData ));
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#ifdef DUMP_FULL_I440FX
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for (i=0; i<256; i++) {
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BX_DEBUG(( "i440fxArray%02x:0x%02x", i, BX_PCI_THIS s.i440fx.pci_conf[i] ));
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}
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#else /* DUMP_FULL_I440FX */
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for (i=0x59; i<0x60; i++) {
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BX_DEBUG(( "i440fxArray%02x:0x%02x", i, BX_PCI_THIS s.i440fx.pci_conf[i] ));
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}
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#endif /* DUMP_FULL_I440FX */
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}
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bx_bool
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bx_pci_c::register_pci_handlers( void *this_ptr, bx_pci_read_handler_t f1,
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bx_pci_write_handler_t f2, Bit8u devfunc,
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const char *name)
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{
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unsigned handle;
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/* first check if device/function is available */
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if (BX_PCI_THIS pci_handler_id[devfunc] == BX_MAX_PCI_DEVICES) {
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if (BX_PCI_THIS num_pci_handles >= BX_MAX_PCI_DEVICES) {
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BX_INFO(("too many PCI devices installed."));
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BX_PANIC((" try increasing BX_MAX_PCI_DEVICES"));
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return false;
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}
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handle = BX_PCI_THIS num_pci_handles++;
|
|
BX_PCI_THIS pci_handler[handle].read = f1;
|
|
BX_PCI_THIS pci_handler[handle].write = f2;
|
|
BX_PCI_THIS pci_handler[handle].this_ptr = this_ptr;
|
|
BX_PCI_THIS pci_handler_id[devfunc] = handle;
|
|
BX_INFO(("%s present at device %d, function %d", name, devfunc >> 3,
|
|
devfunc & 0x07));
|
|
return true; // device/function mapped successfully
|
|
}
|
|
else {
|
|
return false; // device/function not available, return false.
|
|
}
|
|
}
|