554 lines
13 KiB
C
554 lines
13 KiB
C
/*---------------------------------------------------------------------------+
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| errors.c |
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| $Id: errors.c,v 1.18 2004-03-06 13:33:11 sshwarts Exp $
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| The error handling functions for wm-FPU-emu |
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| Copyright (C) 1992,1993,1994,1996 |
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| W. Metzenthen, 22 Parker St, Ormond, Vic 3163, Australia |
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| E-mail billm@jacobi.maths.monash.edu.au |
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+---------------------------------------------------------------------------*/
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/*---------------------------------------------------------------------------+
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| Note: |
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| The file contains code which accesses user memory. |
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| Emulator static data may change when user memory is accessed, due to |
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| other processes using the emulator while swapping is in progress. |
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+---------------------------------------------------------------------------*/
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#include <linux/signal.h>
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#include <stdio.h>
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#include "fpu_emu.h"
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#include "fpu_system.h"
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#include "exception.h"
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#include "status_w.h"
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#include "control_w.h"
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#include "reg_constant.h"
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#ifdef __cplusplus
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extern "C"
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#endif
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int printk(const char * fmt, ...);
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/*
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Called for opcodes which are illegal and which are known to result in a
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SIGILL with a real 80486.
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*/
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void FPU_illegal(void)
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{
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math_abort(NULL, SIGILL);
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}
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static struct {
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int type;
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const char *name;
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} exception_names[] = {
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{ EX_StackOver, "stack overflow" },
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{ EX_StackUnder, "stack underflow" },
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{ EX_Precision, "loss of precision" },
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{ EX_Underflow, "underflow" },
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{ EX_Overflow, "overflow" },
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{ EX_ZeroDiv, "divide by zero" },
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{ EX_Denormal, "denormalized operand" },
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{ EX_Invalid, "invalid operation" },
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{ 0, NULL }
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};
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/*
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EX_INTERNAL is always given with a code which indicates where the
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error was detected.
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Internal error types:
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0x14 in fpu_etc.c
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0x1nn in a *.c file:
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0x101 in reg_add_sub.c
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0x102 in reg_mul.c
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0x104 in poly_atan.c
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0x105 in reg_mul.c
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0x107 in fpu_trig.c
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0x108 in reg_compare.c
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0x109 in reg_compare.c
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0x110 in reg_add_sub.c
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0x111 in fpe_entry.c
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0x112 in fpu_trig.c
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0x113 in errors.c
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0x115 in fpu_trig.c
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0x116 in fpu_trig.c
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0x117 in fpu_trig.c
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0x118 in fpu_trig.c
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0x119 in fpu_trig.c
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0x120 in poly_atan.c
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0x121 in reg_compare.c
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0x122 in reg_compare.c
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0x123 in reg_compare.c
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0x125 in fpu_trig.c
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0x126 in fpu_entry.c
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0x127 in poly_2xm1.c
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0x128 in fpu_entry.c
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0x129 in fpu_entry.c
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0x130 in get_address.c
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0x131 in get_address.c
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0x132 in get_address.c
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0x133 in get_address.c
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0x140 in load_store.c
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0x141 in load_store.c
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0x150 in poly_sin.c
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0x151 in poly_sin.c
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0x160 in reg_ld_str.c
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0x161 in reg_ld_str.c
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0x162 in reg_ld_str.c
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0x163 in reg_ld_str.c
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0x164 in reg_ld_str.c
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0x170 in fpu_tags.c
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0x171 in fpu_tags.c
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0x172 in fpu_tags.c
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0x180 in reg_convert.c
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*/
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void FPU_internal(int type)
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{
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printk("FPU emulator: Internal error type 0x%04x\n", type);
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}
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void FPU_exception(int exception)
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{
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/* Extract only the bits which we use to set the status word */
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exception &= (SW_Exc_Mask);
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/* Set the corresponding exception bit */
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FPU_partial_status |= exception;
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/* Set summary bits iff exception isn't masked */
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if (FPU_partial_status & ~FPU_control_word & CW_Exceptions)
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FPU_partial_status |= (SW_Summary | SW_Backward);
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if (exception & (SW_Stack_Fault | EX_Precision))
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{
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if (!(exception & SW_C1))
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/* This bit distinguishes over- from underflow for a stack fault,
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and roundup from round-down for precision loss. */
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FPU_partial_status &= ~SW_C1;
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}
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}
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/* Real operation attempted on a NaN. */
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/* Returns < 0 if the exception is unmasked */
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int real_1op_NaN(FPU_REG *a)
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{
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int signalling, isNaN;
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isNaN = (exponent(a) == EXP_OVER) && (a->sigh & 0x80000000);
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/* The default result for the case of two "equal" NaNs (signs may
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differ) is chosen to reproduce 80486 behaviour */
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signalling = isNaN && !(a->sigh & 0x40000000);
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if (!signalling)
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{
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if (!isNaN) /* pseudo-NaN, or other unsupported? */
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{
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if (FPU_control_word & CW_Invalid)
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{
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/* Masked response */
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reg_copy(&CONST_QNaN, a);
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}
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EXCEPTION(EX_Invalid);
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return (!(FPU_control_word & CW_Invalid) ? FPU_Exception : 0) | TAG_Special;
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}
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return TAG_Special;
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}
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if (FPU_control_word & CW_Invalid)
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{
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/* The masked response */
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if (!(a->sigh & 0x80000000)) /* pseudo-NaN ? */
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{
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reg_copy(&CONST_QNaN, a);
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}
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/* ensure a Quiet NaN */
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a->sigh |= 0x40000000;
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}
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EXCEPTION(EX_Invalid);
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return (!(FPU_control_word & CW_Invalid) ? FPU_Exception : 0) | TAG_Special;
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}
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/* Real operation attempted on two operands, one a NaN. */
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/* Returns < 0 if the exception is unmasked */
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int real_2op_NaN(FPU_REG const *b, u_char tagb,
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int deststnr,
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FPU_REG const *defaultNaN)
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{
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FPU_REG *dest = &st(deststnr);
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FPU_REG const *a = dest;
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u_char taga = FPU_gettagi(deststnr);
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FPU_REG const *x;
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int signalling, unsupported;
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if (taga == TAG_Special)
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taga = FPU_Special(a);
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if (tagb == TAG_Special)
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tagb = FPU_Special(b);
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/* TW_NaN is also used for unsupported data types. */
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unsupported = ((taga == TW_NaN)
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&& !((exponent(a) == EXP_OVER) && (a->sigh & 0x80000000)))
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|| ((tagb == TW_NaN)
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&& !((exponent(b) == EXP_OVER) && (b->sigh & 0x80000000)));
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if (unsupported)
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{
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if (FPU_control_word & CW_Invalid)
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{
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/* Masked response */
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FPU_copy_to_regi(&CONST_QNaN, TAG_Special, deststnr);
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}
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EXCEPTION(EX_Invalid);
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return (!(FPU_control_word & CW_Invalid) ? FPU_Exception : 0) | TAG_Special;
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}
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if (taga == TW_NaN)
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{
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x = a;
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if (tagb == TW_NaN)
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{
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signalling = !(a->sigh & b->sigh & 0x40000000);
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if (significand(b) > significand(a))
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x = b;
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else if (significand(b) == significand(a))
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{
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/* The default result for the case of two "equal" NaNs (signs may
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differ) is chosen to reproduce 80486 behaviour */
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x = defaultNaN;
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}
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}
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else
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{
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/* return the quiet version of the NaN in a */
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signalling = !(a->sigh & 0x40000000);
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}
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}
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else
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#ifdef PARANOID
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if (tagb == TW_NaN)
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#endif /* PARANOID */
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{
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signalling = !(b->sigh & 0x40000000);
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x = b;
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}
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#ifdef PARANOID
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else
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{
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signalling = 0;
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INTERNAL(0x113);
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x = &CONST_QNaN;
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}
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#endif /* PARANOID */
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if ((!signalling) || (FPU_control_word & CW_Invalid))
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{
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if (! x)
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x = b;
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if (!(x->sigh & 0x80000000)) /* pseudo-NaN ? */
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x = &CONST_QNaN;
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FPU_copy_to_regi(x, TAG_Special, deststnr);
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if (!signalling)
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return TAG_Special;
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/* ensure a Quiet NaN */
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dest->sigh |= 0x40000000;
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}
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EXCEPTION(EX_Invalid);
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return (!(FPU_control_word & CW_Invalid) ? FPU_Exception : 0) | TAG_Special;
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}
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/* Invalid arith operation on Valid registers */
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/* Returns < 0 if the exception is unmasked */
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asmlinkage int arith_invalid(int deststnr)
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{
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EXCEPTION(EX_Invalid);
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if (FPU_control_word & CW_Invalid)
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{
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/* The masked response */
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FPU_copy_to_regi(&CONST_QNaN, TAG_Special, deststnr);
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}
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return (!(FPU_control_word & CW_Invalid) ? FPU_Exception : 0) | TAG_Valid;
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}
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/* Divide a finite number by zero */
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asmlinkage int FPU_divide_by_zero(int deststnr, u_char sign)
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{
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FPU_REG *dest = &st(deststnr);
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int tag = TAG_Valid;
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if (FPU_control_word & CW_ZeroDiv)
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{
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/* The masked response */
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FPU_copy_to_regi(&CONST_INF, TAG_Special, deststnr);
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setsign(dest, sign);
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tag = TAG_Special;
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}
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EXCEPTION(EX_ZeroDiv);
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return (!(FPU_control_word & CW_ZeroDiv) ? FPU_Exception : 0) | tag;
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}
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/* This may be called often, so keep it lean */
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int set_precision_flag(int flags)
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{
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if (FPU_control_word & CW_Precision)
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{
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FPU_partial_status &= ~(SW_C1 & flags);
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FPU_partial_status |= flags; /* The masked response */
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return 0;
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}
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else
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{
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EXCEPTION(flags);
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return 1;
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}
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}
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/* This may be called often, so keep it lean */
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asmlinkage void set_precision_flag_up(void)
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{
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if (FPU_control_word & CW_Precision)
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FPU_partial_status |= (SW_Precision | SW_C1); /* The masked response */
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else
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EXCEPTION(EX_Precision | SW_C1);
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}
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/* This may be called often, so keep it lean */
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asmlinkage void set_precision_flag_down(void)
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{
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if (FPU_control_word & CW_Precision)
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{ /* The masked response */
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FPU_partial_status &= ~SW_C1;
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FPU_partial_status |= SW_Precision;
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}
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else
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EXCEPTION(EX_Precision);
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}
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asmlinkage int denormal_operand(void)
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{
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if (FPU_control_word & CW_Denormal)
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{ /* The masked response */
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FPU_partial_status |= SW_Denorm_Op;
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return TAG_Special;
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}
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else
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{
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EXCEPTION(EX_Denormal);
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return TAG_Special | FPU_Exception;
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}
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}
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asmlinkage int arith_overflow(FPU_REG *dest)
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{
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int tag = TAG_Valid;
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if (FPU_control_word & CW_Overflow)
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{
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/* The masked response */
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reg_copy(&CONST_INF, dest);
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tag = TAG_Special;
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}
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else
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{
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/* Subtract the magic number from the exponent */
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addexponent(dest, (-3 * (1 << 13)));
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}
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EXCEPTION(EX_Overflow);
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if (FPU_control_word & CW_Overflow)
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{
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/* The overflow exception is masked. */
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/* By definition, precision is lost.
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The roundup bit (C1) is also set because we have
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"rounded" upwards to Infinity. */
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EXCEPTION(EX_Precision | SW_C1);
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return tag;
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}
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return tag;
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}
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asmlinkage int arith_round_overflow(FPU_REG *dest, u8 sign)
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{
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int tag = TAG_Valid;
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int largest;
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if (FPU_control_word & CW_Overflow)
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{
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/* The masked response */
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/* The response here depends upon the rounding mode */
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switch (FPU_control_word & CW_RC)
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{
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case RC_CHOP: /* Truncate */
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largest = 1;
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break;
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case RC_UP: /* Towards +infinity */
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largest = (sign == SIGN_NEG);
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break;
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case RC_DOWN: /* Towards -infinity */
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largest = (sign == SIGN_POS);
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break;
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default:
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largest = 0;
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break;
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}
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if (! largest)
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{
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reg_copy(&CONST_INF, dest);
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tag = TAG_Special;
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}
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else
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{
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dest->exp = EXTENDED_Ebias+EXP_OVER-1;
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switch (FPU_control_word & CW_PC)
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{
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case 01:
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case PR_64_BITS:
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significand(dest) = BX_CONST64(0xffffffffffffffff);
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break;
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case PR_53_BITS:
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significand(dest) = BX_CONST64(0xfffffffffffff800);
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break;
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case PR_24_BITS:
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significand(dest) = BX_CONST64(0xffffff0000000000);
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break;
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}
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}
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}
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else
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{
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/* Subtract the magic number from the exponent */
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addexponent(dest, (-3 * (1 << 13)));
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largest = 0;
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}
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EXCEPTION(EX_Overflow);
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if (FPU_control_word & CW_Overflow)
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{
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/* The overflow exception is masked. */
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if (largest)
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{
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EXCEPTION(EX_Precision);
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}
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else
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{
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/* By definition, precision is lost.
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The roundup bit (C1) is also set because we have
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"rounded" upwards to Infinity. */
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EXCEPTION(EX_Precision | SW_C1);
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}
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return tag;
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}
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return tag;
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}
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asmlinkage int arith_underflow(FPU_REG *dest)
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{
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int tag = TAG_Valid;
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if (FPU_control_word & CW_Underflow)
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{
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/* The masked response */
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if (exponent16(dest) <= EXP_UNDER - 63)
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{
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reg_copy(&CONST_Z, dest);
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FPU_partial_status &= ~SW_C1; /* Round down. */
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tag = TAG_Zero;
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}
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else
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{
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stdexp(dest);
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}
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}
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else
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{
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/* Add the magic number to the exponent. */
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addexponent(dest, (3 * (1 << 13)) + EXTENDED_Ebias);
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}
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EXCEPTION(EX_Underflow);
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if (FPU_control_word & CW_Underflow)
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{
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/* The underflow exception is masked. */
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EXCEPTION(EX_Precision);
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return tag;
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}
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return tag;
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}
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void FPU_stack_overflow(void)
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{
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if (FPU_control_word & CW_Invalid)
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{
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/* The masked response */
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FPU_tos--;
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FPU_copy_to_reg0(&CONST_QNaN, TAG_Special);
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}
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EXCEPTION(EX_StackOver);
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}
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void FPU_stack_underflow(void)
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{
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if (FPU_control_word & CW_Invalid)
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{
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/* The masked response */
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FPU_copy_to_reg0(&CONST_QNaN, TAG_Special);
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}
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EXCEPTION(EX_StackUnder);
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}
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void FPU_stack_underflow_i(int i)
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{
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if (FPU_control_word & CW_Invalid)
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{
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/* The masked response */
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FPU_copy_to_regi(&CONST_QNaN, TAG_Special, i);
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}
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EXCEPTION(EX_StackUnder);
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}
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void FPU_stack_underflow_pop(int i)
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{
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if (FPU_control_word & CW_Invalid)
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{
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/* The masked response */
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FPU_copy_to_regi(&CONST_QNaN, TAG_Special, i);
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FPU_pop();
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}
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EXCEPTION(EX_StackUnder);
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}
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