245 lines
8.5 KiB
C
Executable File
245 lines
8.5 KiB
C
Executable File
/////////////////////////////////////////////////////////////////////////
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// $Id$
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/////////////////////////////////////////////////////////////////////////
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//
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// Copyright (C) 2016 The Bochs Project
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//
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// This library is free software; you can redistribute it and/or
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// modify it under the terms of the GNU Lesser General Public
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// License as published by the Free Software Foundation; either
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// version 2 of the License, or (at your option) any later version.
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//
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// This library is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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// Lesser General Public License for more details.
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//
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// You should have received a copy of the GNU Lesser General Public
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// License along with this library; if not, write to the Free Software
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// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA B 02110-1301 USA
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/////////////////////////////////////////////////////////////////////////
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#ifndef BX_X86_DECODER_H
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#define BX_X86_DECODER_H
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// x86 Arch features
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enum {
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BX_ISA_386 = 0, /* 386 or earlier instruction */
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BX_ISA_X87, /* FPU (X87) instruction */
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BX_ISA_486, /* 486 new instruction */
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BX_ISA_PENTIUM, /* Pentium new instruction */
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BX_ISA_P6, /* P6 new instruction */
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BX_ISA_MMX, /* MMX instruction */
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BX_ISA_3DNOW, /* 3DNow! instruction (AMD) */
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BX_ISA_DEBUG_EXTENSIONS, /* Debug Extensions support */
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BX_ISA_VME, /* VME support */
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BX_ISA_PSE, /* PSE support */
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BX_ISA_PAE, /* PAE support */
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BX_ISA_PGE, /* Global Pages support */
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BX_ISA_PSE36, /* PSE-36 support */
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BX_ISA_MTRR, /* MTRR support */
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BX_ISA_PAT, /* PAT support */
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BX_ISA_SYSCALL_SYSRET_LEGACY, /* SYSCALL/SYSRET in legacy mode (AMD) */
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BX_ISA_SYSENTER_SYSEXIT, /* SYSENTER/SYSEXIT instruction */
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BX_ISA_CLFLUSH, /* CLFLUSH instruction */
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BX_ISA_CLFLUSHOPT, /* CLFLUSHOPT instruction */
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BX_ISA_CLWB, /* CLWB instruction */
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BX_ISA_SSE, /* SSE instruction */
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BX_ISA_SSE2, /* SSE2 instruction */
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BX_ISA_SSE3, /* SSE3 instruction */
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BX_ISA_SSSE3, /* SSSE3 instruction */
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BX_ISA_SSE4_1, /* SSE4_1 instruction */
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BX_ISA_SSE4_2, /* SSE4_2 instruction */
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BX_ISA_POPCNT, /* POPCNT instruction */
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BX_ISA_MONITOR_MWAIT, /* MONITOR/MWAIT instruction */
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BX_ISA_VMX, /* VMX instruction */
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BX_ISA_SMX, /* SMX instruction */
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BX_ISA_LONG_MODE, /* Long Mode (x86-64) support */
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BX_ISA_LM_LAHF_SAHF, /* Long Mode LAHF/SAHF instruction */
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BX_ISA_NX, /* No-Execute support */
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BX_ISA_1G_PAGES, /* 1Gb pages support */
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BX_ISA_CMPXCHG16B, /* CMPXCHG16B instruction */
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BX_ISA_RDTSCP, /* RDTSCP instruction */
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BX_ISA_FFXSR, /* EFER.FFXSR support */
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BX_ISA_XSAVE, /* XSAVE/XRSTOR extensions instruction */
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BX_ISA_XSAVEOPT, /* XSAVEOPT instruction */
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BX_ISA_XSAVEC, /* XSAVEC instruction */
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BX_ISA_XSAVES, /* XSAVES instruction */
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BX_ISA_AES_PCLMULQDQ, /* AES+PCLMULQDQ instruction */
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BX_ISA_MOVBE, /* MOVBE instruction */
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BX_ISA_FSGSBASE, /* FS/GS BASE access instruction */
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BX_ISA_INVPCID, /* INVPCID instruction */
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BX_ISA_AVX, /* AVX instruction */
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BX_ISA_AVX2, /* AVX2 instruction */
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BX_ISA_AVX_F16C, /* AVX F16 convert instruction */
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BX_ISA_AVX_FMA, /* AVX FMA instruction */
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BX_ISA_ALT_MOV_CR8, /* LOCK CR0 access CR8 (AMD) */
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BX_ISA_SSE4A, /* SSE4A instruction (AMD) */
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BX_ISA_MISALIGNED_SSE, /* Misaligned SSE (AMD) */
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BX_ISA_LZCNT, /* LZCNT instruction */
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BX_ISA_BMI1, /* BMI1 instruction */
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BX_ISA_BMI2, /* BMI2 instruction */
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BX_ISA_FMA4, /* FMA4 instruction (AMD) */
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BX_ISA_XOP, /* XOP instruction (AMD) */
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BX_ISA_TBM, /* TBM instruction (AMD) */
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BX_ISA_SVM, /* SVM instruction (AMD) */
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BX_ISA_RDRAND, /* RDRAND instruction */
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BX_ISA_ADX, /* ADCX/ADOX instruction */
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BX_ISA_SMAP, /* SMAP support */
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BX_ISA_RDSEED, /* RDSEED instruction */
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BX_ISA_SHA, /* SHA instruction */
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BX_ISA_AVX512, /* AVX-512 instruction */
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BX_ISA_AVX512_CD, /* AVX-512 Conflict Detection instruction */
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BX_ISA_AVX512_PF, /* AVX-512 Sparse Prefetch instruction */
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BX_ISA_AVX512_ER, /* AVX-512 Exponential/Reciprocal instruction */
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BX_ISA_AVX512_DQ, /* AVX-512DQ instruction */
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BX_ISA_AVX512_BW, /* AVX-512 Byte/Word instruction */
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BX_ISA_AVX512_VL, /* AVX-512 Vector Length extensions */
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BX_ISA_AVX512_VBMI, /* AVX-512 Vector Bit Manipulation Instructions */
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BX_ISA_AVX512_IFMA52, /* AVX-512 IFMA52 Instructions */
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BX_ISA_AVX512_VPOPCNTDQ, /* AVX-512 VPOPCNTD/VPOPCNTQ Instructions */
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BX_ISA_XAPIC, /* XAPIC support */
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BX_ISA_X2APIC, /* X2APIC support */
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BX_ISA_XAPIC_EXT, /* XAPIC Extensions support */
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BX_ISA_PCID, /* PCID pages support */
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BX_ISA_SMEP, /* SMEP support */
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BX_ISA_TSC_DEADLINE, /* TSC-Deadline */
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BX_ISA_FCS_FDS_DEPRECATION, /* FCS/FDS Deprecation */
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BX_ISA_FDP_DEPRECATION, /* FDP Deprecation - FDP update on unmasked x87 exception only */
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BX_ISA_PKU, /* User-Mode Protection Keys */
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BX_ISA_UMIP, /* User-Mode Instructions Prevention */
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BX_ISA_RDPID, /* RDPID Support */
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BX_ISA_EXTENSION_LAST
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};
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#define BX_ISA_EXTENSIONS_ARRAY_SIZE (4)
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#if (BX_ISA_EXTENSION_LAST) >= (BX_ISA_EXTENSIONS_ARRAY_SIZE*32)
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#error "ISA extensions array limit exceeded!"
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#endif
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// segment register encoding
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enum BxSegregs {
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BX_SEG_REG_ES = 0,
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BX_SEG_REG_CS = 1,
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BX_SEG_REG_SS = 2,
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BX_SEG_REG_DS = 3,
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BX_SEG_REG_FS = 4,
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BX_SEG_REG_GS = 5,
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// NULL now has to fit in 3 bits.
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BX_SEG_REG_NULL = 7
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};
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#define BX_NULL_SEG_REG(seg) ((seg) == BX_SEG_REG_NULL)
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enum BxRegs8L {
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BX_8BIT_REG_AL,
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BX_8BIT_REG_CL,
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BX_8BIT_REG_DL,
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BX_8BIT_REG_BL,
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BX_8BIT_REG_SPL,
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BX_8BIT_REG_BPL,
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BX_8BIT_REG_SIL,
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BX_8BIT_REG_DIL,
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#if BX_SUPPORT_X86_64
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BX_8BIT_REG_R8,
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BX_8BIT_REG_R9,
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BX_8BIT_REG_R10,
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BX_8BIT_REG_R11,
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BX_8BIT_REG_R12,
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BX_8BIT_REG_R13,
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BX_8BIT_REG_R14,
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BX_8BIT_REG_R15
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#endif
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};
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enum BxRegs8H {
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BX_8BIT_REG_AH,
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BX_8BIT_REG_CH,
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BX_8BIT_REG_DH,
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BX_8BIT_REG_BH
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};
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enum BxRegs16 {
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BX_16BIT_REG_AX,
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BX_16BIT_REG_CX,
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BX_16BIT_REG_DX,
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BX_16BIT_REG_BX,
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BX_16BIT_REG_SP,
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BX_16BIT_REG_BP,
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BX_16BIT_REG_SI,
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BX_16BIT_REG_DI,
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#if BX_SUPPORT_X86_64
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BX_16BIT_REG_R8,
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BX_16BIT_REG_R9,
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BX_16BIT_REG_R10,
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BX_16BIT_REG_R11,
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BX_16BIT_REG_R12,
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BX_16BIT_REG_R13,
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BX_16BIT_REG_R14,
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BX_16BIT_REG_R15,
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#endif
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};
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enum BxRegs32 {
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BX_32BIT_REG_EAX,
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BX_32BIT_REG_ECX,
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BX_32BIT_REG_EDX,
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BX_32BIT_REG_EBX,
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BX_32BIT_REG_ESP,
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BX_32BIT_REG_EBP,
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BX_32BIT_REG_ESI,
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BX_32BIT_REG_EDI,
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#if BX_SUPPORT_X86_64
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BX_32BIT_REG_R8,
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BX_32BIT_REG_R9,
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BX_32BIT_REG_R10,
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BX_32BIT_REG_R11,
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BX_32BIT_REG_R12,
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BX_32BIT_REG_R13,
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BX_32BIT_REG_R14,
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BX_32BIT_REG_R15,
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#endif
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};
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#if BX_SUPPORT_X86_64
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enum BxRegs64 {
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BX_64BIT_REG_RAX,
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BX_64BIT_REG_RCX,
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BX_64BIT_REG_RDX,
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BX_64BIT_REG_RBX,
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BX_64BIT_REG_RSP,
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BX_64BIT_REG_RBP,
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BX_64BIT_REG_RSI,
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BX_64BIT_REG_RDI,
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BX_64BIT_REG_R8,
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BX_64BIT_REG_R9,
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BX_64BIT_REG_R10,
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BX_64BIT_REG_R11,
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BX_64BIT_REG_R12,
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BX_64BIT_REG_R13,
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BX_64BIT_REG_R14,
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BX_64BIT_REG_R15,
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};
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#endif
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#if BX_SUPPORT_X86_64
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# define BX_GENERAL_REGISTERS 16
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#else
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# define BX_GENERAL_REGISTERS 8
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#endif
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enum OpmaskRegs {
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BX_REG_OPMASK_K0,
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BX_REG_OPMASK_K1,
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BX_REG_OPMASK_K2,
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BX_REG_OPMASK_K3,
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BX_REG_OPMASK_K4,
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BX_REG_OPMASK_K5,
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BX_REG_OPMASK_K6,
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BX_REG_OPMASK_K7
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};
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#endif // BX_X86_DECODER_H
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