99 lines
2.4 KiB
ArmAsm
99 lines
2.4 KiB
ArmAsm
/////////////////////////////////////////////////////////////////////////
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// $Id: rombios32start.S,v 1.3 2006-10-02 06:29:38 vruppert Exp $
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/////////////////////////////////////////////////////////////////////////
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//
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// 32 bit Bochs BIOS init code
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// Copyright (C) 2006 Fabrice Bellard
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//
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// This library is free software; you can redistribute it and/or
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// modify it under the terms of the GNU Lesser General Public
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// License as published by the Free Software Foundation; either
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// version 2 of the License, or (at your option) any later version.
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//
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// This library is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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// Lesser General Public License for more details.
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//
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// You should have received a copy of the GNU Lesser General Public
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// License along with this library; if not, write to the Free Software
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// Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
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#include "rombios.h"
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.globl _start
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.globl smp_ap_boot_code_start
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.globl smp_ap_boot_code_end
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.global smm_relocation_start
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.global smm_relocation_end
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.global smm_code_start
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.global smm_code_end
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_start:
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/* clear bss section */
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xor %eax, %eax
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mov $__bss_start, %edi
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mov $_end, %ecx
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sub %edi, %ecx
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rep stosb
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jmp rombios32_init
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.code16
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smp_ap_boot_code_start:
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xor %ax, %ax
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mov %ax, %ds
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incw CPU_COUNT_ADDR
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1:
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hlt
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jmp 1b
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smp_ap_boot_code_end:
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/* code to relocate SMBASE to 0xa0000 */
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smm_relocation_start:
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mov $0x38000 + 0x7efc, %ebx
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addr32 mov (%ebx), %al /* revision ID to see if x86_64 or x86 */
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cmp $0x64, %al
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je 1f
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mov $0x38000 + 0x7ef8, %ebx
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jmp 2f
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1:
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mov $0x38000 + 0x7f00, %ebx
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2:
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movl $0xa0000, %eax
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addr32 movl %eax, (%ebx)
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/* indicate to the BIOS that the SMM code was executed */
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mov $0x00, %al
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movw $0xb3, %dx
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outb %al, %dx
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rsm
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smm_relocation_end:
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/* minimal SMM code to enable or disable ACPI */
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smm_code_start:
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movw $0xb2, %dx
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inb %dx, %al
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cmp $0xf0, %al
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jne 1f
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/* ACPI disable */
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mov $PM_IO_BASE + 0x04, %dx /* PMCNTRL */
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inw %dx, %ax
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andw $~1, %ax
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outw %ax, %dx
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jmp 2f
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1:
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cmp $0xf1, %al
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jne 2f
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/* ACPI enable */
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mov $PM_IO_BASE + 0x04, %dx /* PMCNTRL */
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inw %dx, %ax
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orw $1, %ax
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outw %ax, %dx
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2:
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rsm
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smm_code_end:
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