630 lines
18 KiB
C++
630 lines
18 KiB
C++
/////////////////////////////////////////////////////////////////////////
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// $Id$
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/////////////////////////////////////////////////////////////////////////
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//
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// Copyright (c) 2013-2017 Stanislav Shwartsman
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// Written by Stanislav Shwartsman [sshwarts at sourceforge net]
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//
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// This library is free software; you can redistribute it and/or
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// modify it under the terms of the GNU Lesser General Public
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// License as published by the Free Software Foundation; either
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// version 2 of the License, or (at your option) any later version.
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//
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// This library is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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// Lesser General Public License for more details.
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//
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// You should have received a copy of the GNU Lesser General Public
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// License along with this library; if not, write to the Free Software
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// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA B 02110-1301 USA
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//
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/////////////////////////////////////////////////////////////////////////
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#include "bochs.h"
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#include "../cpu.h"
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#include "fetchdecode.h"
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extern int fetchDecode32(const Bit8u *fetchPtr, Bit32u fetchModeMask, bx_bool handle_lock_cr0, bxInstruction_c *i, unsigned remainingInPage);
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#if BX_SUPPORT_X86_64
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extern int fetchDecode64(const Bit8u *fetchPtr, Bit32u fetchModeMask, bx_bool handle_lock_cr0, bxInstruction_c *i, unsigned remainingInPage);
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#endif
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// table of all Bochs opcodes
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extern struct bxIAOpcodeTable BxOpcodesTable[];
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#include <ctype.h>
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char* dis_sprintf(char *disbufptr, const char *fmt, ...)
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{
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va_list ap;
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va_start(ap, fmt);
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vsprintf(disbufptr, fmt, ap);
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va_end(ap);
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disbufptr += strlen(disbufptr);
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return disbufptr;
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}
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char* dis_putc(char *disbufptr, char symbol)
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{
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*disbufptr++ = symbol;
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*disbufptr = 0;
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return disbufptr;
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}
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static const char *intel_general_16bit_regname[16] = {
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"ax", "cx", "dx", "bx", "sp", "bp", "si", "di",
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"r8w", "r9w", "r10w", "r11w", "r12w", "r13w", "r14w", "r15w"
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};
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static const char *intel_general_32bit_regname[17] = {
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"eax", "ecx", "edx", "ebx", "esp", "ebp", "esi", "edi",
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"r8d", "r9d", "r10d", "r11d", "r12d", "r13d", "r14d", "r15d", "eip"
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};
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static const char *intel_general_64bit_regname[17] = {
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"rax", "rcx", "rdx", "rbx", "rsp", "rbp", "rsi", "rdi",
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"r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", "rip"
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};
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#if BX_SUPPORT_X86_64
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static const char *intel_general_8bit_regname_rex[16] = {
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"al", "cl", "dl", "bl", "spl", "bpl", "sil", "dil",
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"r8b", "r9b", "r10b", "r11b", "r12b", "r13b", "r14b", "r15b"
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};
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#endif
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static const char *intel_general_8bit_regname[8] = {
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"al", "cl", "dl", "bl", "ah", "ch", "dh", "bh"
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};
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static const char *intel_segment_name[8] = {
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"es", "cs", "ss", "ds", "fs", "gs", "??", "??"
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};
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static const char *intel_vector_reg_name[4] = {
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"xmm", "ymm", "???", "zmm"
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};
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#if BX_SUPPORT_EVEX
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static const char *rounding_mode[4] = {
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"round_nearest_even", "round_down", "round_up", "round_to_zero"
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};
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#endif
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#define BX_JUMP_TARGET_NOT_REQ ((bx_address)(-1))
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char *resolve_sib_scale(char *disbufptr, const bxInstruction_c *i, const char *regname[], unsigned src_index)
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{
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unsigned sib_index = i->sibIndex(), sib_scale = i->sibScale();
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#if BX_SUPPORT_AVX
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if (src_index == BX_SRC_VSIB)
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disbufptr = dis_sprintf(disbufptr, "%s%d", intel_vector_reg_name[i->getVL() - 1], sib_index);
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else
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#endif
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disbufptr = dis_sprintf(disbufptr, "%s", regname[sib_index]);
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if (sib_scale)
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disbufptr = dis_sprintf(disbufptr, "*%d", 1 << sib_scale);
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return disbufptr;
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}
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char *resolve_memref(char *disbufptr, const bxInstruction_c *i, const char *regname[], unsigned src_index)
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{
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unsigned sib_base = i->sibBase(), sib_index = i->sibIndex();
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if (sib_index == 4 && src_index != BX_SRC_VSIB)
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sib_index = BX_NIL_REGISTER;
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if (sib_base == BX_NIL_REGISTER)
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{
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if (sib_index == BX_NIL_REGISTER)
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{
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#if BX_SUPPORT_X86_64
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if (i->as64L()) {
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disbufptr = dis_sprintf(disbufptr, "0x" FMT_ADDRX, (Bit64u) i->displ32s());
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return disbufptr;
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}
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#endif
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if (i->as32L()) {
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disbufptr = dis_sprintf(disbufptr, "0x%08x", (Bit32u) i->displ32s());
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}
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else {
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disbufptr = dis_sprintf(disbufptr, "0x%04x", (Bit32u) (Bit16u) i->displ16s());
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}
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return disbufptr;
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}
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disbufptr = dis_putc(disbufptr, '[');
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disbufptr = resolve_sib_scale(disbufptr, i, regname, src_index);
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}
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else {
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disbufptr = dis_sprintf(disbufptr, "[%s", regname[i->sibBase()]);
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if (sib_index != BX_NIL_REGISTER) {
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disbufptr = dis_putc(disbufptr, '+');
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disbufptr = resolve_sib_scale(disbufptr, i, regname, src_index);
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}
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}
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if (i->as32L()) {
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if (i->displ32s() != 0) {
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disbufptr = dis_sprintf(disbufptr, "%+d", i->displ32s());
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}
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}
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else {
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if (i->displ16s() != 0) {
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disbufptr = dis_sprintf(disbufptr, "%+d", (Bit32s) i->displ16s());
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}
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}
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disbufptr = dis_putc(disbufptr, ']');
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return disbufptr;
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}
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char *resolve_memsize(char *disbufptr, const bxInstruction_c *i, unsigned src_index, unsigned src_type)
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{
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if (src_index == BX_SRC_RM) {
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switch(src_type) {
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case BX_GPR8:
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case BX_GPR8_32: // 8-bit memory ref but 32-bit GPR
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disbufptr = dis_sprintf(disbufptr, "byte ptr ");
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break;
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case BX_GPR16:
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case BX_GPR16_32: // 16-bit memory ref but 32-bit GPR
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case BX_SEGREG:
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disbufptr = dis_sprintf(disbufptr, "word ptr ");
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break;
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case BX_GPR32:
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disbufptr = dis_sprintf(disbufptr, "dword ptr ");
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break;
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case BX_GPR64:
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case BX_MMX_REG:
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#if BX_SUPPORT_EVEX
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case BX_KMASK_REG:
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#endif
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disbufptr = dis_sprintf(disbufptr, "qword ptr ");
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break;
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case BX_FPU_REG:
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disbufptr = dis_sprintf(disbufptr, "tbyte ptr ");
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break;
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case BX_VMM_REG:
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#if BX_SUPPORT_AVX
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if (i->getVL() > BX_NO_VL)
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disbufptr = dis_sprintf(disbufptr, "%sword ptr ", intel_vector_reg_name[i->getVL() - 1]);
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else
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#endif
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disbufptr = dis_sprintf(disbufptr, "xmmword ptr ");
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break;
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default:
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break;
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}
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}
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return disbufptr;
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}
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// disasembly of memory reference
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char *resolve_memref(char *disbufptr, const bxInstruction_c *i, unsigned src_index, unsigned src_type)
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{
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disbufptr = resolve_memsize(disbufptr, i, src_index, src_type);
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// seg:[base + index*scale + disp]
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disbufptr = dis_sprintf(disbufptr, "%s:", intel_segment_name[i->seg()]);
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if (i->as64L()) {
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disbufptr = resolve_memref(disbufptr, i, intel_general_64bit_regname, src_index);
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}
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else if (i->as32L()) {
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disbufptr = resolve_memref(disbufptr, i, intel_general_32bit_regname, src_index);
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}
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else {
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disbufptr = resolve_memref(disbufptr, i, intel_general_16bit_regname, src_index);
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}
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return disbufptr;
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}
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// disasembly of register reference
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char *disasm_regref(char *disbufptr, const bxInstruction_c *i, unsigned src_num, unsigned src_type)
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{
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unsigned srcreg = i->getSrcReg(src_num);
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switch(src_type) {
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case BX_GPR8:
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#if BX_SUPPORT_X86_64
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if (i->extend8bitL())
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disbufptr = dis_sprintf(disbufptr, "%s", intel_general_8bit_regname_rex[srcreg]);
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else
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#endif
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disbufptr = dis_sprintf(disbufptr, "%s", intel_general_8bit_regname[srcreg]);
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break;
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case BX_GPR16:
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disbufptr = dis_sprintf(disbufptr, "%s", intel_general_16bit_regname[srcreg]);
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break;
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case BX_GPR32:
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case BX_GPR8_32: // 8-bit memory ref but 32-bit GPR
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case BX_GPR16_32: // 16-bit memory ref but 32-bit GPR
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disbufptr = dis_sprintf(disbufptr, "%s", intel_general_32bit_regname[srcreg]);
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break;
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#if BX_SUPPORT_X86_64
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case BX_GPR64:
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disbufptr = dis_sprintf(disbufptr, "%s", intel_general_64bit_regname[srcreg]);
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break;
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#endif
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case BX_FPU_REG:
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disbufptr = dis_sprintf(disbufptr, "st(%d)", srcreg & 0x7);
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break;
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case BX_MMX_REG:
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disbufptr = dis_sprintf(disbufptr, "mm%d", srcreg & 0x7);
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break;
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case BX_VMM_REG:
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#if BX_SUPPORT_AVX
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if (i->getVL() > BX_NO_VL) {
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disbufptr = dis_sprintf(disbufptr, "%s%d", intel_vector_reg_name[i->getVL() - 1], srcreg);
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#if BX_SUPPORT_EVEX
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if (src_num == 0 && i->opmask()) {
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disbufptr = dis_sprintf(disbufptr, "{k%d}%s", i->opmask(),
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i->isZeroMasking() ? "{z}" : "");
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}
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#endif
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}
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else
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#endif
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{
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disbufptr = dis_sprintf(disbufptr, "xmm%d", srcreg);
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}
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break;
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#if BX_SUPPORT_EVEX
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case BX_KMASK_REG:
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disbufptr = dis_sprintf(disbufptr, "k%d", srcreg);
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assert(srcreg < 8);
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if (src_num == 0 && i->opmask()) {
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disbufptr = dis_sprintf(disbufptr, "{k%d}%s", i->opmask(),
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i->isZeroMasking() ? "{z}" : "");
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}
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break;
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#endif
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case BX_SEGREG:
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disbufptr = dis_sprintf(disbufptr, "%s", intel_segment_name[srcreg]);
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break;
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case BX_CREG:
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disbufptr = dis_sprintf(disbufptr, "cr%d", srcreg);
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break;
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case BX_DREG:
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disbufptr = dis_sprintf(disbufptr, "dr%d", srcreg);
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break;
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default:
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if (src_type != BX_NO_REGISTER)
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disbufptr = dis_sprintf(disbufptr, "(unknown source type %d)", src_type);
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break;
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}
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return disbufptr;
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}
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char *disasm_immediate(char *disbufptr, const bxInstruction_c *i, unsigned src_type, bx_address cs_base, bx_address rip)
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{
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switch(src_type) {
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case BX_DIRECT_MEMREF_B:
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disbufptr = resolve_memsize(disbufptr, i, BX_SRC_RM, BX_GPR8);
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break;
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case BX_DIRECT_MEMREF_W:
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disbufptr = resolve_memsize(disbufptr, i, BX_SRC_RM, BX_GPR16);
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break;
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case BX_DIRECT_MEMREF_D:
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disbufptr = resolve_memsize(disbufptr, i, BX_SRC_RM, BX_GPR32);
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break;
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case BX_DIRECT_MEMREF_Q:
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disbufptr = resolve_memsize(disbufptr, i, BX_SRC_RM, BX_GPR64);
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break;
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default: break;
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};
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switch(src_type) {
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case BX_IMMB:
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disbufptr = dis_sprintf(disbufptr, "0x%02x", i->Ib());
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break;
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case BX_IMMW:
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disbufptr = dis_sprintf(disbufptr, "0x%04x", i->Iw());
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break;
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case BX_IMMD:
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disbufptr = dis_sprintf(disbufptr, "0x%08x", i->Id());
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break;
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#if BX_SUPPORT_X86_64
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case BX_IMMD_SE:
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disbufptr = dis_sprintf(disbufptr, "0x" FMT_ADDRX64, (Bit64u) (Bit32s) i->Id());
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break;
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case BX_IMMQ:
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disbufptr = dis_sprintf(disbufptr, "0x" FMT_ADDRX64, i->Iq());
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break;
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#endif
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case BX_IMMB2:
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disbufptr = dis_sprintf(disbufptr, "0x%02x", i->Ib2());
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break;
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case BX_IMM_BrOff16:
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disbufptr = dis_sprintf(disbufptr, ".%+d", (Bit32s) (Bit16s) i->Iw());
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if (cs_base != BX_JUMP_TARGET_NOT_REQ) {
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Bit16u target = (rip + i->ilen() + (Bit16s) i->Iw()) & 0xffff;
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disbufptr = dis_sprintf(disbufptr, " (0x%08x)", (Bit32u)(cs_base + target));
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}
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break;
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case BX_IMM_BrOff32:
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disbufptr = dis_sprintf(disbufptr, ".%+d", (Bit32s) i->Id());
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if (cs_base != BX_JUMP_TARGET_NOT_REQ) {
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Bit32u target = (Bit32u)(rip + i->ilen() + (Bit32s) i->Id());
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disbufptr = dis_sprintf(disbufptr, " (0x%08x)", (Bit32u) (cs_base + target));
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}
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break;
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#if BX_SUPPORT_X86_64
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case BX_IMM_BrOff64:
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disbufptr = dis_sprintf(disbufptr, ".%+d", (Bit32s) i->Id());
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if (cs_base != BX_JUMP_TARGET_NOT_REQ) {
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Bit64u target = rip + i->ilen() + (Bit32s) i->Id();
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disbufptr = dis_sprintf(disbufptr, " (0x" FMT_ADDRX ")", (Bit64u) (cs_base + target));
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}
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break;
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#endif
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case BX_DIRECT_PTR:
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if (i->os32L())
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disbufptr = dis_sprintf(disbufptr, "0x%04x:%08x", i->Iw2(), i->Id());
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else
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disbufptr = dis_sprintf(disbufptr, "0x%04x:%04x", i->Iw2(), i->Iw());
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break;
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case BX_DIRECT_MEMREF_B:
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case BX_DIRECT_MEMREF_W:
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case BX_DIRECT_MEMREF_D:
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case BX_DIRECT_MEMREF_Q:
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disbufptr = dis_sprintf(disbufptr, "%s:", intel_segment_name[i->seg()]);
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#if BX_SUPPORT_X86_64
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if (i->as64L())
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disbufptr = dis_sprintf(disbufptr, "0x" FMT_ADDRX, i->Iq());
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else
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#endif
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if (i->as32L())
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disbufptr = dis_sprintf(disbufptr, "0x%08x", i->Id());
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else
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disbufptr = dis_sprintf(disbufptr, "0x%04x", i->Id());
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break;
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default:
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disbufptr = dis_sprintf(disbufptr, "(unknown immediate form for disasm %d)", src_type);
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}
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return disbufptr;
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}
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char *disasm_implicit_src(char *disbufptr, const bxInstruction_c *i, unsigned src_type)
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{
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switch(src_type) {
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case BX_RSIREF_B:
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case BX_RDIREF_B:
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disbufptr = resolve_memsize(disbufptr, i, BX_SRC_RM, BX_GPR8);
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break;
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case BX_RSIREF_W:
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case BX_RDIREF_W:
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disbufptr = resolve_memsize(disbufptr, i, BX_SRC_RM, BX_GPR16);
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break;
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case BX_RSIREF_D:
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case BX_RDIREF_D:
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disbufptr = resolve_memsize(disbufptr, i, BX_SRC_RM, BX_GPR32);
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break;
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case BX_RSIREF_Q:
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case BX_RDIREF_Q:
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disbufptr = resolve_memsize(disbufptr, i, BX_SRC_RM, BX_GPR64);
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break;
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default: break;
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};
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switch(src_type) {
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case BX_RSIREF_B:
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case BX_RSIREF_W:
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case BX_RSIREF_D:
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case BX_RSIREF_Q:
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disbufptr = dis_sprintf(disbufptr, "%s:", intel_segment_name[i->seg()]);
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#if BX_SUPPORT_X86_64
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if (i->as64L()) {
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disbufptr = dis_sprintf(disbufptr, "[%s]", intel_general_64bit_regname[BX_64BIT_REG_RSI]);
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}
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else
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#endif
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{
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if (i->as32L())
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disbufptr = dis_sprintf(disbufptr, "[%s]", intel_general_32bit_regname[BX_32BIT_REG_ESI]);
|
|
else
|
|
disbufptr = dis_sprintf(disbufptr, "[%s]", intel_general_16bit_regname[BX_16BIT_REG_SI]);
|
|
}
|
|
break;
|
|
|
|
case BX_RDIREF_B:
|
|
case BX_RDIREF_W:
|
|
case BX_RDIREF_D:
|
|
case BX_RDIREF_Q:
|
|
disbufptr = dis_sprintf(disbufptr, "%s:", intel_segment_name[BX_SEG_REG_ES]);
|
|
#if BX_SUPPORT_X86_64
|
|
if (i->as64L()) {
|
|
disbufptr = dis_sprintf(disbufptr, "[%s]", intel_general_64bit_regname[BX_64BIT_REG_RDI]);
|
|
}
|
|
else
|
|
#endif
|
|
{
|
|
if (i->as32L())
|
|
disbufptr = dis_sprintf(disbufptr, "[%s]", intel_general_32bit_regname[BX_32BIT_REG_EDI]);
|
|
else
|
|
disbufptr = dis_sprintf(disbufptr, "[%s]", intel_general_16bit_regname[BX_16BIT_REG_DI]);
|
|
}
|
|
break;
|
|
|
|
case BX_USECL:
|
|
disbufptr = dis_sprintf(disbufptr, "cl");
|
|
break;
|
|
|
|
case BX_USEDX:
|
|
disbufptr = dis_sprintf(disbufptr, "dx");
|
|
break;
|
|
|
|
default:
|
|
disbufptr = dis_sprintf(disbufptr, "(unknown implicit source for disasm %d)", src_type);
|
|
}
|
|
|
|
return disbufptr;
|
|
}
|
|
|
|
char* disasm(char *disbufptr, const bxInstruction_c *i, bx_address cs_base, bx_address rip)
|
|
{
|
|
#if BX_SUPPORT_HANDLERS_CHAINING_SPEEDUPS
|
|
if (i->getIaOpcode() == BX_INSERTED_OPCODE) {
|
|
disbufptr = dis_sprintf(disbufptr, "(bochs inserted internal opcode)");
|
|
return disbufptr;
|
|
}
|
|
#endif
|
|
|
|
if (i->execute1 == &BX_CPU_C::BxError) {
|
|
disbufptr = dis_sprintf(disbufptr, "(invalid)");
|
|
return disbufptr;
|
|
}
|
|
|
|
const char *opname = i->getIaOpcodeNameShort(); // skip the "BX_IA_"
|
|
unsigned n;
|
|
#if BX_SUPPORT_EVEX
|
|
bx_bool is_vector = BX_FALSE;
|
|
#endif
|
|
|
|
if (! strncmp(opname, "V128_", 5) || ! strncmp(opname, "V256_", 5) || ! strncmp(opname, "V512_", 5)) {
|
|
opname += 5;
|
|
#if BX_SUPPORT_EVEX
|
|
is_vector = BX_TRUE;
|
|
#endif
|
|
}
|
|
|
|
// Step 1: print prefixes
|
|
if (i->lockRepUsedValue() == 1)
|
|
disbufptr = dis_sprintf(disbufptr, "lock ");
|
|
|
|
if (! strncmp(opname, "REP_", 4)) {
|
|
opname += 4;
|
|
|
|
if (i->repUsedL()) {
|
|
if (i->lockRepUsedValue() == 2)
|
|
disbufptr = dis_sprintf(disbufptr, "repne ");
|
|
else
|
|
disbufptr = dis_sprintf(disbufptr, "rep ");
|
|
}
|
|
}
|
|
|
|
// Step 2: print opcode name
|
|
unsigned opname_len = strlen(opname);
|
|
for (n=0;n < opname_len; n++) {
|
|
if (opname[n] == '_') break;
|
|
disbufptr = dis_putc(disbufptr, tolower(opname[n]));
|
|
}
|
|
|
|
disbufptr = dis_putc(disbufptr, ' ');
|
|
|
|
// Step 3: print sources
|
|
Bit16u ia_opcode = i->getIaOpcode();
|
|
unsigned srcs_used = 0;
|
|
for (n = 0; n <= 3; n++) {
|
|
unsigned src = (unsigned) BxOpcodesTable[ia_opcode].src[n];
|
|
unsigned src_type = BX_DISASM_SRC_TYPE(src);
|
|
unsigned src_index = BX_DISASM_SRC_ORIGIN(src);
|
|
if (! src_type && src_index != BX_SRC_RM && src_index != BX_SRC_EVEX_RM) continue;
|
|
if (srcs_used++ > 0)
|
|
disbufptr = dis_sprintf(disbufptr, ", ");
|
|
|
|
if (! i->modC0() && (src_index == BX_SRC_RM || src_index == BX_SRC_EVEX_RM || src_index == BX_SRC_VSIB)) {
|
|
disbufptr = resolve_memref(disbufptr, i, src_index, src_type);
|
|
#if BX_SUPPORT_EVEX
|
|
// EVEX.z is ignored for memory destination forms
|
|
if (n == 0 && (src_index == BX_SRC_EVEX_RM || src_index == BX_SRC_VSIB || src_type == BX_VMM_REG) && i->opmask()) {
|
|
disbufptr = dis_sprintf(disbufptr, "{k%d}", i->opmask());
|
|
}
|
|
#endif
|
|
}
|
|
else {
|
|
if (src_index == BX_SRC_EVEX_RM) src_type = BX_VMM_REG;
|
|
|
|
if (src_index == BX_SRC_IMM) {
|
|
// this is immediate value (including branch targets)
|
|
disbufptr = disasm_immediate(disbufptr, i, src_type, cs_base, rip);
|
|
}
|
|
else if (src_index == BX_SRC_IMPLICIT) {
|
|
// this is implicit register or memory reference
|
|
disbufptr = disasm_implicit_src(disbufptr, i, src_type);
|
|
}
|
|
else {
|
|
// this is register reference
|
|
disbufptr = disasm_regref(disbufptr, i, n, src_type);
|
|
}
|
|
}
|
|
}
|
|
|
|
#if BX_SUPPORT_EVEX
|
|
if (is_vector && i->getEvexb()) {
|
|
if (! i->modC0())
|
|
disbufptr = dis_sprintf(disbufptr, " {broadcast}");
|
|
else
|
|
disbufptr = dis_sprintf(disbufptr, " {sae/%s}", rounding_mode[i->getRC()]);
|
|
}
|
|
#endif
|
|
|
|
return disbufptr;
|
|
}
|
|
|
|
char* disasm(const Bit8u *opcode, bool is_32, bool is_64, char *disbufptr, bxInstruction_c *i, bx_address cs_base, bx_address rip)
|
|
{
|
|
Bit32u fetchModeMask = BX_FETCH_MODE_SSE_OK |
|
|
BX_FETCH_MODE_AVX_OK |
|
|
BX_FETCH_MODE_OPMASK_OK |
|
|
BX_FETCH_MODE_EVEX_OK;
|
|
|
|
if (is_64) fetchModeMask |= BX_FETCH_MODE_IS64_MASK;
|
|
else if (is_32) fetchModeMask |= BX_FETCH_MODE_IS32_MASK;
|
|
|
|
int ret;
|
|
|
|
#if BX_SUPPORT_X86_64
|
|
if (is_64)
|
|
ret = fetchDecode64(opcode, fetchModeMask, BX_CPU(0)->is_cpu_extension_supported(BX_ISA_ALT_MOV_CR8), i, 16);
|
|
else
|
|
#endif
|
|
ret = fetchDecode32(opcode, fetchModeMask, BX_CPU(0)->is_cpu_extension_supported(BX_ISA_ALT_MOV_CR8), i, 16);
|
|
|
|
if (ret < 0)
|
|
sprintf(disbufptr, "decode failed");
|
|
else
|
|
::disasm(disbufptr, i, cs_base, rip);
|
|
|
|
return disbufptr;
|
|
}
|