1fd6745aea
the display adapter code. When ready, the common gui code should handle it completely. The snapshot handler should set a flag 'snapshot_mode' and then it should force a display update. The graphics update code should be redirected to some code that 'draws' to a snapshot buffer. These first steps are done: - store some guest display settings in the gui code (text / graphics switch, x / y resolution and bpp) - split 8 bpp palette update code in a common and a specific part and store the palette values in the gui code
266 lines
9.3 KiB
C++
266 lines
9.3 KiB
C++
/////////////////////////////////////////////////////////////////////////
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// $Id$
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/////////////////////////////////////////////////////////////////////////
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//
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// Copyright (c) 2004 Makoto Suzuki (suzu)
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// Volker Ruppert (vruppert)
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// Robin Kay (komadori)
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//
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// This library is free software; you can redistribute it and/or
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// modify it under the terms of the GNU Lesser General Public
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// License as published by the Free Software Foundation; either
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// version 2 of the License, or (at your option) any later version.
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//
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// This library is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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// Lesser General Public License for more details.
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//
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// You should have received a copy of the GNU Lesser General Public
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// License along with this library; if not, write to the Free Software
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// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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//
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/////////////////////////////////////////////////////////////////////////
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#if BX_SUPPORT_CLGD54XX
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#if BX_USE_CIRRUS_SMF
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# define BX_CIRRUS_SMF static
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# define BX_CIRRUS_THIS theSvga->
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# define BX_CIRRUS_THIS_PTR theSvga
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#else
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# define BX_CIRRUS_SMF
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# define BX_CIRRUS_THIS this->
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# define BX_CIRRUS_THIS_PTR this
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#endif // BX_USE_CIRRUS_SMF
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// 0x3b4,0x3d4
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#define VGA_CRTC_MAX 0x18
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#define CIRRUS_CRTC_MAX 0x27
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// 0x3c4
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#define VGA_SEQENCER_MAX 0x04
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#define CIRRUS_SEQENCER_MAX 0x1f
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// 0x3ce
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#define VGA_CONTROL_MAX 0x08
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#define CIRRUS_CONTROL_MAX 0x39
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// Size of internal cache memory for bitblt. (must be >= 256 and 4-byte aligned)
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#define CIRRUS_BLT_CACHESIZE (2048 * 4)
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#if BX_SUPPORT_PCI
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#define CIRRUS_VIDEO_MEMORY_MB 4
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#else
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#define CIRRUS_VIDEO_MEMORY_MB 2
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#endif
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#define CIRRUS_VIDEO_MEMORY_KB (CIRRUS_VIDEO_MEMORY_MB * 1024)
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#define CIRRUS_VIDEO_MEMORY_BYTES (CIRRUS_VIDEO_MEMORY_KB * 1024)
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typedef void (*bx_cirrus_bitblt_rop_t)(
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Bit8u *dst,const Bit8u *src,
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int dstpitch,int srcpitch,
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int bltwidth,int bltheight);
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class bx_svga_cirrus_c : public bx_vgacore_c
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{
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public:
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bx_svga_cirrus_c();
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virtual ~bx_svga_cirrus_c();
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virtual void init_vga_extension(void);
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virtual void reset(unsigned type);
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virtual void redraw_area(unsigned x0, unsigned y0,
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unsigned width, unsigned height);
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virtual Bit8u mem_read(bx_phy_address addr);
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virtual void mem_write(bx_phy_address addr, Bit8u value);
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virtual void get_text_snapshot(Bit8u **text_snapshot,
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unsigned *txHeight, unsigned *txWidth);
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virtual Bit32u get_gfx_snapshot(Bit8u **snapshot_ptr);
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virtual void register_state(void);
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virtual void after_restore_state(void);
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#if BX_SUPPORT_PCI
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virtual Bit32u pci_read_handler(Bit8u address, unsigned io_len);
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virtual void pci_write_handler(Bit8u address, Bit32u value, unsigned io_len);
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#endif
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#if BX_DEBUGGER
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virtual void debug_dump(int argc, char **argv);
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#endif
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private:
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static Bit32u svga_read_handler(void *this_ptr, Bit32u address, unsigned io_len);
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static void svga_write_handler(void *this_ptr, Bit32u address, Bit32u value, unsigned io_len);
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#if !BX_USE_CIRRUS_SMF
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Bit32u svga_read(Bit32u address, unsigned io_len);
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void svga_write(Bit32u address, Bit32u value, unsigned io_len);
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#endif
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BX_CIRRUS_SMF void mem_write_mode4and5_8bpp(Bit8u mode, Bit32u offset, Bit8u value);
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BX_CIRRUS_SMF void mem_write_mode4and5_16bpp(Bit8u mode, Bit32u offset, Bit8u value);
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static void svga_timer_handler(void *);
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static Bit64s svga_param_handler(bx_param_c *param, int set, Bit64s val);
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BX_CIRRUS_SMF void svga_timer(void);
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BX_CIRRUS_SMF void svga_modeupdate(void);
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BX_CIRRUS_SMF void svga_update(void);
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BX_CIRRUS_SMF void svga_init_members();
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BX_CIRRUS_SMF void draw_hardware_cursor(unsigned, unsigned, bx_svga_tileinfo_t *);
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// bank memory
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BX_CIRRUS_SMF void update_bank_ptr(Bit8u bank_index);
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// 0x3b4-0x3b5,0x3d4-0x3d5
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BX_CIRRUS_SMF Bit8u svga_read_crtc(Bit32u address, unsigned index);
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BX_CIRRUS_SMF void svga_write_crtc(Bit32u address, unsigned index, Bit8u value);
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// 0x3c4-0x3c5
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BX_CIRRUS_SMF Bit8u svga_read_sequencer(Bit32u address, unsigned index);
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BX_CIRRUS_SMF void svga_write_sequencer(Bit32u address, unsigned index, Bit8u value);
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// 0x3ce-0x3cf
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BX_CIRRUS_SMF Bit8u svga_read_control(Bit32u address, unsigned index);
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BX_CIRRUS_SMF void svga_write_control(Bit32u address, unsigned index, Bit8u value);
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// memory-mapped I/O
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BX_CIRRUS_SMF Bit8u svga_mmio_vga_read(Bit32u address);
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BX_CIRRUS_SMF void svga_mmio_vga_write(Bit32u address,Bit8u value);
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BX_CIRRUS_SMF Bit8u svga_mmio_blt_read(Bit32u address);
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BX_CIRRUS_SMF void svga_mmio_blt_write(Bit32u address,Bit8u value);
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BX_CIRRUS_SMF void svga_reset_bitblt(void);
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BX_CIRRUS_SMF void svga_bitblt();
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BX_CIRRUS_SMF void svga_colorexpand(Bit8u *dst,const Bit8u *src,int count,int pixelwidth);
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#if BX_USE_CIRRUS_SMF
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#define svga_colorexpand_8_static svga_colorexpand_8
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#define svga_colorexpand_16_static svga_colorexpand_16
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#define svga_colorexpand_24_static svga_colorexpand_24
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#define svga_colorexpand_32_static svga_colorexpand_32
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#else
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static void svga_colorexpand_8_static(void *this_ptr,Bit8u *dst,const Bit8u *src,int count);
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static void svga_colorexpand_16_static(void *this_ptr,Bit8u *dst,const Bit8u *src,int count);
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static void svga_colorexpand_24_static(void *this_ptr,Bit8u *dst,const Bit8u *src,int count);
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static void svga_colorexpand_32_static(void *this_ptr,Bit8u *dst,const Bit8u *src,int count);
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#endif
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BX_CIRRUS_SMF void svga_colorexpand_8(Bit8u *dst,const Bit8u *src,int count);
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BX_CIRRUS_SMF void svga_colorexpand_16(Bit8u *dst,const Bit8u *src,int count);
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BX_CIRRUS_SMF void svga_colorexpand_24(Bit8u *dst,const Bit8u *src,int count);
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BX_CIRRUS_SMF void svga_colorexpand_32(Bit8u *dst,const Bit8u *src,int count);
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BX_CIRRUS_SMF void svga_setup_bitblt_cputovideo(Bit32u dstaddr,Bit32u srcaddr);
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BX_CIRRUS_SMF void svga_setup_bitblt_videotocpu(Bit32u dstaddr,Bit32u srcaddr);
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BX_CIRRUS_SMF void svga_setup_bitblt_videotovideo(Bit32u dstaddr,Bit32u srcaddr);
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#if BX_USE_CIRRUS_SMF == 0
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static void svga_patterncopy_static(void *this_ptr);
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static void svga_simplebitblt_static(void *this_ptr);
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static void svga_solidfill_static(void *this_ptr);
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static void svga_patterncopy_memsrc_static(void *this_ptr);
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static void svga_simplebitblt_memsrc_static(void *this_ptr);
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static void svga_colorexpand_transp_memsrc_static(void *this_ptr);
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#else
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#define svga_patterncopy_static svga_patterncopy
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#define svga_simplebitblt_static svga_simplebitblt
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#define svga_solidfill_static svga_solidfill
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#define svga_patterncopy_memsrc_static svga_patterncopy_memsrc
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#define svga_simplebitblt_memsrc_static svga_simplebitblt_memsrc
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#define svga_colorexpand_transp_memsrc_static svga_colorexpand_transp_memsrc
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#endif
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BX_CIRRUS_SMF void svga_patterncopy();
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BX_CIRRUS_SMF void svga_simplebitblt();
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BX_CIRRUS_SMF void svga_solidfill();
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BX_CIRRUS_SMF void svga_patterncopy_memsrc();
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BX_CIRRUS_SMF void svga_simplebitblt_memsrc();
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BX_CIRRUS_SMF void svga_colorexpand_transp_memsrc();
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BX_CIRRUS_SMF bx_bool svga_asyncbitblt_next();
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BX_CIRRUS_SMF bx_cirrus_bitblt_rop_t svga_get_fwd_rop_handler(Bit8u rop);
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BX_CIRRUS_SMF bx_cirrus_bitblt_rop_t svga_get_bkwd_rop_handler(Bit8u rop);
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struct {
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Bit8u index;
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Bit8u reg[CIRRUS_CRTC_MAX+1];
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} crtc; // 0x3b4-5/0x3d4-5
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struct {
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Bit8u index;
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Bit8u reg[CIRRUS_SEQENCER_MAX+1];
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} sequencer; // 0x3c4-5
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struct {
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Bit8u index;
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Bit8u reg[CIRRUS_CONTROL_MAX+1];
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Bit8u shadow_reg0;
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Bit8u shadow_reg1;
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} control; // 0x3ce-f
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struct {
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unsigned lockindex;
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Bit8u data;
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Bit8u palette[48];
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} hidden_dac; // 0x3c6
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bx_bool svga_unlock_special;
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bx_bool svga_needs_update_tile;
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bx_bool svga_needs_update_dispentire;
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bx_bool svga_needs_update_mode;
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unsigned svga_xres;
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unsigned svga_yres;
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unsigned svga_pitch;
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unsigned svga_bpp;
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unsigned svga_dispbpp;
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Bit32u bank_base[2];
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Bit32u bank_limit[2];
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Bit8u *disp_ptr;
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struct {
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bx_cirrus_bitblt_rop_t rop_handler;
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int pixelwidth;
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int bltwidth;
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int bltheight;
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int dstpitch;
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int srcpitch;
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Bit8u bltmode;
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Bit8u bltmodeext;
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Bit8u bltrop;
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Bit8u *dst;
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const Bit8u *src;
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Bit32u srcaddr;
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#if BX_USE_CIRRUS_SMF
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void (*bitblt_ptr)();
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#else
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void (*bitblt_ptr)(void *this_ptr);
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#endif
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Bit8u *memsrc_ptr; // CPU -> video
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Bit8u *memsrc_endptr;
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int memsrc_needed;
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Bit8u *memdst_ptr; // video -> CPU
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Bit8u *memdst_endptr;
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int memdst_bytesperline;
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int memdst_needed;
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Bit8u memsrc[CIRRUS_BLT_CACHESIZE];
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Bit8u memdst[CIRRUS_BLT_CACHESIZE];
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} bitblt;
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struct {
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Bit16u x, y, size;
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} hw_cursor;
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struct {
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Bit16u x, y, w, h;
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} redraw;
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bx_bool is_unlocked() { return svga_unlock_special; }
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bx_bool banking_granularity_is_16k() { return !!(control.reg[0x0B] & 0x20); }
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bx_bool banking_is_dual() { return !!(control.reg[0x0B] & 0x01); }
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#if BX_SUPPORT_PCI
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BX_CIRRUS_SMF void svga_init_pcihandlers(void);
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BX_CIRRUS_SMF bx_bool cirrus_mem_read_handler(bx_phy_address addr, unsigned len, void *data, void *param);
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BX_CIRRUS_SMF bx_bool cirrus_mem_write_handler(bx_phy_address addr, unsigned len, void *data, void *param);
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#endif
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};
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#endif // BX_SUPPORT_CLGD54XX
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