f90e5f4f44
Only missing items (to be added soon): - Supervisor Shadow Stack EPT Control is not implemented yet - SMM placing for SSP Currently have to be added manually to some CPUID model, for example to ICL-U To enable configure with --enable-cet
77 lines
2.2 KiB
Plaintext
77 lines
2.2 KiB
Plaintext
TODO (know issues in CPU model):
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-------------------------------
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[!] The following 3DNow! instructions still not implemented:
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PF2IW_PqQq
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PFNACC_PqQq
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PFPNACC_PqQq
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PFCMPGE_PqQq
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PFCMPGT_PqQq
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PFCMPEQ_PqQq
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PFMIN_PqQq
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PFMAX_PqQq
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PFRCP_PqQq
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PFRSQRT_PqQq
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PFSUB_PqQq
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PFSUBR_PqQq
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PFADD_PqQq
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PFACC_PqQq,
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PFMUL_PqQq
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PFRCPIT1_PqQq
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PFRSQIT1_PqQq
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PFRCPIT2_PqQq
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[!] CPUID does not report 3DNow! instruction set
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[!] Some of APIC functionality still not implemented, for example
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- LVT pins handling
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- Filter interrupts according processor priority (PPR)
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[!] REP NOP is PAUSE (on P4/XEON)
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When running in SMP mode, this means that we are in a spin loop.
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This processor should yield to the other one, as we are anyhow waiting
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for a lock, and any other processor is responsible for this.
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[!] 32-bit linear address wrap when executing in legacy mode might be
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not implemented correctly for system memory accesses (like descriptor
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tables and etc)
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[!] AMD and Intel x86_64 implementations are different.
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Currently Bochs emulation is according to Intel version.
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Do we need to support both ?
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[!] VMX:
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- Dual-monitor treatment of SMIs and SMM not implemented yet
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- Posted Interrupts Processing is not implemented yet
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- MTF is not implemented yet
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[!] SVM:
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- Decoding assists, pause filter, VMCB clean are not implemented yet
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- Advanced Virtual Interrupt Controller (AVIC) not implemented yet
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- More?
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[!] AMD misaligned SSE mode should convert #GP on misaligned SSE access to #AC
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exception when #AC is enabled
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[!] TODO: Convert CPUDB to plugins and search for them in runtime
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[!] TODO: Find a way to implement HLE and RTM extensions
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------------------------------------------------------------------------------------
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[!] No plans for MPX, Intel Processor Trace, LWP.
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Their emulation would greatly affect emulation performance.
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Could be implemented through instrumentation if ***really*** needed.
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------------------------------------------------------------------------------------
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[!]: Some system operations have to be done atomically.
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This is the list for future reference:
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- A/D bit update in page table
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- A bit update in segment descriptor
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- BUSY bit in TSS
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- Busy bit in shadow stack
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- RSTORSSP
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