1078 lines
36 KiB
C++
1078 lines
36 KiB
C++
/////////////////////////////////////////////////////////////////////////
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// $Id: exception.cc,v 1.49 2005-03-03 20:24:52 sshwarts Exp $
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/////////////////////////////////////////////////////////////////////////
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//
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// Copyright (C) 2001 MandrakeSoft S.A.
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//
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// MandrakeSoft S.A.
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// 43, rue d'Aboukir
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// 75002 Paris - France
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// http://www.linux-mandrake.com/
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// http://www.mandrakesoft.com/
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//
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// This library is free software; you can redistribute it and/or
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// modify it under the terms of the GNU Lesser General Public
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// License as published by the Free Software Foundation; either
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// version 2 of the License, or (at your option) any later version.
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//
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// This library is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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// Lesser General Public License for more details.
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//
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// You should have received a copy of the GNU Lesser General Public
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// License along with this library; if not, write to the Free Software
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// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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#define NEED_CPU_REG_SHORTCUTS 1
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#include "bochs.h"
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#include "iodev/iodev.h"
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#define LOG_THIS BX_CPU_THIS_PTR
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/* Exception classes. These are used as indexes into the 'is_exception_OK'
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* array below, and are stored in the 'exception' array also
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*/
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#define BX_ET_BENIGN 0
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#define BX_ET_CONTRIBUTORY 1
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#define BX_ET_PAGE_FAULT 2
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#define BX_ET_DOUBLE_FAULT 10
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static const bx_bool is_exception_OK[3][3] = {
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{ 1, 1, 1 }, /* 1st exception is BENIGN */
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{ 1, 0, 1 }, /* 1st exception is CONTRIBUTORY */
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{ 1, 0, 0 } /* 1st exception is PAGE_FAULT */
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};
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void BX_CPU_C::interrupt(Bit8u vector, bx_bool is_INT, bx_bool is_error_code, Bit16u error_code)
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{
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#if BX_DEBUGGER
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if (bx_guard.special_unwind_stack) {
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BX_INFO (("interrupt() returning early because special_unwind_stack is set"));
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return;
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}
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BX_CPU_THIS_PTR show_flag |= Flag_intsig;
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#if BX_DEBUG_LINUX
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if (bx_dbg.linux_syscall) {
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if (vector == 0x80) bx_dbg_linux_syscall ();
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}
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#endif
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#endif
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//BX_DEBUG(( "::interrupt(%u)", vector ));
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BX_INSTR_INTERRUPT(BX_CPU_ID, vector);
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invalidate_prefetch_q();
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// Discard any traps and inhibits for new context; traps will
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// resume upon return.
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BX_CPU_THIS_PTR debug_trap = 0;
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BX_CPU_THIS_PTR inhibit_mask = 0;
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#if BX_CPU_LEVEL >= 2
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// unsigned prev_errno;
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BX_DEBUG(("interrupt(): vector = %u, INT = %u, EXT = %u",
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(unsigned) vector, (unsigned) is_INT, (unsigned) BX_CPU_THIS_PTR EXT));
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BX_CPU_THIS_PTR save_cs = BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS];
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BX_CPU_THIS_PTR save_ss = BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS];
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BX_CPU_THIS_PTR save_eip = EIP;
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BX_CPU_THIS_PTR save_esp = ESP;
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// prev_errno = BX_CPU_THIS_PTR errorno;
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#if BX_SUPPORT_X86_64
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if (BX_CPU_THIS_PTR msr.lma)
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{
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// long mode interrupt
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Bit64u idtindex;
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Bit32u dword1, dword2, dword3;
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bx_descriptor_t gate_descriptor, cs_descriptor;
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bx_selector_t cs_selector;
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Bit16u gate_dest_selector;
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Bit64u gate_dest_offset;
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unsigned ist;
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// interrupt vector must be within IDT table limits,
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// else #GP(vector number*16 + 2 + EXT)
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idtindex = vector*16;
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if ( (idtindex + 15) > BX_CPU_THIS_PTR idtr.limit) {
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BX_DEBUG(("IDT.limit = %04x", (unsigned) BX_CPU_THIS_PTR idtr.limit));
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BX_DEBUG(("IDT.base = %06x", (unsigned) BX_CPU_THIS_PTR idtr.base));
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BX_DEBUG(("interrupt vector must be within IDT table limits"));
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BX_DEBUG(("bailing"));
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BX_DEBUG(("interrupt(): vector > idtr.limit"));
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exception(BX_GP_EXCEPTION, vector*16 + 2, 0);
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}
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// descriptor AR byte must indicate interrupt gate, trap gate,
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// or task gate, else #GP(vector*8 + 2 + EXT)
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idtindex += BX_CPU_THIS_PTR idtr.base;
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access_linear(idtindex, 4, 0, BX_READ, &dword1);
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access_linear(idtindex + 4, 4, 0, BX_READ, &dword2);
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access_linear(idtindex + 8, 4, 0, BX_READ, &dword3);
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parse_descriptor(dword1, dword2, &gate_descriptor);
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if ((gate_descriptor.valid==0) || gate_descriptor.segment)
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{
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BX_DEBUG(("interrupt(): gate descriptor is not valid sys seg"));
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exception(BX_GP_EXCEPTION, vector*8 + 2, 0);
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}
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switch (gate_descriptor.type) {
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//case BX_TASK_GATE:
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//case BX_286_INTERRUPT_GATE:
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//case BX_286_TRAP_GATE:
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case BX_386_INTERRUPT_GATE:
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case BX_386_TRAP_GATE:
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break;
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default:
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BX_DEBUG(("interrupt(): gate.type(%u) != {5,6,7,14,15}",
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(unsigned) gate_descriptor.type));
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exception(BX_GP_EXCEPTION, vector*8 + 2, 0);
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return;
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}
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// if software interrupt, then gate descripor DPL must be >= CPL,
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// else #GP(vector * 8 + 2 + EXT)
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if (is_INT && (gate_descriptor.dpl < CPL))
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{
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BX_DEBUG(("interrupt(): is_INT && (dpl < CPL)"));
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exception(BX_GP_EXCEPTION, vector*8 + 2, 0);
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return;
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}
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// Gate must be present, else #NP(vector * 8 + 2 + EXT)
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if (gate_descriptor.p == 0) {
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BX_DEBUG(("interrupt(): p == 0"));
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exception(BX_NP_EXCEPTION, vector*8 + 2, 0);
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}
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gate_dest_selector = gate_descriptor.u.gate386.dest_selector;
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gate_dest_offset = ((Bit64u)dword3 << 32) +
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gate_descriptor.u.gate386.dest_offset;
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ist = gate_descriptor.u.gate386.dword_count & 0x7;
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// examine CS selector and descriptor given in gate descriptor
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// selector must be non-null else #GP(EXT)
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if ( (gate_dest_selector & 0xfffc) == 0 ) {
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BX_PANIC(("int_trap_gate(): selector null"));
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exception(BX_GP_EXCEPTION, 0, 0);
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}
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parse_selector(gate_dest_selector, &cs_selector);
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// selector must be within its descriptor table limits
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// else #GP(selector+EXT)
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fetch_raw_descriptor(&cs_selector, &dword1, &dword2,
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BX_GP_EXCEPTION);
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parse_descriptor(dword1, dword2, &cs_descriptor);
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// descriptor AR byte must indicate code seg
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// and code segment descriptor DPL<=CPL, else #GP(selector+EXT)
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if ( cs_descriptor.valid==0 ||
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cs_descriptor.segment==0 ||
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cs_descriptor.u.segment.executable==0 ||
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cs_descriptor.dpl>CPL)
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{
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BX_DEBUG(("interrupt(): not code segment"));
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exception(BX_GP_EXCEPTION, cs_selector.value & 0xfffc, 0);
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}
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// check that it's a 64 bit segment
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if ( cs_descriptor.u.segment.l == 0 ||
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cs_descriptor.u.segment.d_b == 1)
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{
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BX_DEBUG(("interrupt(): must be 64 bit segment"));
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exception(BX_GP_EXCEPTION, vector, 0);
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}
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// segment must be present, else #NP(selector + EXT)
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if ( cs_descriptor.p==0 ) {
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BX_DEBUG(("interrupt(): segment not present"));
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exception(BX_NP_EXCEPTION, cs_selector.value & 0xfffc, 0);
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}
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// if code segment is non-conforming and DPL < CPL then
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// INTERRUPT TO INNER PRIVILEGE:
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if ((cs_descriptor.u.segment.c_ed==0 && cs_descriptor.dpl<CPL) || (ist > 0))
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{
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Bit16u old_SS;
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Bit64u RSP_for_cpl_x, old_RSP;
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bx_descriptor_t ss_descriptor;
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bx_selector_t ss_selector;
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int savemode;
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BX_DEBUG(("interrupt(): INTERRUPT TO INNER PRIVILEGE"));
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// check selector and descriptor for new stack in current TSS
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if (ist > 0) {
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BX_DEBUG(("trap to IST, vector = %d\n",ist));
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get_RSP_from_TSS(ist+3,&RSP_for_cpl_x);
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}
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else {
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get_RSP_from_TSS(cs_descriptor.dpl,&RSP_for_cpl_x);
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}
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// set up a null descriptor
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parse_selector(0,&ss_selector);
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parse_descriptor(0,0,&ss_descriptor);
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// 386 int/trap gate
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// new stack must have room for 40|48 bytes, else #SS(0)
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//if ( is_error_code )
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// bytes = 48;
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//else
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// bytes = 40;
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old_SS = BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].selector.value;
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old_RSP = RSP;
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// load new RSP values from TSS
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savemode = BX_CPU_THIS_PTR cpu_mode;
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BX_CPU_THIS_PTR cpu_mode = BX_MODE_LONG_64;
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// need to switch to 64 bit mode temporarily here.
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// this means that any exception after here might be delivered
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// a little insanely. Like faults are page faults..
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load_ss(&ss_selector, &ss_descriptor, cs_descriptor.dpl);
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RSP = RSP_for_cpl_x;
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// load new CS:IP values from gate
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// set CPL to new code segment DPL
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CPL = cs_descriptor.dpl;
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// set RPL of CS to CPL
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// push long pointer to old stack onto new stack
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// align ESP
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push_64(old_SS);
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push_64(old_RSP);
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// push EFLAGS
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push_64(read_eflags());
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// push long pointer to return address onto new stack
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push_64(BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].selector.value);
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push_64(RIP);
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if ( is_error_code )
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push_64(error_code);
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BX_CPU_THIS_PTR cpu_mode = savemode;
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load_cs(&cs_selector, &cs_descriptor, cs_descriptor.dpl);
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RIP = gate_dest_offset;
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// if INTERRUPT GATE set IF to 0
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if ( !(gate_descriptor.type & 1) ) // even is int-gate
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BX_CPU_THIS_PTR clear_IF ();
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BX_CPU_THIS_PTR clear_TF ();
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BX_CPU_THIS_PTR clear_VM ();
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BX_CPU_THIS_PTR clear_RF ();
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BX_CPU_THIS_PTR clear_NT ();
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return;
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}
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// if code segment is conforming OR code segment DPL = CPL then
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// INTERRUPT TO SAME PRIVILEGE LEVEL:
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if (cs_descriptor.u.segment.c_ed==1 || cs_descriptor.dpl==CPL)
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{
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BX_DEBUG(("int_trap_gate286(): INTERRUPT TO SAME PRIVILEGE"));
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Bit64u old_RSP = RSP;
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// align stack
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RSP = RSP & BX_CONST64(0xfffffffffffffff0);
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// push flags onto stack
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// push current CS selector onto stack
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// push return offset onto stack
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push_64(BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].selector.value);
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push_64(old_RSP);
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push_64(read_eflags());
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push_64(BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].selector.value);
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push_64(RIP);
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if ( is_error_code )
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push_64(error_code);
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// load CS:IP from gate
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// load CS descriptor
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// set the RPL field of CS to CPL
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load_cs(&cs_selector, &cs_descriptor, CPL);
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RIP = gate_dest_offset;
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// if interrupt gate then set IF to 0
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if ( !(gate_descriptor.type & 1) ) // even is int-gate
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BX_CPU_THIS_PTR clear_IF ();
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BX_CPU_THIS_PTR clear_TF ();
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BX_CPU_THIS_PTR clear_VM ();
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BX_CPU_THIS_PTR clear_RF ();
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BX_CPU_THIS_PTR clear_NT ();
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return;
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}
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// else #GP(CS selector + ext)
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BX_DEBUG(("interrupt: bad descriptor"));
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BX_DEBUG(("c_ed=%u, descriptor.dpl=%u, CPL=%u",
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(unsigned) cs_descriptor.u.segment.c_ed,
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(unsigned) cs_descriptor.dpl,
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(unsigned) CPL));
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BX_DEBUG(("cs.segment = %u", (unsigned) cs_descriptor.segment));
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exception(BX_GP_EXCEPTION, cs_selector.value & 0xfffc, 0);
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}
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else
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#endif // #if BX_SUPPORT_X86_64
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if(!real_mode()) {
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Bit32u dword1, dword2;
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bx_descriptor_t gate_descriptor, cs_descriptor;
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bx_selector_t cs_selector;
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Bit16u raw_tss_selector;
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bx_selector_t tss_selector;
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bx_descriptor_t tss_descriptor;
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Bit16u gate_dest_selector;
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Bit32u gate_dest_offset;
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// interrupt vector must be within IDT table limits,
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// else #GP(vector number*8 + 2 + EXT)
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if ( (vector*8 + 7) > BX_CPU_THIS_PTR idtr.limit) {
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BX_DEBUG(("IDT.limit = %04x", (unsigned) BX_CPU_THIS_PTR idtr.limit));
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BX_DEBUG(("IDT.base = %06x", (unsigned) BX_CPU_THIS_PTR idtr.base));
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BX_DEBUG(("interrupt vector must be within IDT table limits"));
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BX_DEBUG(("bailing"));
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BX_DEBUG(("interrupt(): vector > idtr.limit"));
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exception(BX_GP_EXCEPTION, vector*8 + 2, 0);
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}
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// descriptor AR byte must indicate interrupt gate, trap gate,
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// or task gate, else #GP(vector*8 + 2 + EXT)
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access_linear(BX_CPU_THIS_PTR idtr.base + vector*8, 4, 0,
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BX_READ, &dword1);
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access_linear(BX_CPU_THIS_PTR idtr.base + vector*8 + 4, 4, 0,
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BX_READ, &dword2);
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parse_descriptor(dword1, dword2, &gate_descriptor);
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if ((gate_descriptor.valid==0) || gate_descriptor.segment) {
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BX_DEBUG(("interrupt(): gate descriptor is not valid sys seg"));
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exception(BX_GP_EXCEPTION, vector*8 + 2, 0);
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}
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switch (gate_descriptor.type) {
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case BX_TASK_GATE:
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case BX_286_INTERRUPT_GATE:
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case BX_286_TRAP_GATE:
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case BX_386_INTERRUPT_GATE:
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case BX_386_TRAP_GATE:
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break;
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default:
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BX_DEBUG(("interrupt(): gate.type(%u) != {5,6,7,14,15}",
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(unsigned) gate_descriptor.type));
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exception(BX_GP_EXCEPTION, vector*8 + 2, 0);
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return;
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}
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// if software interrupt, then gate descripor DPL must be >= CPL,
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// else #GP(vector * 8 + 2 + EXT)
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if (is_INT && (gate_descriptor.dpl < CPL)) {
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BX_DEBUG(("interrupt(): is_INT && (dpl < CPL)"));
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exception(BX_GP_EXCEPTION, vector*8 + 2, 0);
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}
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// Gate must be present, else #NP(vector * 8 + 2 + EXT)
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if (gate_descriptor.p == 0) {
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BX_DEBUG(("interrupt(): gate not present"));
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exception(BX_NP_EXCEPTION, vector*8 + 2, 0);
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}
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switch (gate_descriptor.type) {
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case BX_TASK_GATE:
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// examine selector to TSS, given in task gate descriptor
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raw_tss_selector = gate_descriptor.u.taskgate.tss_selector;
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parse_selector(raw_tss_selector, &tss_selector);
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// must specify global in the local/global bit,
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// else #TS(TSS selector)
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// +++
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// 486/Pent books say #TSS(selector)
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// PPro+ says #GP(selector)
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if (tss_selector.ti) {
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BX_PANIC(("interrupt: tss_selector.ti=1"));
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exception(BX_TS_EXCEPTION, raw_tss_selector & 0xfffc, 0);
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return;
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}
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// index must be within GDT limits, else #TS(TSS selector)
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fetch_raw_descriptor(&tss_selector, &dword1, &dword2, BX_TS_EXCEPTION);
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// AR byte must specify available TSS,
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// else #TS(TSS selector)
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parse_descriptor(dword1, dword2, &tss_descriptor);
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if (tss_descriptor.valid==0 || tss_descriptor.segment) {
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BX_PANIC(("exception: TSS selector points to bad TSS"));
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exception(BX_TS_EXCEPTION, raw_tss_selector & 0xfffc, 0);
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return;
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}
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if (tss_descriptor.type!=9 && tss_descriptor.type!=1) {
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BX_PANIC(("exception: TSS selector points to bad TSS"));
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exception(BX_TS_EXCEPTION, raw_tss_selector & 0xfffc, 0);
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return;
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}
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// TSS must be present, else #NP(TSS selector)
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// done in task_switch()
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// switch tasks with nesting to TSS
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task_switch(&tss_selector, &tss_descriptor,
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BX_TASK_FROM_CALL_OR_INT, dword1, dword2);
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// if interrupt was caused by fault with error code
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// stack limits must allow push of 2 more bytes, else #SS(0)
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// push error code onto stack
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//??? push_16 vs push_32
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if ( is_error_code ) {
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//if (tss_descriptor.type==9)
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if (BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.u.segment.d_b)
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push_32(error_code);
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else
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push_16(error_code);
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}
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// instruction pointer must be in CS limit, else #GP(0)
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if (EIP > BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.u.segment.limit_scaled) {
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BX_ERROR(("exception(): EIP > CS.limit"));
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exception(BX_GP_EXCEPTION, 0, 0);
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}
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return;
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|
case BX_286_INTERRUPT_GATE:
|
|
case BX_286_TRAP_GATE:
|
|
case BX_386_INTERRUPT_GATE:
|
|
case BX_386_TRAP_GATE:
|
|
if ( gate_descriptor.type >= 14 ) { // 386 gate
|
|
gate_dest_selector = gate_descriptor.u.gate386.dest_selector;
|
|
gate_dest_offset = gate_descriptor.u.gate386.dest_offset;
|
|
}
|
|
else { // 286 gate
|
|
gate_dest_selector = gate_descriptor.u.gate286.dest_selector;
|
|
gate_dest_offset = gate_descriptor.u.gate286.dest_offset;
|
|
}
|
|
|
|
// examine CS selector and descriptor given in gate descriptor
|
|
// selector must be non-null else #GP(EXT)
|
|
if ( (gate_dest_selector & 0xfffc) == 0 ) {
|
|
BX_PANIC(("int_trap_gate(): selector null"));
|
|
exception(BX_GP_EXCEPTION, 0, 0);
|
|
}
|
|
|
|
parse_selector(gate_dest_selector, &cs_selector);
|
|
|
|
// selector must be within its descriptor table limits
|
|
// else #GP(selector+EXT)
|
|
fetch_raw_descriptor(&cs_selector, &dword1, &dword2, BX_GP_EXCEPTION);
|
|
parse_descriptor(dword1, dword2, &cs_descriptor);
|
|
|
|
// descriptor AR byte must indicate code seg
|
|
// and code segment descriptor DPL<=CPL, else #GP(selector+EXT)
|
|
if ( cs_descriptor.valid==0 ||
|
|
cs_descriptor.segment==0 ||
|
|
cs_descriptor.u.segment.executable==0 ||
|
|
cs_descriptor.dpl>CPL )
|
|
{
|
|
BX_DEBUG(("interrupt(): not code segment"));
|
|
exception(BX_GP_EXCEPTION, cs_selector.value & 0xfffc, 0);
|
|
}
|
|
|
|
// segment must be present, else #NP(selector + EXT)
|
|
if ( cs_descriptor.p==0 ) {
|
|
BX_DEBUG(("interrupt(): segment not present"));
|
|
exception(BX_NP_EXCEPTION, cs_selector.value & 0xfffc, 0);
|
|
}
|
|
|
|
// if code segment is non-conforming and DPL < CPL then
|
|
// INTERRUPT TO INNER PRIVILEGE:
|
|
if ( cs_descriptor.u.segment.c_ed==0 && cs_descriptor.dpl<CPL )
|
|
{
|
|
Bit16u old_SS, old_CS, SS_for_cpl_x;
|
|
Bit32u ESP_for_cpl_x, old_EIP, old_ESP;
|
|
bx_descriptor_t ss_descriptor;
|
|
bx_selector_t ss_selector;
|
|
int bytes;
|
|
|
|
int is_v8086_mode = v8086_mode();
|
|
|
|
BX_DEBUG(("interrupt(): INTERRUPT TO INNER PRIVILEGE"));
|
|
|
|
if (is_v8086_mode && cs_descriptor.dpl != 0) {
|
|
// if code segment DPL != 0 then #GP(new code segment selector)
|
|
exception(BX_GP_EXCEPTION, cs_selector.value & 0xfffc, 0);
|
|
}
|
|
|
|
// check selector and descriptor for new stack in current TSS
|
|
get_SS_ESP_from_TSS(cs_descriptor.dpl,
|
|
&SS_for_cpl_x, &ESP_for_cpl_x);
|
|
|
|
// Selector must be non-null else #TS(EXT)
|
|
if ( (SS_for_cpl_x & 0xfffc) == 0 ) {
|
|
BX_PANIC(("interrupt(): SS selector null"));
|
|
/* TS(ext) */
|
|
exception(BX_TS_EXCEPTION, 0, 0);
|
|
}
|
|
|
|
// selector index must be within its descriptor table limits
|
|
// else #TS(SS selector + EXT)
|
|
parse_selector(SS_for_cpl_x, &ss_selector);
|
|
// fetch 2 dwords of descriptor; call handles out of limits checks
|
|
fetch_raw_descriptor(&ss_selector, &dword1, &dword2, BX_TS_EXCEPTION);
|
|
parse_descriptor(dword1, dword2, &ss_descriptor);
|
|
|
|
// selector rpl must = dpl of code segment,
|
|
// else #TS(SS selector + ext)
|
|
if (ss_selector.rpl != cs_descriptor.dpl) {
|
|
BX_PANIC(("interrupt(): SS.rpl != CS.dpl"));
|
|
exception(BX_TS_EXCEPTION, SS_for_cpl_x & 0xfffc, 0);
|
|
}
|
|
|
|
// stack seg DPL must = DPL of code segment,
|
|
// else #TS(SS selector + ext)
|
|
if (ss_descriptor.dpl != cs_descriptor.dpl) {
|
|
BX_PANIC(("interrupt(): SS.dpl != CS.dpl"));
|
|
exception(BX_TS_EXCEPTION, SS_for_cpl_x & 0xfffc, 0);
|
|
}
|
|
|
|
// descriptor must indicate writable data segment,
|
|
// else #TS(SS selector + EXT)
|
|
if (ss_descriptor.valid==0 ||
|
|
ss_descriptor.segment==0 ||
|
|
ss_descriptor.u.segment.executable==1 ||
|
|
ss_descriptor.u.segment.r_w==0)
|
|
{
|
|
BX_PANIC(("interrupt(): SS not writable data segment"));
|
|
exception(BX_TS_EXCEPTION, SS_for_cpl_x & 0xfffc, 0);
|
|
}
|
|
|
|
// seg must be present, else #SS(SS selector + ext)
|
|
if (ss_descriptor.p==0) {
|
|
BX_PANIC(("interrupt(): SS not present"));
|
|
exception(BX_SS_EXCEPTION, SS_for_cpl_x & 0xfffc, 0);
|
|
}
|
|
|
|
if (gate_descriptor.type>=14) {
|
|
// 386 int/trap gate
|
|
// new stack must have room for 20|24 bytes, else #SS(0)
|
|
if ( is_error_code )
|
|
bytes = 24;
|
|
else
|
|
bytes = 20;
|
|
if (is_v8086_mode)
|
|
bytes += 16;
|
|
}
|
|
else {
|
|
// new stack must have room for 10|12 bytes, else #SS(0)
|
|
if ( is_error_code )
|
|
bytes = 12;
|
|
else
|
|
bytes = 10;
|
|
if (is_v8086_mode) {
|
|
bytes += 8;
|
|
BX_PANIC(("interrupt: int/trap gate VM"));
|
|
}
|
|
}
|
|
|
|
// new stack must have enough room, else #SS(seg selector)
|
|
if ( !can_push(&ss_descriptor, ESP_for_cpl_x, bytes) )
|
|
{
|
|
BX_DEBUG(("interrupt(): new stack doesn't have room for %u bytes", (unsigned) bytes));
|
|
exception(BX_SS_EXCEPTION, SS_for_cpl_x & 0xfffc, 0);
|
|
}
|
|
|
|
// IP must be within CS segment boundaries, else #GP(0)
|
|
if (gate_dest_offset > cs_descriptor.u.segment.limit_scaled) {
|
|
BX_DEBUG(("interrupt(): gate EIP > CS.limit"));
|
|
exception(BX_GP_EXCEPTION, 0, 0);
|
|
}
|
|
|
|
old_ESP = ESP;
|
|
old_SS = BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].selector.value;
|
|
old_EIP = EIP;
|
|
old_CS = BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].selector.value;
|
|
|
|
// load new SS:SP values from TSS
|
|
load_ss(&ss_selector, &ss_descriptor, cs_descriptor.dpl);
|
|
|
|
if (ss_descriptor.u.segment.d_b)
|
|
ESP = ESP_for_cpl_x;
|
|
else
|
|
SP = ESP_for_cpl_x; // leave upper 16bits
|
|
|
|
// load new CS:IP values from gate
|
|
// set CPL to new code segment DPL
|
|
// set RPL of CS to CPL
|
|
load_cs(&cs_selector, &cs_descriptor, cs_descriptor.dpl);
|
|
EIP = gate_dest_offset;
|
|
|
|
Bit32u eflags = read_eflags();
|
|
|
|
// if INTERRUPT GATE set IF to 0
|
|
if ( !(gate_descriptor.type & 1) ) // even is int-gate
|
|
BX_CPU_THIS_PTR clear_IF ();
|
|
BX_CPU_THIS_PTR clear_TF ();
|
|
BX_CPU_THIS_PTR clear_VM ();
|
|
BX_CPU_THIS_PTR clear_RF ();
|
|
BX_CPU_THIS_PTR clear_NT ();
|
|
|
|
if (is_v8086_mode)
|
|
{
|
|
if (gate_descriptor.type>=14) { // 386 int/trap gate
|
|
push_32(BX_CPU_THIS_PTR sregs[BX_SEG_REG_GS].selector.value);
|
|
push_32(BX_CPU_THIS_PTR sregs[BX_SEG_REG_FS].selector.value);
|
|
push_32(BX_CPU_THIS_PTR sregs[BX_SEG_REG_DS].selector.value);
|
|
push_32(BX_CPU_THIS_PTR sregs[BX_SEG_REG_ES].selector.value);
|
|
}
|
|
else {
|
|
push_16(BX_CPU_THIS_PTR sregs[BX_SEG_REG_GS].selector.value);
|
|
push_16(BX_CPU_THIS_PTR sregs[BX_SEG_REG_FS].selector.value);
|
|
push_16(BX_CPU_THIS_PTR sregs[BX_SEG_REG_DS].selector.value);
|
|
push_16(BX_CPU_THIS_PTR sregs[BX_SEG_REG_ES].selector.value);
|
|
}
|
|
|
|
BX_CPU_THIS_PTR sregs[BX_SEG_REG_GS].cache.valid = 0;
|
|
BX_CPU_THIS_PTR sregs[BX_SEG_REG_GS].selector.value = 0;
|
|
BX_CPU_THIS_PTR sregs[BX_SEG_REG_FS].cache.valid = 0;
|
|
BX_CPU_THIS_PTR sregs[BX_SEG_REG_FS].selector.value = 0;
|
|
BX_CPU_THIS_PTR sregs[BX_SEG_REG_DS].cache.valid = 0;
|
|
BX_CPU_THIS_PTR sregs[BX_SEG_REG_DS].selector.value = 0;
|
|
BX_CPU_THIS_PTR sregs[BX_SEG_REG_ES].cache.valid = 0;
|
|
BX_CPU_THIS_PTR sregs[BX_SEG_REG_ES].selector.value = 0;
|
|
}
|
|
|
|
if (gate_descriptor.type>=14) { // 386 int/trap gate
|
|
// push long pointer to old stack onto new stack
|
|
push_32(old_SS);
|
|
push_32(old_ESP);
|
|
|
|
// push EFLAGS
|
|
push_32(eflags);
|
|
|
|
// push long pointer to return address onto new stack
|
|
push_32(old_CS);
|
|
push_32(old_EIP);
|
|
|
|
if ( is_error_code )
|
|
push_32(error_code);
|
|
}
|
|
else { // 286 int/trap gate
|
|
// push long pointer to old stack onto new stack
|
|
push_16(old_SS);
|
|
push_16(old_ESP); // ignores upper 16bits
|
|
|
|
// push FLAGS
|
|
push_16(eflags); // ignores upper 16bits
|
|
|
|
// push return address onto new stack
|
|
push_16(old_CS);
|
|
push_16(old_EIP); // ignores upper 16bits
|
|
|
|
if ( is_error_code )
|
|
push_16(error_code);
|
|
}
|
|
|
|
return;
|
|
}
|
|
|
|
if (v8086_mode()) {
|
|
// if code segment DPL != 0 then #GP(new code segment selector)
|
|
exception(BX_GP_EXCEPTION, cs_selector.value & 0xfffc, 0);
|
|
}
|
|
|
|
// if code segment is conforming OR code segment DPL = CPL then
|
|
// INTERRUPT TO SAME PRIVILEGE LEVEL:
|
|
if ( cs_descriptor.u.segment.c_ed==1 || cs_descriptor.dpl==CPL )
|
|
{
|
|
int bytes;
|
|
Bit32u temp_ESP;
|
|
|
|
if (BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].cache.u.segment.d_b)
|
|
temp_ESP = ESP;
|
|
else
|
|
temp_ESP = SP;
|
|
|
|
BX_DEBUG(("int_trap_gate286(): INTERRUPT TO SAME PRIVILEGE"));
|
|
|
|
// Current stack limits must allow pushing 6|8 bytes, else #SS(0)
|
|
if (gate_descriptor.type >= 14) { // 386 gate
|
|
if ( is_error_code )
|
|
bytes = 16;
|
|
else
|
|
bytes = 12;
|
|
}
|
|
else { // 286 gate
|
|
if ( is_error_code )
|
|
bytes = 8;
|
|
else
|
|
bytes = 6;
|
|
}
|
|
|
|
if (! can_push(&BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].cache, temp_ESP, bytes))
|
|
{
|
|
BX_DEBUG(("interrupt(): stack doesn't have room"));
|
|
exception(BX_SS_EXCEPTION, 0, 0);
|
|
}
|
|
|
|
// EIP must be in CS limit else #GP(0)
|
|
if (gate_dest_offset > cs_descriptor.u.segment.limit_scaled) {
|
|
BX_ERROR(("interrupt(): IP > cs descriptor limit"));
|
|
exception(BX_GP_EXCEPTION, 0, 0);
|
|
}
|
|
|
|
// push flags onto stack
|
|
// push current CS selector onto stack
|
|
// push return offset onto stack
|
|
if (gate_descriptor.type >= 14) { // 386 gate
|
|
push_32(read_eflags());
|
|
push_32(BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].selector.value);
|
|
push_32(EIP);
|
|
if ( is_error_code )
|
|
push_32(error_code);
|
|
}
|
|
else { // 286 gate
|
|
push_16(read_flags());
|
|
push_16(BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].selector.value);
|
|
push_16(IP);
|
|
if ( is_error_code )
|
|
push_16(error_code);
|
|
}
|
|
|
|
// load CS:IP from gate
|
|
// load CS descriptor
|
|
// set the RPL field of CS to CPL
|
|
load_cs(&cs_selector, &cs_descriptor, CPL);
|
|
EIP = gate_dest_offset;
|
|
|
|
// if interrupt gate then set IF to 0
|
|
if ( !(gate_descriptor.type & 1) ) // even is int-gate
|
|
BX_CPU_THIS_PTR clear_IF ();
|
|
BX_CPU_THIS_PTR clear_TF ();
|
|
BX_CPU_THIS_PTR clear_NT ();
|
|
BX_CPU_THIS_PTR clear_VM ();
|
|
BX_CPU_THIS_PTR clear_RF ();
|
|
return;
|
|
}
|
|
|
|
// else #GP(CS selector + ext)
|
|
BX_DEBUG(("interrupt: bad descriptor"));
|
|
BX_DEBUG(("c_ed=%u, descriptor.dpl=%u, CPL=%u",
|
|
(unsigned) cs_descriptor.u.segment.c_ed,
|
|
(unsigned) cs_descriptor.dpl,
|
|
(unsigned) CPL));
|
|
BX_DEBUG(("cs.segment = %u", (unsigned) cs_descriptor.segment));
|
|
exception(BX_GP_EXCEPTION, cs_selector.value & 0xfffc, 0);
|
|
break;
|
|
|
|
default:
|
|
BX_PANIC(("bad descriptor type in interrupt()!"));
|
|
break;
|
|
}
|
|
}
|
|
else
|
|
#endif
|
|
{ /* real mode */
|
|
Bit16u cs_selector, ip;
|
|
|
|
if ( (vector*4+3) > BX_CPU_THIS_PTR idtr.limit )
|
|
{
|
|
BX_ERROR(("interrupt(real mode) vector > idtr.limit"));
|
|
exception(BX_GP_EXCEPTION, 0, 0);
|
|
}
|
|
|
|
push_16(read_flags());
|
|
|
|
cs_selector = BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].selector.value;
|
|
push_16(cs_selector);
|
|
ip = EIP;
|
|
push_16(ip);
|
|
|
|
access_linear(BX_CPU_THIS_PTR idtr.base + 4 * vector, 2, 0, BX_READ, &ip);
|
|
EIP = (Bit32u) ip;
|
|
access_linear(BX_CPU_THIS_PTR idtr.base + 4 * vector + 2, 2, 0, BX_READ, &cs_selector);
|
|
load_seg_reg(&BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS], cs_selector);
|
|
|
|
/* INT affects the following flags: I,T */
|
|
BX_CPU_THIS_PTR clear_IF ();
|
|
BX_CPU_THIS_PTR clear_TF ();
|
|
#if BX_CPU_LEVEL >= 4
|
|
BX_CPU_THIS_PTR clear_AC ();
|
|
#endif
|
|
BX_CPU_THIS_PTR clear_RF ();
|
|
}
|
|
}
|
|
|
|
// vector: 0..255: vector in IDT
|
|
// error_code: if exception generates and error, push this error code
|
|
void BX_CPU_C::exception(unsigned vector, Bit16u error_code, bx_bool is_INT)
|
|
{
|
|
bx_bool push_error;
|
|
Bit8u exception_type;
|
|
unsigned prev_errno;
|
|
|
|
invalidate_prefetch_q();
|
|
UNUSED(is_INT);
|
|
|
|
#if BX_DEBUGGER
|
|
if (bx_guard.special_unwind_stack) {
|
|
BX_INFO (("exception() returning early because special_unwind_stack is set"));
|
|
longjmp(BX_CPU_THIS_PTR jmp_buf_env, 1); // go back to main decode loop
|
|
}
|
|
#endif
|
|
|
|
#if BX_EXTERNAL_DEBUGGER
|
|
//trap_debugger(1);
|
|
#endif
|
|
|
|
BX_INSTR_EXCEPTION(BX_CPU_ID, vector);
|
|
|
|
BX_DEBUG(("exception(%02x h)", (unsigned) vector));
|
|
|
|
// if not initial error, restore previous register values from
|
|
// previous attempt to handle exception
|
|
if (BX_CPU_THIS_PTR errorno) {
|
|
BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS] = BX_CPU_THIS_PTR save_cs;
|
|
BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS] = BX_CPU_THIS_PTR save_ss;
|
|
EIP = BX_CPU_THIS_PTR save_eip;
|
|
ESP = BX_CPU_THIS_PTR save_esp;
|
|
}
|
|
|
|
BX_CPU_THIS_PTR errorno++;
|
|
if (BX_CPU_THIS_PTR errorno >= 3) {
|
|
#if BX_RESET_ON_TRIPLE_FAULT
|
|
BX_ERROR(("exception(): 3rd (%d) exception with no resolution, shutdown status is %02xh, resetting", vector, DEV_cmos_get_reg(0x0f)));
|
|
bx_pc_system.Reset( BX_RESET_SOFTWARE );
|
|
#else
|
|
BX_PANIC(("exception(): 3rd (%d) exception with no resolution", vector));
|
|
BX_ERROR(("WARNING: Any simulation after this point is completely bogus."));
|
|
#endif
|
|
#if BX_DEBUGGER
|
|
bx_guard.special_unwind_stack = true;
|
|
#endif
|
|
longjmp(BX_CPU_THIS_PTR jmp_buf_env, 1); // go back to main decode loop
|
|
}
|
|
|
|
/* careful not to get here with curr_exception[1]==DOUBLE_FAULT */
|
|
/* ...index on DOUBLE_FAULT below, will be out of bounds */
|
|
|
|
/* if 1st was a double fault (software INT?), then shutdown */
|
|
if ( (BX_CPU_THIS_PTR errorno==2) && (BX_CPU_THIS_PTR curr_exception[0]==BX_ET_DOUBLE_FAULT) ) {
|
|
#if BX_RESET_ON_TRIPLE_FAULT
|
|
BX_INFO(("exception(): triple fault encountered, shutdown status is %02xh, resetting", DEV_cmos_get_reg(0x0f)));
|
|
bx_pc_system.Reset( BX_RESET_SOFTWARE );
|
|
#else
|
|
BX_PANIC(("exception(): triple fault encountered"));
|
|
BX_ERROR(("WARNING: Any simulation after this point is completely bogus."));
|
|
#endif
|
|
#if BX_DEBUGGER
|
|
bx_guard.special_unwind_stack = true;
|
|
#endif
|
|
longjmp(BX_CPU_THIS_PTR jmp_buf_env, 1); // go back to main decode loop
|
|
}
|
|
|
|
/* ??? this is not totally correct, should be done depending on
|
|
* vector */
|
|
/* backup IP to value before error occurred */
|
|
EIP = BX_CPU_THIS_PTR prev_eip;
|
|
ESP = BX_CPU_THIS_PTR prev_esp;
|
|
|
|
// note: fault-class exceptions _except_ #DB set RF in
|
|
// eflags image.
|
|
|
|
switch (vector) {
|
|
case 0: // DIV by 0
|
|
push_error = 0;
|
|
exception_type = BX_ET_CONTRIBUTORY;
|
|
BX_CPU_THIS_PTR assert_RF ();
|
|
break;
|
|
case 1: // debug exceptions
|
|
push_error = 0;
|
|
exception_type = BX_ET_BENIGN;
|
|
break;
|
|
case 2: // NMI
|
|
push_error = 0;
|
|
exception_type = BX_ET_BENIGN;
|
|
break;
|
|
case 3: // breakpoint
|
|
push_error = 0;
|
|
exception_type = BX_ET_BENIGN;
|
|
break;
|
|
case 4: // overflow
|
|
push_error = 0;
|
|
exception_type = BX_ET_BENIGN;
|
|
break;
|
|
case 5: // bounds check
|
|
push_error = 0;
|
|
exception_type = BX_ET_BENIGN;
|
|
BX_CPU_THIS_PTR assert_RF ();
|
|
break;
|
|
case 6: // invalid opcode
|
|
push_error = 0;
|
|
exception_type = BX_ET_BENIGN;
|
|
BX_CPU_THIS_PTR assert_RF ();
|
|
break;
|
|
case 7: // device not available
|
|
push_error = 0;
|
|
exception_type = BX_ET_BENIGN;
|
|
BX_CPU_THIS_PTR assert_RF ();
|
|
break;
|
|
case 8: // double fault
|
|
push_error = 1;
|
|
exception_type = BX_ET_DOUBLE_FAULT;
|
|
break;
|
|
case 9: // coprocessor segment overrun (286,386 only)
|
|
push_error = 0;
|
|
exception_type = BX_ET_CONTRIBUTORY;
|
|
BX_CPU_THIS_PTR assert_RF ();
|
|
BX_PANIC(("exception(9): unfinished"));
|
|
break;
|
|
case 10: // invalid TSS
|
|
push_error = 1;
|
|
exception_type = BX_ET_CONTRIBUTORY;
|
|
error_code = (error_code & 0xfffe) | BX_CPU_THIS_PTR EXT;
|
|
BX_CPU_THIS_PTR assert_RF ();
|
|
break;
|
|
case 11: // segment not present
|
|
push_error = 1;
|
|
exception_type = BX_ET_CONTRIBUTORY;
|
|
error_code = (error_code & 0xfffe) | BX_CPU_THIS_PTR EXT;
|
|
BX_CPU_THIS_PTR assert_RF ();
|
|
break;
|
|
case 12: // stack fault
|
|
push_error = 1;
|
|
exception_type = BX_ET_CONTRIBUTORY;
|
|
error_code = (error_code & 0xfffe) | BX_CPU_THIS_PTR EXT;
|
|
BX_CPU_THIS_PTR assert_RF ();
|
|
break;
|
|
case 13: // general protection
|
|
push_error = 1;
|
|
exception_type = BX_ET_CONTRIBUTORY;
|
|
error_code = (error_code & 0xfffe) | BX_CPU_THIS_PTR EXT;
|
|
BX_CPU_THIS_PTR assert_RF ();
|
|
break;
|
|
case 14: // page fault
|
|
if (BX_CPU_THIS_PTR except_chk) // Help with OS/2
|
|
{
|
|
BX_CPU_THIS_PTR except_chk = 0;
|
|
BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].selector.value = BX_CPU_THIS_PTR except_cs;
|
|
BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].selector.value = BX_CPU_THIS_PTR except_ss;
|
|
}
|
|
push_error = 1;
|
|
exception_type = BX_ET_PAGE_FAULT;
|
|
// ??? special format error returned
|
|
BX_CPU_THIS_PTR assert_RF ();
|
|
break;
|
|
case 15: // reserved
|
|
BX_PANIC(("exception(15): reserved"));
|
|
push_error = 0; // keep compiler happy for now
|
|
exception_type = 0; // keep compiler happy for now
|
|
break;
|
|
case 16: // floating-point error
|
|
push_error = 0;
|
|
exception_type = BX_ET_BENIGN;
|
|
BX_CPU_THIS_PTR assert_RF ();
|
|
break;
|
|
#if BX_CPU_LEVEL >= 4
|
|
case 17: // alignment check
|
|
BX_PANIC(("exception(): alignment-check, vector 17 unimplemented"));
|
|
push_error = 0; // keep compiler happy for now
|
|
exception_type = 0; // keep compiler happy for now
|
|
BX_CPU_THIS_PTR assert_RF ();
|
|
break;
|
|
#endif
|
|
#if BX_CPU_LEVEL >= 5
|
|
case 18: // machine check
|
|
BX_PANIC(("exception(): machine-check, vector 18 unimplemented"));
|
|
push_error = 0; // keep compiler happy for now
|
|
exception_type = 0; // keep compiler happy for now
|
|
break;
|
|
#endif
|
|
default:
|
|
BX_PANIC(("exception(%u): bad vector", (unsigned) vector));
|
|
push_error = 0; // keep compiler happy for now
|
|
exception_type = 0; // keep compiler happy for now
|
|
break;
|
|
}
|
|
|
|
if (exception_type != BX_ET_PAGE_FAULT) {
|
|
// Page faults have different format
|
|
error_code = (error_code & 0xfffe) | BX_CPU_THIS_PTR EXT;
|
|
}
|
|
BX_CPU_THIS_PTR EXT = 1;
|
|
|
|
/* if we've already had 1st exception, see if 2nd causes a
|
|
* Double Fault instead. Otherwise, just record 1st exception
|
|
*/
|
|
if (BX_CPU_THIS_PTR errorno >= 2) {
|
|
if (is_exception_OK[BX_CPU_THIS_PTR curr_exception[0]][exception_type])
|
|
BX_CPU_THIS_PTR curr_exception[1] = exception_type;
|
|
else {
|
|
BX_CPU_THIS_PTR curr_exception[1] = BX_ET_DOUBLE_FAULT;
|
|
vector = 8;
|
|
}
|
|
}
|
|
else {
|
|
BX_CPU_THIS_PTR curr_exception[0] = exception_type;
|
|
}
|
|
|
|
|
|
#if BX_CPU_LEVEL >= 2
|
|
if (!real_mode()) {
|
|
prev_errno = BX_CPU_THIS_PTR errorno;
|
|
BX_CPU_THIS_PTR interrupt(vector, 0, push_error, error_code);
|
|
// if (BX_CPU_THIS_PTR errorno > prev_errno) {
|
|
// BX_INFO(("segment_exception(): errorno changed"));
|
|
// longjmp(jmp_buf_env, 1); // go back to main decode loop
|
|
// return;
|
|
// }
|
|
|
|
// if (push_error) {
|
|
// /* push error code on stack, after handling interrupt */
|
|
// /* pushed as a word or dword depending upon default size ??? */
|
|
// if (ss.cache.u.segment.d_b)
|
|
// push_32((Bit32u) error_code); /* upper bits reserved */
|
|
// else
|
|
// push_16(error_code);
|
|
// if (BX_CPU_THIS_PTR errorno > prev_errno) {
|
|
// BX_PANIC(("segment_exception(): errorno changed"));
|
|
// return;
|
|
// }
|
|
// }
|
|
BX_CPU_THIS_PTR errorno = 0; // error resolved
|
|
longjmp(BX_CPU_THIS_PTR jmp_buf_env, 1); // go back to main decode loop
|
|
}
|
|
else // real mode
|
|
#endif
|
|
{
|
|
// not INT, no error code pushed
|
|
BX_CPU_THIS_PTR interrupt(vector, 0, 0, 0);
|
|
BX_CPU_THIS_PTR errorno = 0; // error resolved
|
|
longjmp(BX_CPU_THIS_PTR jmp_buf_env, 1); // go back to main decode loop
|
|
}
|
|
}
|