e2e219eda0
also extended by the REX.B field on Hammer) is passed to instructions. I rearranged the bxInstruction_c to free up a field to be used to pass this info when mod-rm bytes are not used. This got rid of the ugly ((i->b1 & 7) + i->rex_b) code. Probably shaved just a very little run time off Hammer emulation, and even less on x86-32. The resultant is a little cleaner anyways.
339 lines
7.4 KiB
C++
339 lines
7.4 KiB
C++
/////////////////////////////////////////////////////////////////////////
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// $Id: stack64.cc,v 1.6 2002-09-20 23:17:51 kevinlawton Exp $
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/////////////////////////////////////////////////////////////////////////
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//
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// Copyright (C) 2001 MandrakeSoft S.A.
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//
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// MandrakeSoft S.A.
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// 43, rue d'Aboukir
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// 75002 Paris - France
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// http://www.linux-mandrake.com/
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// http://www.mandrakesoft.com/
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//
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// This library is free software; you can redistribute it and/or
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// modify it under the terms of the GNU Lesser General Public
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// License as published by the Free Software Foundation; either
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// version 2 of the License, or (at your option) any later version.
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//
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// This library is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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// Lesser General Public License for more details.
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//
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// You should have received a copy of the GNU Lesser General Public
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// License along with this library; if not, write to the Free Software
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// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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#define NEED_CPU_REG_SHORTCUTS 1
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#include "bochs.h"
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#define LOG_THIS BX_CPU_THIS_PTR
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#if BX_USE_CPU_SMF
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#define this (BX_CPU(0))
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#endif
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void
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BX_CPU_C::POP_Eq(bxInstruction_c *i)
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{
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Bit64u val64;
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pop_64(&val64);
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if (i->modC0()) {
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BX_WRITE_64BIT_REG(i->rm(), val64);
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}
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else {
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// Note: there is one little weirdism here. When 64bit addressing
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// is used, it is possible to use RSP in the modrm addressing.
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// If used, the value of RSP after the pop is used to calculate
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// the address.
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if (i->as64L() && (!i->modC0()) && (i->rm()==4) && (i->sibBase()==4)) {
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// call method on BX_CPU_C object
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BX_CPU_CALL_METHOD (i->ResolveModrm, (i));
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}
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write_virtual_qword(i->seg(), RMAddr(i), &val64);
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}
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}
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void
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BX_CPU_C::PUSH_RRX(bxInstruction_c *i)
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{
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push_64(BX_CPU_THIS_PTR gen_reg[i->opcodeReg()].rrx);
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}
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void
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BX_CPU_C::POP_RRX(bxInstruction_c *i)
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{
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Bit64u rrx;
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pop_64(&rrx);
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BX_CPU_THIS_PTR gen_reg[i->opcodeReg()].rrx = rrx;
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}
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void
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BX_CPU_C::PUSH64_CS(bxInstruction_c *i)
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{
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push_64(BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].selector.value);
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}
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void
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BX_CPU_C::PUSH64_DS(bxInstruction_c *i)
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{
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push_64(BX_CPU_THIS_PTR sregs[BX_SEG_REG_DS].selector.value);
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}
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void
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BX_CPU_C::PUSH64_ES(bxInstruction_c *i)
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{
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push_64(BX_CPU_THIS_PTR sregs[BX_SEG_REG_ES].selector.value);
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}
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void
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BX_CPU_C::PUSH64_FS(bxInstruction_c *i)
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{
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push_64(BX_CPU_THIS_PTR sregs[BX_SEG_REG_FS].selector.value);
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}
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void
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BX_CPU_C::PUSH64_GS(bxInstruction_c *i)
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{
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push_64(BX_CPU_THIS_PTR sregs[BX_SEG_REG_GS].selector.value);
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}
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void
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BX_CPU_C::PUSH64_SS(bxInstruction_c *i)
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{
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push_64(BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].selector.value);
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}
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void
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BX_CPU_C::POP64_DS(bxInstruction_c *i)
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{
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Bit64u ds;
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pop_64(&ds);
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load_seg_reg(&BX_CPU_THIS_PTR sregs[BX_SEG_REG_DS], (Bit16u) ds);
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}
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void
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BX_CPU_C::POP64_ES(bxInstruction_c *i)
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{
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Bit64u es;
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pop_64(&es);
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load_seg_reg(&BX_CPU_THIS_PTR sregs[BX_SEG_REG_ES], (Bit16u) es);
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}
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void
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BX_CPU_C::POP64_FS(bxInstruction_c *i)
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{
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Bit64u fs;
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pop_64(&fs);
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load_seg_reg(&BX_CPU_THIS_PTR sregs[BX_SEG_REG_FS], (Bit16u) fs);
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}
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void
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BX_CPU_C::POP64_GS(bxInstruction_c *i)
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{
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Bit64u gs;
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pop_64(&gs);
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load_seg_reg(&BX_CPU_THIS_PTR sregs[BX_SEG_REG_GS], (Bit16u) gs);
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}
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void
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BX_CPU_C::POP64_SS(bxInstruction_c *i)
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{
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Bit64u ss;
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pop_64(&ss);
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load_seg_reg(&BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS], (Bit16u) ss);
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// POP SS inhibits interrupts, debug exceptions and single-step
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// trap exceptions until the execution boundary following the
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// next instruction is reached.
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// Same code as MOV_SwEw()
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BX_CPU_THIS_PTR inhibit_mask |=
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BX_INHIBIT_INTERRUPTS | BX_INHIBIT_DEBUG;
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BX_CPU_THIS_PTR async_event = 1;
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}
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void
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BX_CPU_C::PUSHAD64(bxInstruction_c *i)
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{
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#if BX_CPU_LEVEL < 2
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BX_PANIC(("PUSHAD: not supported on an 8086"));
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#else
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Bit64u temp_RSP;
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Bit64u rsp;
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temp_RSP = RSP;
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if ( !can_push(&BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].cache, temp_RSP, 64) ) {
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BX_PANIC(("PUSHAD(): stack doesn't have enough room!"));
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exception(BX_SS_EXCEPTION, 0, 0);
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return;
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}
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rsp = RSP;
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/* ??? optimize this by using virtual write, all checks passed */
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push_64(RAX);
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push_64(RCX);
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push_64(RDX);
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push_64(RBX);
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push_64(rsp);
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push_64(RBP);
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push_64(RSI);
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push_64(RDI);
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#endif
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}
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void
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BX_CPU_C::POPAD64(bxInstruction_c *i)
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{
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#if BX_CPU_LEVEL < 2
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BX_PANIC(("POPAD not supported on an 8086"));
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#else /* 286+ */
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Bit64u rdi, rsi, rbp, rtmp, rbx, rdx, rcx, rax;
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if ( !can_pop(64) ) {
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BX_PANIC(("pop_ad: not enough bytes on stack"));
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exception(BX_SS_EXCEPTION, 0, 0);
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return;
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}
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/* ??? optimize this */
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pop_64(&rdi);
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pop_64(&rsi);
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pop_64(&rbp);
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pop_64(&rtmp); /* value for ESP discarded */
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pop_64(&rbx);
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pop_64(&rdx);
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pop_64(&rcx);
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pop_64(&rax);
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RDI = rdi;
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RSI = rsi;
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RBP = rbp;
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RBX = rbx;
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RDX = rdx;
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RCX = rcx;
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RAX = rax;
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#endif
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}
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void
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BX_CPU_C::PUSH64_Id(bxInstruction_c *i)
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{
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#if BX_CPU_LEVEL < 2
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BX_PANIC(("PUSH_Id: not supported on 8086!"));
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#else
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Bit64u imm64;
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imm64 = (Bit32s) i->Id();
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push_64(imm64);
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#endif
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}
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void
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BX_CPU_C::PUSH_Eq(bxInstruction_c *i)
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{
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Bit64u op1_64;
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/* op1_64 is a register or memory reference */
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if (i->modC0()) {
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op1_64 = BX_READ_64BIT_REG(i->rm());
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}
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else {
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/* pointer, segment address pair */
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read_virtual_qword(i->seg(), RMAddr(i), &op1_64);
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}
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push_64(op1_64);
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}
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void
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BX_CPU_C::ENTER64_IwIb(bxInstruction_c *i)
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{
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#if BX_CPU_LEVEL < 2
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BX_PANIC(("ENTER_IwIb: not supported by 8086!"));
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#else
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Bit64u frame_ptr64;
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Bit16u frame_ptr16;
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Bit8u level;
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static Bit8u first_time = 1;
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level = i->Ib2();
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invalidate_prefetch_q();
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level %= 32;
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/* ??? */
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if (first_time && level>0) {
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BX_ERROR(("enter() with level > 0. The emulation of this instruction may not be complete. This warning will be printed only once per bochs run."));
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first_time = 0;
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}
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//if (BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].cache.u.segment.d_b && i->os64L()==0) {
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// BX_INFO(("enter(): stacksize!=opsize: I'm unsure of the code for this"));
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// BX_PANIC((" The Intel manuals are a mess on this one!"));
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// }
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{
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Bit64u bytes_to_push, temp_RSP;
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if (level == 0) {
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bytes_to_push = 8 + i->Iw();
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}
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else { /* level > 0 */
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bytes_to_push = 8 + (level-1)*8 + 8 + i->Iw();
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}
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temp_RSP = RSP;
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if ( !can_push(&BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].cache, temp_RSP, bytes_to_push) ) {
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BX_PANIC(("ENTER: not enough room on stack!"));
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exception(BX_SS_EXCEPTION, 0, 0);
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}
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}
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push_64(RBP);
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frame_ptr64 = RSP;
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if (level > 0) {
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/* do level-1 times */
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while (--level) {
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Bit64u temp64;
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RBP -= 4;
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read_virtual_qword(BX_SEG_REG_SS, RBP, &temp64);
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ESP -= 4;
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write_virtual_qword(BX_SEG_REG_SS, RSP, &temp64);
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} /* while (--level) */
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/* push(frame pointer) */
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RSP -= 4;
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write_virtual_qword(BX_SEG_REG_SS, RSP, &frame_ptr64);
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} /* if (level > 0) ... */
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RBP = frame_ptr64;
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RSP = RSP - i->Iw();
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#endif
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}
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void
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BX_CPU_C::LEAVE64(bxInstruction_c *i)
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{
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#if BX_CPU_LEVEL < 2
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BX_PANIC(("LEAVE: not supported by 8086!"));
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#else
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// delete frame
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RSP = RBP;
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// restore frame pointer
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{
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Bit64u temp64;
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pop_64(&temp64);
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RBP = temp64;
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}
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#endif
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}
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