177 lines
11 KiB
C++
177 lines
11 KiB
C++
/////////////////////////////////////////////////////////////////////////
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// $Id$
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/////////////////////////////////////////////////////////////////////////
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//
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// Copyright (c) 2013 Stanislav Shwartsman
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// Written by Stanislav Shwartsman [sshwarts at sourceforge net]
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//
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// This library is free software; you can redistribute it and/or
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// modify it under the terms of the GNU Lesser General Public
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// License as published by the Free Software Foundation; either
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// version 2 of the License, or (at your option) any later version.
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//
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// This library is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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// Lesser General Public License for more details.
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//
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// You should have received a copy of the GNU Lesser General Public
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// License along with this library; if not, write to the Free Software
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// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA B 02110-1301 USA
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//
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/////////////////////////////////////////////////////////////////////////
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#define NEED_CPU_REG_SHORTCUTS 1
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#include "bochs.h"
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#include "cpu.h"
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#define LOG_THIS BX_CPU_THIS_PTR
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#if BX_SUPPORT_EVEX
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extern void mxcsr_to_softfloat_status_word(float_status_t &status, bx_mxcsr_t mxcsr);
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#include "simd_int.h"
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#include "simd_pfp.h"
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//////////////////////////////
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// AVX-512 FMA Instructions //
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//////////////////////////////
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#define EVEX_FMA_PACKED_SINGLE(HANDLER, func) \
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BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C:: HANDLER (bxInstruction_c *i) \
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{ \
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BxPackedAvxRegister op1 = BX_READ_AVX_REG(i->src1()); \
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BxPackedAvxRegister op2 = BX_READ_AVX_REG(i->src2()); \
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BxPackedAvxRegister op3 = BX_READ_AVX_REG(i->src3()); \
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unsigned mask = BX_READ_16BIT_OPMASK(i->opmask()); \
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unsigned len = i->getVL(); \
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\
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float_status_t status; \
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mxcsr_to_softfloat_status_word(status, MXCSR); \
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softfloat_status_word_rc_override(status, i); \
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\
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for (unsigned n=0, tmp_mask = mask; n < len; n++, tmp_mask >>= 4) \
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(func)(&op1.vmm128(n), &op2.vmm128(n), &op3.vmm128(n), status, tmp_mask); \
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\
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check_exceptionsSSE(get_exception_flags(status)); \
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\
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if (! i->isZeroMasking()) { \
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for (unsigned n=0; n < len; n++, mask >>= 4) \
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xmm_blendps(&BX_READ_AVX_REG_LANE(i->dst(), n), &op1.vmm128(n), mask); \
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\
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BX_CLEAR_AVX_REGZ(i->dst(), len); \
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} \
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else { \
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BX_WRITE_AVX_REGZ(i->dst(), op1, len); \
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} \
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\
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BX_NEXT_INSTR(i); \
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}
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EVEX_FMA_PACKED_SINGLE(VFMADDPS_MASK_VpsHpsWpsR, xmm_fmaddps_mask)
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EVEX_FMA_PACKED_SINGLE(VFMADDSUBPS_MASK_VpsHpsWpsR, xmm_fmaddsubps_mask)
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EVEX_FMA_PACKED_SINGLE(VFMSUBADDPS_MASK_VpsHpsWpsR, xmm_fmsubaddps_mask)
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EVEX_FMA_PACKED_SINGLE(VFMSUBPS_MASK_VpsHpsWpsR, xmm_fmsubps_mask)
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EVEX_FMA_PACKED_SINGLE(VFNMADDPS_MASK_VpsHpsWpsR, xmm_fnmaddps_mask)
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EVEX_FMA_PACKED_SINGLE(VFNMSUBPS_MASK_VpsHpsWpsR, xmm_fnmsubps_mask)
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#define EVEX_FMA_PACKED_DOUBLE(HANDLER, func) \
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BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C:: HANDLER (bxInstruction_c *i) \
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{ \
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BxPackedAvxRegister op1 = BX_READ_AVX_REG(i->src1()); \
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BxPackedAvxRegister op2 = BX_READ_AVX_REG(i->src2()); \
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BxPackedAvxRegister op3 = BX_READ_AVX_REG(i->src3()); \
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unsigned mask = BX_READ_8BIT_OPMASK(i->opmask()); \
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unsigned len = i->getVL(); \
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\
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float_status_t status; \
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mxcsr_to_softfloat_status_word(status, MXCSR); \
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softfloat_status_word_rc_override(status, i); \
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\
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for (unsigned n=0, tmp_mask = mask; n < len; n++, tmp_mask >>= 2) \
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(func)(&op1.vmm128(n), &op2.vmm128(n), &op3.vmm128(n), status, tmp_mask); \
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\
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check_exceptionsSSE(get_exception_flags(status)); \
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\
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if (! i->isZeroMasking()) { \
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for (unsigned n=0; n < len; n++, mask >>= 2) \
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xmm_blendpd(&BX_READ_AVX_REG_LANE(i->dst(), n), &op1.vmm128(n), mask); \
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\
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BX_CLEAR_AVX_REGZ(i->dst(), len); \
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} \
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else { \
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BX_WRITE_AVX_REGZ(i->dst(), op1, len); \
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} \
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\
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BX_NEXT_INSTR(i); \
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}
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EVEX_FMA_PACKED_DOUBLE(VFMADDPD_MASK_VpdHpdWpdR, xmm_fmaddpd_mask)
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EVEX_FMA_PACKED_DOUBLE(VFMADDSUBPD_MASK_VpdHpdWpdR, xmm_fmaddsubpd_mask)
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EVEX_FMA_PACKED_DOUBLE(VFMSUBADDPD_MASK_VpdHpdWpdR, xmm_fmsubaddpd_mask)
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EVEX_FMA_PACKED_DOUBLE(VFMSUBPD_MASK_VpdHpdWpdR, xmm_fmsubpd_mask)
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EVEX_FMA_PACKED_DOUBLE(VFNMADDPD_MASK_VpdHpdWpdR, xmm_fnmaddpd_mask)
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EVEX_FMA_PACKED_DOUBLE(VFNMSUBPD_MASK_VpdHpdWpdR, xmm_fnmsubpd_mask)
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#define EVEX_FMA_SCALAR_SINGLE(HANDLER, func) \
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BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C:: HANDLER (bxInstruction_c *i) \
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{ \
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if (BX_SCALAR_ELEMENT_MASK(i->opmask())) { \
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float32 op1 = BX_READ_XMM_REG_LO_DWORD(i->src1()); \
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float32 op2 = BX_READ_XMM_REG_LO_DWORD(i->src2()); \
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float32 op3 = BX_READ_XMM_REG_LO_DWORD(i->src3()); \
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\
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float_status_t status; \
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mxcsr_to_softfloat_status_word(status, MXCSR); \
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softfloat_status_word_rc_override(status, i); \
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op1 = (func)(op1, op2, op3, status); \
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check_exceptionsSSE(get_exception_flags(status)); \
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\
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BX_WRITE_XMM_REG_LO_DWORD(i->dst(), op1); \
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} \
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else { \
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if (i->isZeroMasking()) \
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BX_WRITE_XMM_REG_LO_DWORD(i->dst(), 0); \
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} \
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\
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BX_CLEAR_AVX_HIGH128(i->dst()); \
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BX_NEXT_INSTR(i); \
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}
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EVEX_FMA_SCALAR_SINGLE(VFMADDSS_MASK_VpsHssWssR, float32_fmadd)
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EVEX_FMA_SCALAR_SINGLE(VFMSUBSS_MASK_VpsHssWssR, float32_fmsub)
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EVEX_FMA_SCALAR_SINGLE(VFNMADDSS_MASK_VpsHssWssR, float32_fnmadd)
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EVEX_FMA_SCALAR_SINGLE(VFNMSUBSS_MASK_VpsHssWssR, float32_fnmsub)
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#define EVEX_FMA_SCALAR_DOUBLE(HANDLER, func) \
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BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C:: HANDLER (bxInstruction_c *i) \
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{ \
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if (BX_SCALAR_ELEMENT_MASK(i->opmask())) { \
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float64 op1 = BX_READ_XMM_REG_LO_QWORD(i->src1()); \
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float64 op2 = BX_READ_XMM_REG_LO_QWORD(i->src2()); \
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float64 op3 = BX_READ_XMM_REG_LO_QWORD(i->src3()); \
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\
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float_status_t status; \
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mxcsr_to_softfloat_status_word(status, MXCSR); \
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softfloat_status_word_rc_override(status, i); \
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op1 = (func)(op1, op2, op3, status); \
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check_exceptionsSSE(get_exception_flags(status)); \
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\
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BX_WRITE_XMM_REG_LO_QWORD(i->dst(), op1); \
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} \
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else { \
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if (i->isZeroMasking()) \
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BX_WRITE_XMM_REG_LO_QWORD(i->dst(), 0); \
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} \
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\
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BX_CLEAR_AVX_HIGH128(i->dst()); \
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BX_NEXT_INSTR(i); \
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}
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EVEX_FMA_SCALAR_DOUBLE(VFMADDSD_MASK_VpdHsdWsdR, float64_fmadd)
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EVEX_FMA_SCALAR_DOUBLE(VFMSUBSD_MASK_VpdHsdWsdR, float64_fmsub)
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EVEX_FMA_SCALAR_DOUBLE(VFNMADDSD_MASK_VpdHsdWsdR, float64_fnmadd)
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EVEX_FMA_SCALAR_DOUBLE(VFNMSUBSD_MASK_VpdHsdWsdR, float64_fnmsub)
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#endif
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