13feb0772a
feature is enabled by default when configure with --enable-all-optimizations
option, to disable handlers chaining speedups configure with
--disable-handlers-chaining
341 lines
10 KiB
C++
341 lines
10 KiB
C++
/////////////////////////////////////////////////////////////////////////
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// $Id$
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/////////////////////////////////////////////////////////////////////////
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//
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// Copyright (c) 2008-2011 Stanislav Shwartsman
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// Written by Stanislav Shwartsman [sshwarts at sourceforge net]
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//
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// This library is free software; you can redistribute it and/or
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// modify it under the terms of the GNU Lesser General Public
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// License as published by the Free Software Foundation; either
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// version 2 of the License, or (at your option) any later version.
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//
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// This library is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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// Lesser General Public License for more details.
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//
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// You should have received a copy of the GNU Lesser General Public
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// License along with this library; if not, write to the Free Software
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// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA B 02110-1301 USA
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//
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/////////////////////////////////////////////////////////////////////////
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#ifndef BX_INSTR_H
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#define BX_INSTR_H
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class bxInstruction_c;
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typedef void BX_INSF_TYPE;
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#if BX_DISASM
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// print the instruction that is about to be executed
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#define BX_DEBUG_DISASM_INSTRUCTION() \
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if (BX_CPU_THIS_PTR trace) { debug_disasm_instruction(BX_CPU_THIS_PTR prev_rip); }
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#else
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#define BX_DEBUG_DISASM_INSTRUCTION() /* do nothing */
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#endif
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#define BX_NEXT_INSTR(i) { \
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BX_CPU_THIS_PTR prev_rip = RIP; /* commit new RIP */ \
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BX_INSTR_AFTER_EXECUTION(BX_CPU_ID, i); \
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BX_TICK1_IF_SINGLE_PROCESSOR(); \
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if (BX_CPU_THIS_PTR async_event) return; \
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++i; \
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BX_DEBUG_DISASM_INSTRUCTION(); \
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BX_INSTR_BEFORE_EXECUTION(BX_CPU_ID, i); \
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RIP += i->ilen(); \
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return BX_CPU_CALL_METHOD(i->execute, (i)); \
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}
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#define BX_NEXT_TRACE(i) { return; }
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// <TAG-TYPE-EXECUTEPTR-START>
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#if BX_USE_CPU_SMF
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typedef BX_INSF_TYPE (BX_CPP_AttrRegparmN(1) *BxExecutePtr_tR)(bxInstruction_c *);
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typedef bx_address (BX_CPP_AttrRegparmN(1) *BxResolvePtr_tR)(bxInstruction_c *);
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typedef void (BX_CPP_AttrRegparmN(1) *BxRepIterationPtr_tR)(bxInstruction_c *);
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#else
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typedef BX_INSF_TYPE (BX_CPU_C::*BxExecutePtr_tR)(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
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typedef bx_address (BX_CPU_C::*BxResolvePtr_tR)(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
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typedef void (BX_CPU_C::*BxRepIterationPtr_tR)(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
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#endif
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// <TAG-TYPE-EXECUTEPTR-END>
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extern bx_address bx_asize_mask[];
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const char *get_bx_opcode_name(Bit16u ia_opcode);
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// <TAG-CLASS-INSTRUCTION-START>
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class bxInstruction_c {
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public:
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// Function pointers; a function to resolve the modRM address
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// given the current state of the CPU and the instruction data,
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// and a function to execute the instruction after resolving
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// the memory address (if any).
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BxExecutePtr_tR execute;
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BxExecutePtr_tR execute2;
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BxResolvePtr_tR ResolveModrm;
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struct {
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// 15.12 AVX vl (0=no VL, 1=128 bit, 2=256 bit)
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// 11..0 opcode
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Bit16u ia_opcode;
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// 7...4 (unused)
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// 3...0 ilen (0..15)
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Bit8u ilen;
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// 7...6 repUsed (0=none, 2=0xF2, 3=0xF3)
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// 5...5 extend8bit
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// 4...4 mod==c0 (modrm)
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// 3...3 os64
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// 2...2 os32
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// 1...1 as64
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// 0...0 as32
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Bit8u metaInfo1;
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} metaInfo;
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#define BX_INSTR_METADATA_SEG 0
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#define BX_INSTR_METADATA_B1 1
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#define BX_INSTR_METADATA_NNN 2
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#define BX_INSTR_METADATA_RM 3
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#define BX_INSTR_METADATA_BASE 4
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#define BX_INSTR_METADATA_INDEX 5
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#define BX_INSTR_METADATA_SCALE 6
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#define BX_INSTR_METADATA_MODRM 7 /* modrm for FPU only */
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#define BX_INSTR_METADATA_VVV 7
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// using 5-bit field for registers (16 regs in 64-bit, RIP, NIL)
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Bit8u metaData[8];
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union {
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// Form (longest case): [opcode+modrm+sib/displacement32/immediate32]
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struct {
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union {
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Bit32u Id;
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Bit16u Iw;
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Bit8u Ib;
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};
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union {
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Bit16u displ16u; // for 16-bit modrm forms
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Bit32u displ32u; // for 32-bit modrm forms
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Bit16u Iw2;
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Bit8u Ib2;
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};
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} modRMForm;
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#if BX_SUPPORT_X86_64
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struct {
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Bit64u Iq; // for MOV Rx,imm64
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} IqForm;
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#endif
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};
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#ifdef BX_INSTR_STORE_OPCODE_BYTES
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Bit8u opcode_bytes[16];
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BX_CPP_INLINE const Bit8u* get_opcode_bytes(void) const {
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return opcode_bytes;
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}
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BX_CPP_INLINE void set_opcode_bytes(const Bit8u *opcode) {
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memcpy(opcode_bytes, opcode, ilen());
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}
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#endif
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BX_CPP_INLINE unsigned seg(void) const {
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return metaData[BX_INSTR_METADATA_SEG];
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}
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BX_CPP_INLINE void setSeg(unsigned val) {
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metaData[BX_INSTR_METADATA_SEG] = val;
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}
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BX_CPP_INLINE unsigned b1(void) const {
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return metaData[BX_INSTR_METADATA_B1];
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}
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BX_CPP_INLINE void setB1(unsigned b1) {
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metaData[BX_INSTR_METADATA_B1] = b1 & 0xff;
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}
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BX_CPP_INLINE void setModRM(unsigned modrm) {
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metaData[BX_INSTR_METADATA_MODRM] = modrm;
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}
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BX_CPP_INLINE unsigned modrm() const {
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return metaData[BX_INSTR_METADATA_MODRM];
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}
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BX_CPP_INLINE void setNnn(unsigned nnn) {
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metaData[BX_INSTR_METADATA_NNN] = nnn;
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}
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BX_CPP_INLINE unsigned nnn() const {
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return metaData[BX_INSTR_METADATA_NNN];
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}
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BX_CPP_INLINE void setRm(unsigned rm) {
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metaData[BX_INSTR_METADATA_RM] = rm;
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}
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BX_CPP_INLINE unsigned rm() const {
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return metaData[BX_INSTR_METADATA_RM];
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}
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BX_CPP_INLINE void setSibScale(unsigned scale) {
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metaData[BX_INSTR_METADATA_SCALE] = scale;
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}
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BX_CPP_INLINE unsigned sibScale() const {
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return metaData[BX_INSTR_METADATA_SCALE];
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}
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BX_CPP_INLINE void setSibIndex(unsigned index) {
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metaData[BX_INSTR_METADATA_INDEX] = index;
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}
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BX_CPP_INLINE unsigned sibIndex() const {
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return metaData[BX_INSTR_METADATA_INDEX];
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}
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BX_CPP_INLINE void setSibBase(unsigned base) {
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metaData[BX_INSTR_METADATA_BASE] = base;
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}
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BX_CPP_INLINE unsigned sibBase() const {
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return metaData[BX_INSTR_METADATA_BASE];
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}
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BX_CPP_INLINE Bit32s displ32s() const { return (Bit32s) modRMForm.displ32u; }
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BX_CPP_INLINE Bit16s displ16s() const { return (Bit16s) modRMForm.displ16u; }
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BX_CPP_INLINE Bit32u Id() const { return modRMForm.Id; }
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BX_CPP_INLINE Bit16u Iw() const { return modRMForm.Iw; }
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BX_CPP_INLINE Bit8u Ib() const { return modRMForm.Ib; }
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BX_CPP_INLINE Bit16u Iw2() const { return modRMForm.Iw2; }
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BX_CPP_INLINE Bit8u Ib2() const { return modRMForm.Ib2; }
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#if BX_SUPPORT_X86_64
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BX_CPP_INLINE Bit64u Iq() const { return IqForm.Iq; }
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#endif
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// Info in the metaInfo field.
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// Note: the 'L' at the end of certain flags, means the value returned
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// is for Logical comparisons, eg if (i->os32L() && i->as32L()). If you
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// want a bx_bool value, use os32B() etc. This makes for smaller
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// code, when a strict 0 or 1 is not necessary.
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BX_CPP_INLINE void init(unsigned os32, unsigned as32, unsigned os64, unsigned as64)
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{
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metaInfo.metaInfo1 = (os32<<2) | (os64<<3) | (as32<<0) | (as64<<1);
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}
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BX_CPP_INLINE unsigned os32L(void) const {
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return metaInfo.metaInfo1 & (1<<2);
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}
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BX_CPP_INLINE void setOs32B(unsigned bit) {
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metaInfo.metaInfo1 = (metaInfo.metaInfo1 & ~(1<<2)) | (bit<<2);
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}
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BX_CPP_INLINE void assertOs32(void) {
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metaInfo.metaInfo1 |= (1<<2);
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}
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#if BX_SUPPORT_X86_64
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BX_CPP_INLINE unsigned os64L(void) const {
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return metaInfo.metaInfo1 & (1<<3);
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}
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BX_CPP_INLINE void assertOs64(void) {
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metaInfo.metaInfo1 |= (1<<3);
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}
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#else
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BX_CPP_INLINE unsigned os64L(void) const { return 0; }
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#endif
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BX_CPP_INLINE unsigned as32L(void) const {
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return metaInfo.metaInfo1 & 0x1;
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}
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BX_CPP_INLINE void setAs32B(unsigned bit) {
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metaInfo.metaInfo1 = (metaInfo.metaInfo1 & ~0x1) | (bit);
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}
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#if BX_SUPPORT_X86_64
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BX_CPP_INLINE unsigned as64L(void) const {
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return metaInfo.metaInfo1 & (1<<1);
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}
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BX_CPP_INLINE void clearAs64(void) {
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metaInfo.metaInfo1 &= ~(1<<1);
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}
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#else
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BX_CPP_INLINE unsigned as64L(void) const { return 0; }
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#endif
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BX_CPP_INLINE unsigned asize(void) const {
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return metaInfo.metaInfo1 & 0x3;
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}
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BX_CPP_INLINE bx_address asize_mask(void) const {
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return bx_asize_mask[asize()];
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}
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#if BX_SUPPORT_X86_64
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BX_CPP_INLINE unsigned extend8bitL(void) const {
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return metaInfo.metaInfo1 & (1<<5);
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}
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BX_CPP_INLINE void assertExtend8bit(void) {
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metaInfo.metaInfo1 |= (1<<5);
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}
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#endif
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BX_CPP_INLINE unsigned ilen(void) const {
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return metaInfo.ilen;
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}
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BX_CPP_INLINE void setILen(unsigned ilen) {
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metaInfo.ilen = ilen;
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}
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BX_CPP_INLINE unsigned getIaOpcode(void) const {
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return metaInfo.ia_opcode & 0xfff;
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}
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BX_CPP_INLINE void setIaOpcode(Bit16u op) {
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metaInfo.ia_opcode = (metaInfo.ia_opcode & 0xf000) | op;
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}
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BX_CPP_INLINE const char* getIaOpcodeName(void) const {
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return get_bx_opcode_name(getIaOpcode());
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}
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BX_CPP_INLINE unsigned repUsedL(void) const {
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return metaInfo.metaInfo1 >> 6;
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}
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BX_CPP_INLINE unsigned repUsedValue(void) const {
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return metaInfo.metaInfo1 >> 6;
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}
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BX_CPP_INLINE void setRepUsed(unsigned value) {
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metaInfo.metaInfo1 = (metaInfo.metaInfo1 & 0x3f) | (value << 6);
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}
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BX_CPP_INLINE unsigned getVL(void) const {
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#if BX_SUPPORT_AVX
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return metaInfo.ia_opcode >> 12;
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#else
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return 0;
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#endif
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}
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BX_CPP_INLINE void setVL(unsigned value) {
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metaInfo.ia_opcode = (metaInfo.ia_opcode & 0xfff) | (value << 12);
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}
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BX_CPP_INLINE void setVvv(unsigned vvv) {
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metaData[BX_INSTR_METADATA_VVV] = vvv;
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}
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BX_CPP_INLINE unsigned vvv() const {
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return metaData[BX_INSTR_METADATA_VVV];
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}
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BX_CPP_INLINE unsigned modC0() const
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{
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// This is a cheaper way to test for modRM instructions where
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// the mod field is 0xc0. FetchDecode flags this condition since
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// it is quite common to be tested for.
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return metaInfo.metaInfo1 & (1<<4);
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}
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BX_CPP_INLINE unsigned assertModC0()
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{
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return metaInfo.metaInfo1 |= (1<<4);
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}
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};
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// <TAG-CLASS-INSTRUCTION-END>
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enum {
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#define bx_define_opcode(a, b, c, d, e) a,
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#include "ia_opcodes.h"
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BX_IA_LAST
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};
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#undef bx_define_opcode
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#endif
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