91fd4b3745
user can turn on/off use of native host specific inline asm statements. By default, this option is enabled, so you only need it to disable inline asms in your compile for now. Currently only on x86+GCC environments, will inline asm() statements be used. Eventually, other platforms could specify some asm()s; probably for endian issues such as byte-swapping and unaligned memory accesses. On x86, there are some inline asm()s which do the arithmetic EFLAGS processing so that the lazy flags handling is somewhat bypassed. Eventually, I'll add more, at least for the more common instructions. This adds a little extra performance.
557 lines
12 KiB
C++
557 lines
12 KiB
C++
/////////////////////////////////////////////////////////////////////////
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// $Id: logical32.cc,v 1.12 2002-09-23 17:59:17 kevinlawton Exp $
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/////////////////////////////////////////////////////////////////////////
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//
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// Copyright (C) 2001 MandrakeSoft S.A.
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//
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// MandrakeSoft S.A.
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// 43, rue d'Aboukir
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// 75002 Paris - France
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// http://www.linux-mandrake.com/
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// http://www.mandrakesoft.com/
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//
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// This library is free software; you can redistribute it and/or
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// modify it under the terms of the GNU Lesser General Public
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// License as published by the Free Software Foundation; either
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// version 2 of the License, or (at your option) any later version.
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//
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// This library is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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// Lesser General Public License for more details.
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//
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// You should have received a copy of the GNU Lesser General Public
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// License along with this library; if not, write to the Free Software
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// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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#define NEED_CPU_REG_SHORTCUTS 1
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#include "bochs.h"
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#define LOG_THIS BX_CPU_THIS_PTR
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void
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BX_CPU_C::XOR_EdGd(bxInstruction_c *i)
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{
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/* for 32 bit operand size mode */
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Bit32u op2_32, op1_32, result_32;
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/* op2_32 is a register, op2_addr is an index of a register */
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op2_32 = BX_READ_32BIT_REG(i->nnn());
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/* op1_32 is a register or memory reference */
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if (i->modC0()) {
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op1_32 = BX_READ_32BIT_REG(i->rm());
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}
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else {
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/* pointer, segment address pair */
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read_RMW_virtual_dword(i->seg(), RMAddr(i), &op1_32);
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}
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result_32 = op1_32 ^ op2_32;
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/* now write result back to destination */
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if (i->modC0()) {
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BX_WRITE_32BIT_REGZ(i->rm(), result_32);
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}
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else {
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Write_RMW_virtual_dword(result_32);
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}
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SET_FLAGS_OSZAPC_32(op1_32, op2_32, result_32, BX_INSTR_XOR32);
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}
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void
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BX_CPU_C::XOR_GdEd(bxInstruction_c *i)
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{
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/* for 32 bit operand size mode */
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Bit32u op1_32, op2_32, result_32;
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op1_32 = BX_READ_32BIT_REG(i->nnn());
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/* op2_32 is a register or memory reference */
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if (i->modC0()) {
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op2_32 = BX_READ_32BIT_REG(i->rm());
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}
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else {
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/* pointer, segment address pair */
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read_virtual_dword(i->seg(), RMAddr(i), &op2_32);
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}
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result_32 = op1_32 ^ op2_32;
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/* now write result back to destination */
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BX_WRITE_32BIT_REGZ(i->nnn(), result_32);
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SET_FLAGS_OSZAPC_32(op1_32, op2_32, result_32, BX_INSTR_XOR32);
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}
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void
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BX_CPU_C::XOR_EAXId(bxInstruction_c *i)
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{
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/* for 32 bit operand size mode */
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Bit32u op1_32, op2_32, sum_32;
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op1_32 = EAX;
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op2_32 = i->Id();
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sum_32 = op1_32 ^ op2_32;
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/* now write sum back to destination */
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#if BX_SUPPORT_X86_64
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RAX = sum_32;
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#else
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EAX = sum_32;
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#endif
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SET_FLAGS_OSZAPC_32(op1_32, op2_32, sum_32, BX_INSTR_XOR32);
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}
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void
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BX_CPU_C::XOR_EdId(bxInstruction_c *i)
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{
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Bit32u op2_32, op1_32, result_32;
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op2_32 = i->Id();
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/* op1_32 is a register or memory reference */
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if (i->modC0()) {
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op1_32 = BX_READ_32BIT_REG(i->rm());
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}
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else {
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/* pointer, segment address pair */
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read_RMW_virtual_dword(i->seg(), RMAddr(i), &op1_32);
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}
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result_32 = op1_32 ^ op2_32;
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/* now write result back to destination */
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if (i->modC0()) {
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BX_WRITE_32BIT_REGZ(i->rm(), result_32);
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}
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else {
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Write_RMW_virtual_dword(result_32);
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}
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SET_FLAGS_OSZAPC_32(op1_32, op2_32, result_32, BX_INSTR_XOR32);
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}
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void
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BX_CPU_C::OR_EdId(bxInstruction_c *i)
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{
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Bit32u op2_32, op1_32, result_32;
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op2_32 = i->Id();
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/* op1_32 is a register or memory reference */
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if (i->modC0()) {
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op1_32 = BX_READ_32BIT_REG(i->rm());
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}
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else {
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/* pointer, segment address pair */
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read_RMW_virtual_dword(i->seg(), RMAddr(i), &op1_32);
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}
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result_32 = op1_32 | op2_32;
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/* now write result back to destination */
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if (i->modC0()) {
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BX_WRITE_32BIT_REGZ(i->rm(), result_32);
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}
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else {
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Write_RMW_virtual_dword(result_32);
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}
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SET_FLAGS_OSZAPC_32(op1_32, op2_32, result_32, BX_INSTR_OR32);
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}
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void
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BX_CPU_C::NOT_Ed(bxInstruction_c *i)
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{
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Bit32u op1_32, result_32;
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/* op1 is a register or memory reference */
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if (i->modC0()) {
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op1_32 = BX_READ_32BIT_REG(i->rm());
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}
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else {
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/* pointer, segment address pair */
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read_RMW_virtual_dword(i->seg(), RMAddr(i), &op1_32);
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}
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result_32 = ~op1_32;
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/* now write result back to destination */
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if (i->modC0()) {
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BX_WRITE_32BIT_REGZ(i->rm(), result_32);
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}
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else {
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Write_RMW_virtual_dword(result_32);
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}
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}
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void
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BX_CPU_C::OR_EdGd(bxInstruction_c *i)
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{
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Bit32u op2_32, op1_32, result_32;
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/* op2_32 is a register, op2_addr is an index of a register */
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op2_32 = BX_READ_32BIT_REG(i->nnn());
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/* op1_32 is a register or memory reference */
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if (i->modC0()) {
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op1_32 = BX_READ_32BIT_REG(i->rm());
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}
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else {
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/* pointer, segment address pair */
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read_RMW_virtual_dword(i->seg(), RMAddr(i), &op1_32);
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}
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result_32 = op1_32 | op2_32;
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/* now write result back to destination */
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if (i->modC0()) {
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BX_WRITE_32BIT_REGZ(i->rm(), result_32);
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}
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else {
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Write_RMW_virtual_dword(result_32);
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}
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SET_FLAGS_OSZAPC_32(op1_32, op2_32, result_32, BX_INSTR_OR32);
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}
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void
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BX_CPU_C::OR_GdEd(bxInstruction_c *i)
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{
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Bit32u op1_32, op2_32, result_32;
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op1_32 = BX_READ_32BIT_REG(i->nnn());
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/* op2_32 is a register or memory reference */
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if (i->modC0()) {
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op2_32 = BX_READ_32BIT_REG(i->rm());
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}
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else {
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/* pointer, segment address pair */
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read_virtual_dword(i->seg(), RMAddr(i), &op2_32);
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}
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result_32 = op1_32 | op2_32;
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/* now write result back to destination */
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BX_WRITE_32BIT_REGZ(i->nnn(), result_32);
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SET_FLAGS_OSZAPC_32(op1_32, op2_32, result_32, BX_INSTR_OR32);
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}
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void
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BX_CPU_C::OR_EAXId(bxInstruction_c *i)
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{
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Bit32u op1_32, op2_32, sum_32;
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op1_32 = EAX;
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op2_32 = i->Id();
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sum_32 = op1_32 | op2_32;
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/* now write sum back to destination */
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#if BX_SUPPORT_X86_64
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RAX = sum_32;
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#else
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EAX = sum_32;
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#endif
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SET_FLAGS_OSZAPC_32(op1_32, op2_32, sum_32, BX_INSTR_OR32);
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}
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void
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BX_CPU_C::AND_EdGd(bxInstruction_c *i)
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{
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Bit32u op2_32, op1_32, result_32;
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op2_32 = BX_READ_32BIT_REG(i->nnn());
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if (i->modC0()) {
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op1_32 = BX_READ_32BIT_REG(i->rm());
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}
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else {
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read_RMW_virtual_dword(i->seg(), RMAddr(i), &op1_32);
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}
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result_32 = op1_32 & op2_32;
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if (i->modC0()) {
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BX_WRITE_32BIT_REGZ(i->rm(), result_32);
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}
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else {
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Write_RMW_virtual_dword(result_32);
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}
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#if (defined(__i386__) && defined(__GNUC__) && BX_SupportHostAsms)
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Bit32u flags32;
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asm (
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"andl %3, %1\n\t"
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"pushfl \n\t"
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"popl %0"
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: "=g" (flags32), "=r" (result_32)
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: "1" (op1_32), "g" (op2_32)
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: "cc"
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);
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BX_CPU_THIS_PTR eflags.val32 =
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(BX_CPU_THIS_PTR eflags.val32 & ~EFlagsOSZAPCMask) |
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(flags32 & EFlagsOSZAPCMask);
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BX_CPU_THIS_PTR lf_flags_status = 0;
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#else
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SET_FLAGS_OSZAPC_32(op1_32, op2_32, result_32, BX_INSTR_AND32);
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#endif
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}
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void
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BX_CPU_C::AND_GdEd(bxInstruction_c *i)
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{
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Bit32u op1_32, op2_32, result_32;
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op1_32 = BX_READ_32BIT_REG(i->nnn());
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if (i->modC0()) {
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op2_32 = BX_READ_32BIT_REG(i->rm());
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}
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else {
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read_virtual_dword(i->seg(), RMAddr(i), &op2_32);
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}
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result_32 = op1_32 & op2_32;
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BX_WRITE_32BIT_REGZ(i->nnn(), result_32);
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#if (defined(__i386__) && defined(__GNUC__) && BX_SupportHostAsms)
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Bit32u flags32;
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asm (
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"andl %3, %1\n\t"
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"pushfl \n\t"
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"popl %0"
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: "=g" (flags32), "=r" (result_32)
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: "1" (op1_32), "g" (op2_32)
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: "cc"
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);
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BX_CPU_THIS_PTR eflags.val32 =
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(BX_CPU_THIS_PTR eflags.val32 & ~EFlagsOSZAPCMask) |
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(flags32 & EFlagsOSZAPCMask);
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BX_CPU_THIS_PTR lf_flags_status = 0;
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#else
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SET_FLAGS_OSZAPC_32(op1_32, op2_32, result_32, BX_INSTR_AND32);
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#endif
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}
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void
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BX_CPU_C::AND_EAXId(bxInstruction_c *i)
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{
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Bit32u op1_32, op2_32, result_32;
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op1_32 = EAX;
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op2_32 = i->Id();
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result_32 = op1_32 & op2_32;
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#if BX_SUPPORT_X86_64
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RAX = result_32;
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#else
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EAX = result_32;
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#endif
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#if (defined(__i386__) && defined(__GNUC__) && BX_SupportHostAsms)
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Bit32u flags32;
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asm (
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"andl %3, %1\n\t"
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"pushfl \n\t"
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"popl %0"
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: "=g" (flags32), "=r" (result_32)
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: "1" (op1_32), "g" (op2_32)
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: "cc"
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);
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BX_CPU_THIS_PTR eflags.val32 =
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(BX_CPU_THIS_PTR eflags.val32 & ~EFlagsOSZAPCMask) |
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(flags32 & EFlagsOSZAPCMask);
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BX_CPU_THIS_PTR lf_flags_status = 0;
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#else
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SET_FLAGS_OSZAPC_32(op1_32, op2_32, result_32, BX_INSTR_AND32);
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#endif
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}
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void
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BX_CPU_C::AND_EdId(bxInstruction_c *i)
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{
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Bit32u op2_32, op1_32, result_32;
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op2_32 = i->Id();
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if (i->modC0()) {
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op1_32 = BX_READ_32BIT_REG(i->rm());
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}
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else {
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/* pointer, segment address pair */
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read_RMW_virtual_dword(i->seg(), RMAddr(i), &op1_32);
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}
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result_32 = op1_32 & op2_32;
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if (i->modC0()) {
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BX_WRITE_32BIT_REGZ(i->rm(), result_32);
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}
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else {
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Write_RMW_virtual_dword(result_32);
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}
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#if (defined(__i386__) && defined(__GNUC__) && BX_SupportHostAsms)
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Bit32u flags32;
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asm (
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"andl %3, %1\n\t"
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"pushfl \n\t"
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"popl %0"
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: "=g" (flags32), "=r" (result_32)
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: "1" (op1_32), "g" (op2_32)
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: "cc"
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);
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BX_CPU_THIS_PTR eflags.val32 =
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(BX_CPU_THIS_PTR eflags.val32 & ~EFlagsOSZAPCMask) |
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(flags32 & EFlagsOSZAPCMask);
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BX_CPU_THIS_PTR lf_flags_status = 0;
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#else
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SET_FLAGS_OSZAPC_32(op1_32, op2_32, result_32, BX_INSTR_AND32);
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#endif
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}
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void
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BX_CPU_C::TEST_EdGd(bxInstruction_c *i)
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{
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Bit32u op2_32, op1_32;
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/* op2_32 is a register, op2_addr is an index of a register */
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op2_32 = BX_READ_32BIT_REG(i->nnn());
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/* op1_32 is a register or memory reference */
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if (i->modC0()) {
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op1_32 = BX_READ_32BIT_REG(i->rm());
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}
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else {
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/* pointer, segment address pair */
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read_virtual_dword(i->seg(), RMAddr(i), &op1_32);
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}
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#if (defined(__i386__) && defined(__GNUC__) && BX_SupportHostAsms)
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Bit32u flags32;
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asm (
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"testl %2, %1\n\t"
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"pushfl \n\t"
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"popl %0"
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: "=g" (flags32)
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: "r" (op1_32), "g" (op2_32)
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: "cc"
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);
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BX_CPU_THIS_PTR eflags.val32 =
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(BX_CPU_THIS_PTR eflags.val32 & ~EFlagsOSZAPCMask) |
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(flags32 & EFlagsOSZAPCMask);
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BX_CPU_THIS_PTR lf_flags_status = 0;
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#else
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Bit32u result_32;
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result_32 = op1_32 & op2_32;
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SET_FLAGS_OSZAPC_32(op1_32, op2_32, result_32, BX_INSTR_TEST32);
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#endif
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}
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void
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BX_CPU_C::TEST_EAXId(bxInstruction_c *i)
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{
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Bit32u op2_32, op1_32;
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/* op1 is EAX register */
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op1_32 = EAX;
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/* op2 is imm32 */
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op2_32 = i->Id();
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#if (defined(__i386__) && defined(__GNUC__) && BX_SupportHostAsms)
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Bit32u flags32;
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asm (
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"testl %2, %1\n\t"
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"pushfl \n\t"
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"popl %0"
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: "=g" (flags32)
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: "r" (op1_32), "g" (op2_32)
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: "cc"
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);
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BX_CPU_THIS_PTR eflags.val32 =
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(BX_CPU_THIS_PTR eflags.val32 & ~EFlagsOSZAPCMask) |
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(flags32 & EFlagsOSZAPCMask);
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BX_CPU_THIS_PTR lf_flags_status = 0;
|
|
#else
|
|
Bit32u result_32;
|
|
result_32 = op1_32 & op2_32;
|
|
|
|
SET_FLAGS_OSZAPC_32(op1_32, op2_32, result_32, BX_INSTR_TEST32);
|
|
#endif
|
|
}
|
|
|
|
|
|
void
|
|
BX_CPU_C::TEST_EdId(bxInstruction_c *i)
|
|
{
|
|
Bit32u op2_32, op1_32;
|
|
|
|
/* op2 is imm32 */
|
|
op2_32 = i->Id();
|
|
|
|
/* op1_32 is a register or memory reference */
|
|
if (i->modC0()) {
|
|
op1_32 = BX_READ_32BIT_REG(i->rm());
|
|
}
|
|
else {
|
|
/* pointer, segment address pair */
|
|
read_virtual_dword(i->seg(), RMAddr(i), &op1_32);
|
|
}
|
|
|
|
#if (defined(__i386__) && defined(__GNUC__) && BX_SupportHostAsms)
|
|
Bit32u flags32;
|
|
asm (
|
|
"testl %2, %1\n\t"
|
|
"pushfl \n\t"
|
|
"popl %0"
|
|
: "=g" (flags32)
|
|
: "r" (op1_32), "g" (op2_32)
|
|
: "cc"
|
|
);
|
|
BX_CPU_THIS_PTR eflags.val32 =
|
|
(BX_CPU_THIS_PTR eflags.val32 & ~EFlagsOSZAPCMask) |
|
|
(flags32 & EFlagsOSZAPCMask);
|
|
BX_CPU_THIS_PTR lf_flags_status = 0;
|
|
#else
|
|
Bit32u result_32;
|
|
result_32 = op1_32 & op2_32;
|
|
|
|
SET_FLAGS_OSZAPC_32(op1_32, op2_32, result_32, BX_INSTR_TEST32);
|
|
#endif
|
|
}
|