386 lines
11 KiB
C++
386 lines
11 KiB
C++
/////////////////////////////////////////////////////////////////////////
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// $Id: memory.cc,v 1.33 2004-08-06 15:49:55 vruppert Exp $
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/////////////////////////////////////////////////////////////////////////
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//
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// Copyright (C) 2001 MandrakeSoft S.A.
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//
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// MandrakeSoft S.A.
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// 43, rue d'Aboukir
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// 75002 Paris - France
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// http://www.linux-mandrake.com/
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// http://www.mandrakesoft.com/
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//
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// This library is free software; you can redistribute it and/or
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// modify it under the terms of the GNU Lesser General Public
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// License as published by the Free Software Foundation; either
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// version 2 of the License, or (at your option) any later version.
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//
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// This library is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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// Lesser General Public License for more details.
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//
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// You should have received a copy of the GNU Lesser General Public
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// License along with this library; if not, write to the Free Software
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// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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#include "iodev/iodev.h"
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#define LOG_THIS BX_MEM_THIS
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#if BX_PROVIDE_CPU_MEMORY
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void BX_CPP_AttrRegparmN(3)
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BX_MEM_C::writePhysicalPage(BX_CPU_C *cpu, Bit32u addr, unsigned len, void *data)
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{
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Bit8u *data_ptr;
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Bit32u a20addr;
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// Note: accesses should always be contained within a single page now.
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#if BX_SUPPORT_IODEBUG
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bx_iodebug_c::mem_write(cpu, addr, len, data);
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#endif
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a20addr = A20ADDR(addr);
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struct memory_handler_struct *memory_handler = memory_handlers[a20addr >> 20];
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while (memory_handler) {
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if (memory_handler->begin <= a20addr &&
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memory_handler->end >= a20addr &&
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memory_handler->write_handler(a20addr, len, data, memory_handler->write_param))
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return;
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memory_handler = memory_handler->next;
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}
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BX_INSTR_PHY_WRITE(cpu->which_cpu(), a20addr, len);
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#if BX_DEBUGGER
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// (mch) Check for physical write break points, TODO
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// (bbd) Each breakpoint should have an associated CPU#, TODO
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for (int i = 0; i < num_write_watchpoints; i++)
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if (write_watchpoint[i] == a20addr) {
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BX_CPU(0)->watchpoint = a20addr;
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BX_CPU(0)->break_point = BREAK_POINT_WRITE;
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break;
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}
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#endif
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#if BX_SUPPORT_ICACHE
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if (a20addr < BX_MEM_THIS len)
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cpu->iCache.decWriteStamp(cpu, a20addr);
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#endif
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if ( a20addr <= BX_MEM_THIS len ) {
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// all of data is within limits of physical memory
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if ( (a20addr & 0xfff80000) != 0x00080000 ) {
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if (len == 4) {
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WriteHostDWordToLittleEndian(&vector[a20addr], *(Bit32u*)data);
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BX_DBG_DIRTY_PAGE(a20addr >> 12);
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return;
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}
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if (len == 2) {
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WriteHostWordToLittleEndian(&vector[a20addr], *(Bit16u*)data);
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BX_DBG_DIRTY_PAGE(a20addr >> 12);
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return;
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}
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if (len == 1) {
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* ((Bit8u *) (&vector[a20addr])) = * (Bit8u *) data;
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BX_DBG_DIRTY_PAGE(a20addr >> 12);
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return;
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}
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// len == other, just fall thru to special cases handling
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}
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#ifdef BX_LITTLE_ENDIAN
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data_ptr = (Bit8u *) data;
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#else // BX_BIG_ENDIAN
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data_ptr = (Bit8u *) data + (len - 1);
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#endif
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write_one:
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if ( (a20addr & 0xfff80000) != 0x00080000 ) {
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// addr *not* in range 00080000 .. 000FFFFF
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vector[a20addr] = *data_ptr;
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BX_DBG_DIRTY_PAGE(a20addr >> 12);
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inc_one:
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if (len == 1) return;
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len--;
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a20addr++;
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#ifdef BX_LITTLE_ENDIAN
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data_ptr++;
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#else // BX_BIG_ENDIAN
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data_ptr--;
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#endif
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goto write_one;
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}
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// addr in range 00080000 .. 000FFFFF
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if (a20addr <= 0x0009ffff) {
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// regular memory 80000 .. 9FFFF
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vector[a20addr] = *data_ptr;
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BX_DBG_DIRTY_PAGE(a20addr >> 12);
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goto inc_one;
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}
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// adapter ROM C0000 .. DFFFF
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// ROM BIOS memory E0000 .. FFFFF
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// (ignore write)
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//BX_INFO(("ROM lock %08x: len=%u",
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// (unsigned) a20addr, (unsigned) len));
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#if BX_SUPPORT_PCI == 0
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#if BX_SHADOW_RAM
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// Write it since its in shadow RAM
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vector[a20addr] = *data_ptr;
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BX_DBG_DIRTY_PAGE(a20addr >> 12);
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#else
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// ignore write to ROM
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#endif
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#else
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// Write Based on 440fx Programming
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if (bx_options.Oi440FXSupport->get () &&
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((a20addr >= 0xC0000) && (a20addr <= 0xFFFFF))) {
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switch (DEV_pci_wr_memtype(a20addr & 0xFC000)) {
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case 0x1: // Writes to ShadowRAM
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// BX_INFO(("Writing to ShadowRAM %08x, len %u ! ", (unsigned) a20addr, (unsigned) len));
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shadow[a20addr - 0xc0000] = *data_ptr;
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BX_DBG_DIRTY_PAGE(a20addr >> 12);
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goto inc_one;
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case 0x0: // Writes to ROM, Inhibit
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BX_DEBUG(("Write to ROM ignored: address %08x, data %02x", (unsigned) a20addr, *data_ptr));
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goto inc_one;
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default:
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BX_PANIC(("writePhysicalPage: default case"));
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goto inc_one;
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}
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}
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#endif
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goto inc_one;
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}
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else {
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// some or all of data is outside limits of physical memory
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unsigned i;
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#ifdef BX_LITTLE_ENDIAN
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data_ptr = (Bit8u *) data;
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#else // BX_BIG_ENDIAN
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data_ptr = (Bit8u *) data + (len - 1);
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#endif
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#if BX_SUPPORT_APIC
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bx_generic_apic_c *local_apic = &cpu->local_apic;
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bx_generic_apic_c *ioapic = bx_devices.ioapic;
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if (local_apic->is_selected (a20addr, len)) {
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local_apic->write (a20addr, (Bit32u *)data, len);
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return;
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} else if (ioapic->is_selected (a20addr, len)) {
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ioapic->write (a20addr, (Bit32u *)data, len);
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return;
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}
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else
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#endif
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for (i = 0; i < len; i++) {
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if (a20addr < BX_MEM_THIS len) {
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vector[a20addr] = *data_ptr;
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BX_DBG_DIRTY_PAGE(a20addr >> 12);
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}
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// otherwise ignore byte, since it overruns memory
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addr++;
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a20addr = (addr);
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#ifdef BX_LITTLE_ENDIAN
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data_ptr++;
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#else // BX_BIG_ENDIAN
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data_ptr--;
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#endif
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}
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return;
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}
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}
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void BX_CPP_AttrRegparmN(3)
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BX_MEM_C::readPhysicalPage(BX_CPU_C *cpu, Bit32u addr, unsigned len, void *data)
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{
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Bit8u *data_ptr;
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Bit32u a20addr;
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#if BX_SUPPORT_IODEBUG
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bx_iodebug_c::mem_read(cpu, addr, len, data);
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#endif
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a20addr = A20ADDR(addr);
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struct memory_handler_struct *memory_handler = memory_handlers[a20addr >> 20];
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while (memory_handler) {
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if (memory_handler->begin <= a20addr &&
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memory_handler->end >= a20addr &&
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memory_handler->read_handler(a20addr, len, data, memory_handler->read_param))
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return;
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memory_handler = memory_handler->next;
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}
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BX_INSTR_PHY_READ(cpu->which_cpu(), a20addr, len);
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#if BX_DEBUGGER
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// (mch) Check for physical read break points, TODO
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// (bbd) Each breakpoint should have an associated CPU#, TODO
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for (int i = 0; i < num_read_watchpoints; i++)
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if (read_watchpoint[i] == a20addr) {
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BX_CPU(0)->watchpoint = a20addr;
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BX_CPU(0)->break_point = BREAK_POINT_READ;
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break;
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}
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#endif
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if ( (a20addr + len) <= BX_MEM_THIS len ) {
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// all of data is within limits of physical memory
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if ( (a20addr & 0xfff80000) != 0x00080000 ) {
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if (len == 4) {
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ReadHostDWordFromLittleEndian(&vector[a20addr], * (Bit32u*) data);
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return;
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}
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if (len == 2) {
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ReadHostWordFromLittleEndian(&vector[a20addr], * (Bit16u*) data);
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return;
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}
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if (len == 1) {
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* (Bit8u *) data = * ((Bit8u *) (&vector[a20addr]));
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return;
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}
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// len == 3 case can just fall thru to special cases handling
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}
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#ifdef BX_LITTLE_ENDIAN
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data_ptr = (Bit8u *) data;
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#else // BX_BIG_ENDIAN
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data_ptr = (Bit8u *) data + (len - 1);
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#endif
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read_one:
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if ( (a20addr & 0xfff80000) != 0x00080000 ) {
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// addr *not* in range 00080000 .. 000FFFFF
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*data_ptr = vector[a20addr];
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inc_one:
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if (len == 1) return;
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len--;
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a20addr++;
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#ifdef BX_LITTLE_ENDIAN
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data_ptr++;
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#else // BX_BIG_ENDIAN
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data_ptr--;
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#endif
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goto read_one;
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}
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// addr in range 00080000 .. 000FFFFF
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#if BX_SUPPORT_PCI == 0
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if ((a20addr <= 0x0009ffff) || (a20addr >= 0x000c0000) ) {
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// regular memory 80000 .. 9FFFF, C0000 .. F0000
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*data_ptr = vector[a20addr];
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goto inc_one;
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}
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#else // #if BX_SUPPORT_PCI == 0
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if (a20addr <= 0x0009ffff) {
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*data_ptr = vector[a20addr];
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goto inc_one;
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}
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if ((a20addr >= 0xC0000) && (a20addr <= 0xFFFFF)) {
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if (!bx_options.Oi440FXSupport->get ()) {
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*data_ptr = vector[a20addr];
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goto inc_one;
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}
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else {
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switch (DEV_pci_rd_memtype(a20addr & 0xFC000)) {
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case 0x1: // Read from ShadowRAM
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*data_ptr = shadow[a20addr - 0xc0000];
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BX_INFO(("Reading from ShadowRAM %08x, Data %02x ", (unsigned) a20addr, *data_ptr));
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goto inc_one;
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case 0x0: // Read from ROM
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*data_ptr = vector[a20addr];
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//BX_INFO(("Reading from ROM %08x, Data %02x ", (unsigned) a20addr, *data_ptr));
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goto inc_one;
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default:
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BX_PANIC(("::readPhysicalPage: default case"));
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}
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}
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goto inc_one;
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}
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#endif // #if BX_SUPPORT_PCI == 0
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}
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else {
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// some or all of data is outside limits of physical memory
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unsigned i;
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#ifdef BX_LITTLE_ENDIAN
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data_ptr = (Bit8u *) data;
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#else // BX_BIG_ENDIAN
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data_ptr = (Bit8u *) data + (len - 1);
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#endif
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#if BX_SUPPORT_APIC
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bx_generic_apic_c *local_apic = &cpu->local_apic;
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bx_generic_apic_c *ioapic = bx_devices.ioapic;
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if (local_apic->is_selected (addr, len)) {
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local_apic->read (addr, data, len);
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return;
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} else if (ioapic->is_selected (addr, len)) {
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ioapic->read (addr, data, len);
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return;
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}
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#endif
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for (i = 0; i < len; i++) {
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#if BX_SUPPORT_PCI == 0
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if (a20addr < BX_MEM_THIS len)
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*data_ptr = vector[a20addr];
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else
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*data_ptr = 0xff;
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#else // BX_SUPPORT_PCI == 0
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if (a20addr < BX_MEM_THIS len) {
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if ((a20addr >= 0x000C0000) && (a20addr <= 0x000FFFFF)) {
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if (!bx_options.Oi440FXSupport->get ())
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*data_ptr = vector[a20addr];
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else {
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switch (DEV_pci_rd_memtype(a20addr & 0xFC000)) {
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case 0x0: // Read from ROM
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*data_ptr = vector[a20addr];
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//BX_INFO(("Reading from ROM %08x, Data %02x ", (unsigned) a20addr, *data_ptr));
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break;
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case 0x1: // Read from Shadow RAM
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*data_ptr = shadow[a20addr - 0xc0000];
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BX_INFO(("Reading from ShadowRAM %08x, Data %02x ", (unsigned) a20addr, *data_ptr));
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break;
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default:
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BX_PANIC(("readPhysicalPage: default case"));
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} // Switch
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}
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}
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else {
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*data_ptr = vector[a20addr];
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BX_INFO(("Reading from Norm %08x, Data %02x ", (unsigned) a20addr, *data_ptr));
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}
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}
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else
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*data_ptr = 0xff;
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#endif // BX_SUPPORT_PCI == 0
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addr++;
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a20addr = (addr);
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#ifdef BX_LITTLE_ENDIAN
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data_ptr++;
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#else // BX_BIG_ENDIAN
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data_ptr--;
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#endif
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}
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return;
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}
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}
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#endif // #if BX_PROVIDE_CPU_MEMORY
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