241 lines
7.6 KiB
C++
241 lines
7.6 KiB
C++
/////////////////////////////////////////////////////////////////////////
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// $Id: pcivga.cc,v 1.26 2009-04-10 14:41:29 vruppert Exp $
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/////////////////////////////////////////////////////////////////////////
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//
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// Copyright (C) 2002,2003 Mike Nordell
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//
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// This library is free software; you can redistribute it and/or
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// modify it under the terms of the GNU Lesser General Public
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// License as published by the Free Software Foundation; either
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// version 2 of the License, or (at your option) any later version.
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//
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// This library is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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// Lesser General Public License for more details.
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//
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// You should have received a copy of the GNU Lesser General Public
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// License along with this library; if not, write to the Free Software
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// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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//
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// Experimental PCI VGA adapter
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//
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// Note: This "driver" was created for the SOLE PURPOSE of getting BeOS
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// to boot. It currently does NOTHING more than presenting a generic VGA
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// device on the PCI bus. ALL gfx in/out-put is still handled by the VGA code.
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// Furthermore, almost all of the PCI registers are currently acting like RAM.
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// Define BX_PLUGGABLE in files that can be compiled into plugins. For
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// platforms that require a special tag on exported symbols, BX_PLUGGABLE
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// is used to know when we are exporting symbols and when we are importing.
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#define BX_PLUGGABLE
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#include "iodev.h"
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#if BX_SUPPORT_PCI && BX_SUPPORT_PCIVGA
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#include "pci.h"
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#include "pcivga.h"
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#define LOG_THIS thePciVgaAdapter->
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bx_pcivga_c* thePciVgaAdapter = 0;
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int libpcivga_LTX_plugin_init(plugin_t *plugin, plugintype_t type, int argc, char *argv[])
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{
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thePciVgaAdapter = new bx_pcivga_c();
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BX_REGISTER_DEVICE_DEVMODEL(plugin, type, thePciVgaAdapter, BX_PLUGIN_PCIVGA);
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return 0; // Success
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}
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void libpcivga_LTX_plugin_fini(void)
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{
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delete thePciVgaAdapter;
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}
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bx_pcivga_c::bx_pcivga_c()
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{
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put("PCIVGA");
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}
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bx_pcivga_c::~bx_pcivga_c()
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{
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BX_DEBUG(("Exit"));
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}
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void bx_pcivga_c::init(void)
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{
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// called once when bochs initializes
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Bit8u devfunc = 0x00;
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unsigned i;
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DEV_register_pci_handlers(this, &devfunc, BX_PLUGIN_PCIVGA,
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"Experimental PCI VGA");
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for (i=0; i<256; i++) {
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BX_PCIVGA_THIS s.pci_conf[i] = 0x0;
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}
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// readonly registers
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static const struct init_vals_t {
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unsigned addr;
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unsigned char val;
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} init_vals[] = {
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// Note that the values for vendor and device id are selected at random!
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// There might actually be "real" values for "experimental" vendor and
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// device that should be used!
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{ 0x00, 0x34 }, { 0x01, 0x12 }, // 0x1234 - experimental vendor
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{ 0x02, 0x11 }, { 0x03, 0x11 }, // 0x1111 - experimental device
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{ 0x0a, 0x00 }, // class_sub VGA controller
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{ 0x0b, 0x03 }, // class_base display
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{ 0x0e, 0x00 } // header_type_generic
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};
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for (i = 0; i < sizeof(init_vals) / sizeof(*init_vals); ++i) {
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BX_PCIVGA_THIS s.pci_conf[init_vals[i].addr] = init_vals[i].val;
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}
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WriteHostDWordToLittleEndian(&BX_PCIVGA_THIS s.pci_conf[0x10], 0x08);
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BX_PCIVGA_THIS s.base_address = 0;
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}
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void bx_pcivga_c::reset(unsigned type)
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{
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static const struct reset_vals_t {
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unsigned addr;
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unsigned char val;
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} reset_vals[] = {
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{ 0x04, 0x03 }, { 0x05, 0x00 }, // command_io + command_mem
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{ 0x06, 0x00 }, { 0x07, 0x02 } // status_devsel_medium
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};
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for (unsigned i = 0; i < sizeof(reset_vals) / sizeof(*reset_vals); ++i) {
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BX_PCIVGA_THIS s.pci_conf[reset_vals[i].addr] = reset_vals[i].val;
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}
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}
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void bx_pcivga_c::register_state(void)
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{
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bx_list_c *list = new bx_list_c(SIM->get_bochs_root(), "pcivga", "PCI VGA Adapter State", 1);
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register_pci_state(list, BX_PCIVGA_THIS s.pci_conf);
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}
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void bx_pcivga_c::after_restore_state(void)
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{
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if (DEV_vbe_set_base_addr(&BX_PCIVGA_THIS s.base_address,
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&BX_PCIVGA_THIS s.pci_conf[0x10])) {
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BX_INFO(("new base address: 0x%08x", BX_PCIVGA_THIS s.base_address));
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}
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}
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// pci configuration space read callback handler
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Bit32u bx_pcivga_c::pci_read_handler(Bit8u address, unsigned io_len)
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{
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Bit32u value = 0;
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if (io_len > 4 || io_len == 0) {
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BX_DEBUG(("Experimental PCIVGA read register 0x%02x, len=%u !",
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(unsigned) address, (unsigned) io_len));
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return 0xffffffff;
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}
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const char* pszName = " ";
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switch (address) {
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case 0x00: if (io_len == 2) {
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pszName = "(vendor id) ";
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} else if (io_len == 4) {
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pszName = "(vendor + device) ";
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}
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break;
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case 0x04: if (io_len == 2) {
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pszName = "(command) ";
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} else if (io_len == 4) {
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pszName = "(command+status) ";
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}
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break;
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case 0x08: if (io_len == 1) {
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pszName = "(revision id) ";
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} else if (io_len == 4) {
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pszName = "(rev.+class code) ";
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}
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break;
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case 0x0c: pszName = "(cache line size) "; break;
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case 0x10: pszName = "(base address #0) "; break;
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case 0x28: pszName = "(cardbus cis) "; break;
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case 0x2c: pszName = "(subsys. vendor+) "; break;
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case 0x30: pszName = "(rom base) "; break;
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case 0x3c: pszName = "(interrupt line+) "; break;
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case 0x3d: pszName = "(interrupt pin) "; break;
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}
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// This odd code is to display only what bytes actually were read.
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char szTmp[9];
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char szTmp2[3];
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szTmp[0] = '\0';
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szTmp2[0] = '\0';
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for (unsigned i=0; i<io_len; i++) {
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value |= (BX_PCIVGA_THIS s.pci_conf[address+i] << (i*8));
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sprintf(szTmp2, "%02x", (BX_PCIVGA_THIS s.pci_conf[address+i]));
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strrev(szTmp2);
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strcat(szTmp, szTmp2);
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}
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strrev(szTmp);
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BX_DEBUG(("Experimental PCIVGA read register 0x%02x %svalue 0x%s",
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address, pszName, szTmp));
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return value;
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}
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// static pci configuration space write callback handler
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void bx_pcivga_c::pci_write_handler(Bit8u address, Bit32u value, unsigned io_len)
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{
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unsigned i;
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unsigned write_addr;
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Bit8u new_value, old_value;
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bx_bool baseaddr_change = 0;
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if ((address >= 0x14) && (address < 0x34))
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return;
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if (io_len <= 4) {
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// This odd code is to display only what bytes actually were written.
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char szTmp[9];
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char szTmp2[3];
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szTmp[0] = '\0';
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szTmp2[0] = '\0';
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for (i = 0; i < io_len; i++) {
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write_addr = address + i;
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old_value = BX_PCIVGA_THIS s.pci_conf[write_addr];
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new_value = (Bit8u)(value & 0xff);
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switch (write_addr) {
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case 0x04: // disallowing write to command
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case 0x06: // disallowing write to status lo-byte (is that expected?)
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new_value = old_value;
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strcpy(szTmp2, "..");
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break;
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case 0x10: // base address #0
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new_value = (new_value & 0xf0) | (old_value & 0x0f);
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case 0x11: case 0x12: case 0x13:
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baseaddr_change |= (old_value != new_value);
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default:
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sprintf(szTmp2, "%02x", new_value);
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}
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BX_PCIVGA_THIS s.pci_conf[write_addr] = new_value;
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value >>= 8;
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strrev(szTmp2);
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strcat(szTmp, szTmp2);
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}
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if (baseaddr_change) {
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if (DEV_vbe_set_base_addr(&BX_PCIVGA_THIS s.base_address,
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&BX_PCIVGA_THIS s.pci_conf[0x10])) {
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BX_INFO(("new base address: 0x%08x", BX_PCIVGA_THIS s.base_address));
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}
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}
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strrev(szTmp);
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BX_DEBUG(("Experimental PCIVGA write register 0x%02x value 0x%s", address, szTmp));
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}
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}
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#endif // BX_SUPPORT_PCI && BX_SUPPORT_PCIVGA
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