0d7a5fdf3c
All the EFLAGS bits used to be cached in separate fields. I left a few of them in separate fields for now - might remove them at some point also. When the arithmetic fields are known (ie they're not in lazy mode), they are all cached in a 32-bit EFLAGS image, just like the x86 EFLAGS register expects. All other eflags are store in the 32-bit register also, with a few also mirrored in separate fields for now. The reason I did this, was so that on x86 hosts, asm() statements can be #ifdef'd in to do the calculation and get the native eflags results very cheaply. Just to test that it works, I coded ADD_EdId() and ADD_EwIw() with some conditionally compiled asm()s for accelerated eflags processing and it works. -Kevin
913 lines
20 KiB
C++
913 lines
20 KiB
C++
/////////////////////////////////////////////////////////////////////////
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// $Id: arith32.cc,v 1.9 2002-09-08 04:08:14 kevinlawton Exp $
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/////////////////////////////////////////////////////////////////////////
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//
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// Copyright (C) 2001 MandrakeSoft S.A.
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//
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// MandrakeSoft S.A.
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// 43, rue d'Aboukir
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// 75002 Paris - France
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// http://www.linux-mandrake.com/
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// http://www.mandrakesoft.com/
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//
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// This library is free software; you can redistribute it and/or
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// modify it under the terms of the GNU Lesser General Public
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// License as published by the Free Software Foundation; either
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// version 2 of the License, or (at your option) any later version.
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//
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// This library is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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// Lesser General Public License for more details.
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//
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// You should have received a copy of the GNU Lesser General Public
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// License along with this library; if not, write to the Free Software
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// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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#define NEED_CPU_REG_SHORTCUTS 1
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#include "bochs.h"
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#define LOG_THIS BX_CPU_THIS_PTR
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void
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BX_CPU_C::INC_ERX(BxInstruction_t *i)
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{
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Bit32u erx;
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erx = ++ BX_CPU_THIS_PTR gen_reg[i->b1 & 0x07].erx;
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SET_FLAGS_OSZAP_32(0, 0, erx, BX_INSTR_INC32);
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}
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void
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BX_CPU_C::DEC_ERX(BxInstruction_t *i)
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{
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Bit32u erx;
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erx = -- BX_CPU_THIS_PTR gen_reg[i->b1 & 0x07].erx;
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SET_FLAGS_OSZAP_32(0, 0, erx, BX_INSTR_DEC32);
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}
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void
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BX_CPU_C::ADD_EdGd(BxInstruction_t *i)
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{
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/* for 32 bit operand size mode */
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Bit32u op2_32, op1_32, sum_32;
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/* op2_32 is a register, i->rm_addr is an index of a register */
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op2_32 = BX_READ_32BIT_REG(i->nnn);
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/* op1_32 is a register or memory reference */
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if (i->mod == 0xc0) {
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op1_32 = BX_READ_32BIT_REG(i->rm);
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}
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else {
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/* pointer, segment address pair */
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read_RMW_virtual_dword(i->seg, i->rm_addr, &op1_32);
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}
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sum_32 = op1_32 + op2_32;
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/* now write sum back to destination */
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if (i->mod == 0xc0) {
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BX_WRITE_32BIT_REG(i->rm, sum_32);
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}
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else {
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Write_RMW_virtual_dword(sum_32);
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}
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SET_FLAGS_OSZAPC_32(op1_32, op2_32, sum_32, BX_INSTR_ADD32);
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}
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void
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BX_CPU_C::ADD_GdEd(BxInstruction_t *i)
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{
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/* for 32 bit operand size mode */
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Bit32u op1_32, op2_32, sum_32;
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/* op1_32 is a register, i->rm_addr is an index of a register */
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op1_32 = BX_READ_32BIT_REG(i->nnn);
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/* op2_32 is a register or memory reference */
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if (i->mod == 0xc0) {
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op2_32 = BX_READ_32BIT_REG(i->rm);
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}
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else {
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/* pointer, segment address pair */
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read_virtual_dword(i->seg, i->rm_addr, &op2_32);
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}
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sum_32 = op1_32 + op2_32;
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/* now write sum back to destination */
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BX_WRITE_32BIT_REG(i->nnn, sum_32);
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SET_FLAGS_OSZAPC_32(op1_32, op2_32, sum_32, BX_INSTR_ADD32);
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}
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void
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BX_CPU_C::ADD_EAXId(BxInstruction_t *i)
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{
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/* for 32 bit operand size mode */
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Bit32u op1_32, op2_32, sum_32;
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op1_32 = EAX;
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op2_32 = i->Id;
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sum_32 = op1_32 + op2_32;
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/* now write sum back to destination */
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EAX = sum_32;
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SET_FLAGS_OSZAPC_32(op1_32, op2_32, sum_32, BX_INSTR_ADD32);
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}
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void
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BX_CPU_C::ADC_EdGd(BxInstruction_t *i)
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{
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Boolean temp_CF;
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temp_CF = get_CF();
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/* for 32 bit operand size mode */
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Bit32u op2_32, op1_32, sum_32;
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/* op2_32 is a register, i->rm_addr is an index of a register */
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op2_32 = BX_READ_32BIT_REG(i->nnn);
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/* op1_32 is a register or memory reference */
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if (i->mod == 0xc0) {
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op1_32 = BX_READ_32BIT_REG(i->rm);
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}
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else {
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/* pointer, segment address pair */
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read_RMW_virtual_dword(i->seg, i->rm_addr, &op1_32);
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}
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sum_32 = op1_32 + op2_32 + temp_CF;
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/* now write sum back to destination */
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if (i->mod == 0xc0) {
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BX_WRITE_32BIT_REG(i->rm, sum_32);
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}
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else {
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Write_RMW_virtual_dword(sum_32);
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}
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SET_FLAGS_OSZAPC_32_CF(op1_32, op2_32, sum_32, BX_INSTR_ADC32,
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temp_CF);
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}
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void
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BX_CPU_C::ADC_GdEd(BxInstruction_t *i)
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{
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Boolean temp_CF;
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temp_CF = get_CF();
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/* for 32 bit operand size mode */
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Bit32u op1_32, op2_32, sum_32;
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/* op1_32 is a register, i->rm_addr is an index of a register */
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op1_32 = BX_READ_32BIT_REG(i->nnn);
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/* op2_32 is a register or memory reference */
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if (i->mod == 0xc0) {
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op2_32 = BX_READ_32BIT_REG(i->rm);
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}
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else {
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/* pointer, segment address pair */
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read_virtual_dword(i->seg, i->rm_addr, &op2_32);
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}
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sum_32 = op1_32 + op2_32 + temp_CF;
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/* now write sum back to destination */
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BX_WRITE_32BIT_REG(i->nnn, sum_32);
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SET_FLAGS_OSZAPC_32_CF(op1_32, op2_32, sum_32, BX_INSTR_ADC32,
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temp_CF);
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}
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void
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BX_CPU_C::ADC_EAXId(BxInstruction_t *i)
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{
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Boolean temp_CF;
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temp_CF = get_CF();
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/* for 32 bit operand size mode */
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Bit32u op1_32, op2_32, sum_32;
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op1_32 = EAX;
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op2_32 = i->Id;
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sum_32 = op1_32 + op2_32 + temp_CF;
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/* now write sum back to destination */
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EAX = sum_32;
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SET_FLAGS_OSZAPC_32_CF(op1_32, op2_32, sum_32, BX_INSTR_ADC32,
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temp_CF);
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}
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void
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BX_CPU_C::SBB_EdGd(BxInstruction_t *i)
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{
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Boolean temp_CF;
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temp_CF = get_CF();
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/* for 32 bit operand size mode */
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Bit32u op2_32, op1_32, diff_32;
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/* op2_32 is a register, i->rm_addr is an index of a register */
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op2_32 = BX_READ_32BIT_REG(i->nnn);
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/* op1_32 is a register or memory reference */
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if (i->mod == 0xc0) {
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op1_32 = BX_READ_32BIT_REG(i->rm);
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}
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else {
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/* pointer, segment address pair */
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read_RMW_virtual_dword(i->seg, i->rm_addr, &op1_32);
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}
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diff_32 = op1_32 - (op2_32 + temp_CF);
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/* now write diff back to destination */
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if (i->mod == 0xc0) {
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BX_WRITE_32BIT_REG(i->rm, diff_32);
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}
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else {
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Write_RMW_virtual_dword(diff_32);
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}
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SET_FLAGS_OSZAPC_32_CF(op1_32, op2_32, diff_32, BX_INSTR_SBB32,
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temp_CF);
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}
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void
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BX_CPU_C::SBB_GdEd(BxInstruction_t *i)
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{
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Boolean temp_CF;
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temp_CF = get_CF();
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/* for 32 bit operand size mode */
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Bit32u op1_32, op2_32, diff_32;
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/* op1_32 is a register, i->rm_addr is an index of a register */
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op1_32 = BX_READ_32BIT_REG(i->nnn);
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/* op2_32 is a register or memory reference */
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if (i->mod == 0xc0) {
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op2_32 = BX_READ_32BIT_REG(i->rm);
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}
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else {
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/* pointer, segment address pair */
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read_virtual_dword(i->seg, i->rm_addr, &op2_32);
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}
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diff_32 = op1_32 - (op2_32 + temp_CF);
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/* now write diff back to destination */
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BX_WRITE_32BIT_REG(i->nnn, diff_32);
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SET_FLAGS_OSZAPC_32_CF(op1_32, op2_32, diff_32, BX_INSTR_SBB32,
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temp_CF);
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}
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void
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BX_CPU_C::SBB_EAXId(BxInstruction_t *i)
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{
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Boolean temp_CF;
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temp_CF = get_CF();
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/* for 32 bit operand size mode */
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Bit32u op1_32, op2_32, diff_32;
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op1_32 = EAX;
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op2_32 = i->Id;
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diff_32 = op1_32 - (op2_32 + temp_CF);
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/* now write diff back to destination */
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EAX = diff_32;
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SET_FLAGS_OSZAPC_32_CF(op1_32, op2_32, diff_32, BX_INSTR_SBB32,
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temp_CF);
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}
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void
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BX_CPU_C::SBB_EdId(BxInstruction_t *i)
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{
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Boolean temp_CF;
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temp_CF = get_CF();
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/* for 32 bit operand size mode */
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Bit32u op2_32, op1_32, diff_32;
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op2_32 = i->Id;
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/* op1_32 is a register or memory reference */
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if (i->mod == 0xc0) {
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op1_32 = BX_READ_32BIT_REG(i->rm);
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}
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else {
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/* pointer, segment address pair */
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read_RMW_virtual_dword(i->seg, i->rm_addr, &op1_32);
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}
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diff_32 = op1_32 - (op2_32 + temp_CF);
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/* now write diff back to destination */
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if (i->mod == 0xc0) {
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BX_WRITE_32BIT_REG(i->rm, diff_32);
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}
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else {
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Write_RMW_virtual_dword(diff_32);
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}
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SET_FLAGS_OSZAPC_32_CF(op1_32, op2_32, diff_32, BX_INSTR_SBB32,
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temp_CF);
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}
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void
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BX_CPU_C::SUB_EdGd(BxInstruction_t *i)
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{
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/* for 32 bit operand size mode */
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Bit32u op2_32, op1_32, diff_32;
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/* op2_32 is a register, i->rm_addr is an index of a register */
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op2_32 = BX_READ_32BIT_REG(i->nnn);
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/* op1_32 is a register or memory reference */
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if (i->mod == 0xc0) {
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op1_32 = BX_READ_32BIT_REG(i->rm);
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}
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else {
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/* pointer, segment address pair */
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read_RMW_virtual_dword(i->seg, i->rm_addr, &op1_32);
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}
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diff_32 = op1_32 - op2_32;
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/* now write diff back to destination */
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if (i->mod == 0xc0) {
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BX_WRITE_32BIT_REG(i->rm, diff_32);
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}
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else {
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Write_RMW_virtual_dword(diff_32);
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}
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SET_FLAGS_OSZAPC_32(op1_32, op2_32, diff_32, BX_INSTR_SUB32);
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}
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void
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BX_CPU_C::SUB_GdEd(BxInstruction_t *i)
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{
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/* for 32 bit operand size mode */
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Bit32u op1_32, op2_32, diff_32;
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/* op1_32 is a register, i->rm_addr is an index of a register */
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op1_32 = BX_READ_32BIT_REG(i->nnn);
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/* op2_32 is a register or memory reference */
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if (i->mod == 0xc0) {
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op2_32 = BX_READ_32BIT_REG(i->rm);
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}
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else {
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/* pointer, segment address pair */
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read_virtual_dword(i->seg, i->rm_addr, &op2_32);
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}
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diff_32 = op1_32 - op2_32;
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/* now write diff back to destination */
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BX_WRITE_32BIT_REG(i->nnn, diff_32);
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SET_FLAGS_OSZAPC_32(op1_32, op2_32, diff_32, BX_INSTR_SUB32);
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}
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void
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BX_CPU_C::SUB_EAXId(BxInstruction_t *i)
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{
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/* for 32 bit operand size mode */
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Bit32u op1_32, op2_32, diff_32;
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op1_32 = EAX;
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op2_32 = i->Id;
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diff_32 = op1_32 - op2_32;
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/* now write diff back to destination */
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EAX = diff_32;
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SET_FLAGS_OSZAPC_32(op1_32, op2_32, diff_32, BX_INSTR_SUB32);
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}
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void
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BX_CPU_C::CMP_EdGd(BxInstruction_t *i)
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{
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/* for 32 bit operand size mode */
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Bit32u op2_32, op1_32, diff_32;
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/* op2_32 is a register, i->rm_addr is an index of a register */
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op2_32 = BX_READ_32BIT_REG(i->nnn);
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/* op1_32 is a register or memory reference */
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if (i->mod == 0xc0) {
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op1_32 = BX_READ_32BIT_REG(i->rm);
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}
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else {
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/* pointer, segment address pair */
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read_virtual_dword(i->seg, i->rm_addr, &op1_32);
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}
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diff_32 = op1_32 - op2_32;
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SET_FLAGS_OSZAPC_32(op1_32, op2_32, diff_32, BX_INSTR_CMP32);
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}
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void
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BX_CPU_C::CMP_GdEd(BxInstruction_t *i)
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{
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/* for 32 bit operand size mode */
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Bit32u op1_32, op2_32, diff_32;
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/* op1_32 is a register, i->rm_addr is an index of a register */
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op1_32 = BX_READ_32BIT_REG(i->nnn);
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/* op2_32 is a register or memory reference */
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if (i->mod == 0xc0) {
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op2_32 = BX_READ_32BIT_REG(i->rm);
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}
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else {
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/* pointer, segment address pair */
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read_virtual_dword(i->seg, i->rm_addr, &op2_32);
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}
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diff_32 = op1_32 - op2_32;
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SET_FLAGS_OSZAPC_32(op1_32, op2_32, diff_32, BX_INSTR_CMP32);
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}
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|
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void
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BX_CPU_C::CMP_EAXId(BxInstruction_t *i)
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{
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|
/* for 32 bit operand size mode */
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Bit32u op1_32, op2_32, diff_32;
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op1_32 = EAX;
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op2_32 = i->Id;
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diff_32 = op1_32 - op2_32;
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SET_FLAGS_OSZAPC_32(op1_32, op2_32, diff_32, BX_INSTR_CMP32);
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}
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void
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BX_CPU_C::CWDE(BxInstruction_t *i)
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{
|
|
/* CBW: no flags are effected */
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EAX = (Bit16s) AX;
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}
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|
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void
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BX_CPU_C::CDQ(BxInstruction_t *i)
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{
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/* CWD: no flags are affected */
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|
|
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if (EAX & 0x80000000) {
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EDX = 0xFFFFFFFF;
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}
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else {
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EDX = 0x00000000;
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}
|
|
}
|
|
|
|
// Some info on the opcodes at {0F,A6} and {0F,A7}
|
|
// On 386 steps A0-B0:
|
|
// {OF,A6} = XBTS
|
|
// {OF,A7} = IBTS
|
|
// On 486 steps A0-B0:
|
|
// {OF,A6} = CMPXCHG 8
|
|
// {OF,A7} = CMPXCHG 16|32
|
|
//
|
|
// On 486 >= B steps, and further processors, the
|
|
// CMPXCHG instructions were moved to opcodes:
|
|
// {OF,B0} = CMPXCHG 8
|
|
// {OF,B1} = CMPXCHG 16|32
|
|
|
|
void
|
|
BX_CPU_C::CMPXCHG_XBTS(BxInstruction_t *i)
|
|
{
|
|
BX_INFO(("CMPXCHG_XBTS:"));
|
|
UndefinedOpcode(i);
|
|
}
|
|
|
|
void
|
|
BX_CPU_C::CMPXCHG_IBTS(BxInstruction_t *i)
|
|
{
|
|
BX_INFO(("CMPXCHG_IBTS:"));
|
|
UndefinedOpcode(i);
|
|
}
|
|
|
|
|
|
void
|
|
BX_CPU_C::XADD_EdGd(BxInstruction_t *i)
|
|
{
|
|
#if (BX_CPU_LEVEL >= 4) || (BX_CPU_LEVEL_HACKED >= 4)
|
|
|
|
Bit32u op2_32, op1_32, sum_32;
|
|
|
|
/* XADD dst(r/m), src(r)
|
|
* temp <-- src + dst | sum = op2 + op1
|
|
* src <-- dst | op2 = op1
|
|
* dst <-- tmp | op1 = sum
|
|
*/
|
|
|
|
/* op2 is a register, i->rm_addr is an index of a register */
|
|
op2_32 = BX_READ_32BIT_REG(i->nnn);
|
|
|
|
/* op1 is a register or memory reference */
|
|
if (i->mod == 0xc0) {
|
|
op1_32 = BX_READ_32BIT_REG(i->rm);
|
|
}
|
|
else {
|
|
/* pointer, segment address pair */
|
|
read_RMW_virtual_dword(i->seg, i->rm_addr, &op1_32);
|
|
}
|
|
|
|
sum_32 = op1_32 + op2_32;
|
|
|
|
/* now write sum back to destination */
|
|
if (i->mod == 0xc0) {
|
|
// and write destination into source
|
|
// Note: if both op1 & op2 are registers, the last one written
|
|
// should be the sum, as op1 & op2 may be the same register.
|
|
// For example: XADD AL, AL
|
|
BX_WRITE_32BIT_REG(i->nnn, op1_32);
|
|
BX_WRITE_32BIT_REG(i->rm, sum_32);
|
|
}
|
|
else {
|
|
Write_RMW_virtual_dword(sum_32);
|
|
/* and write destination into source */
|
|
BX_WRITE_32BIT_REG(i->nnn, op1_32);
|
|
}
|
|
|
|
|
|
SET_FLAGS_OSZAPC_32(op1_32, op2_32, sum_32, BX_INSTR_XADD32);
|
|
#else
|
|
|
|
#endif
|
|
}
|
|
|
|
|
|
|
|
void
|
|
BX_CPU_C::ADD_EdId(BxInstruction_t *i)
|
|
{
|
|
Bit32u op2_32, op1_32, sum_32;
|
|
|
|
op2_32 = i->Id;
|
|
|
|
/* op1_32 is a register or memory reference */
|
|
if (i->mod == 0xc0) {
|
|
op1_32 = BX_READ_32BIT_REG(i->rm);
|
|
}
|
|
else {
|
|
/* pointer, segment address pair */
|
|
read_RMW_virtual_dword(i->seg, i->rm_addr, &op1_32);
|
|
}
|
|
|
|
#if (defined(__i386__) && defined(__GNUC__))
|
|
Bit32u flags32;
|
|
asm volatile (
|
|
"addl %3, %1\n\t"
|
|
"pushfl \n\t"
|
|
"popl %0"
|
|
: "=g" (flags32), "=r" (sum_32)
|
|
: "1" (op1_32), "g" (op2_32)
|
|
: "memory", "cc"
|
|
);
|
|
#else
|
|
sum_32 = op1_32 + op2_32;
|
|
#endif
|
|
|
|
/* now write sum back to destination */
|
|
if (i->mod == 0xc0) {
|
|
BX_WRITE_32BIT_REG(i->rm, sum_32);
|
|
}
|
|
else {
|
|
Write_RMW_virtual_dword(sum_32);
|
|
}
|
|
|
|
#if (defined(__i386__) && defined(__GNUC__))
|
|
BX_CPU_THIS_PTR eflags.val32 =
|
|
(BX_CPU_THIS_PTR eflags.val32 & ~0x000008d5) | (flags32 & 0x000008d5);
|
|
BX_CPU_THIS_PTR lf_flags_status = 0;
|
|
#else
|
|
SET_FLAGS_OSZAPC_32(op1_32, op2_32, sum_32, BX_INSTR_ADD32);
|
|
#endif
|
|
}
|
|
|
|
void
|
|
BX_CPU_C::ADC_EdId(BxInstruction_t *i)
|
|
{
|
|
Boolean temp_CF;
|
|
|
|
temp_CF = get_CF();
|
|
|
|
/* for 32 bit operand size mode */
|
|
Bit32u op2_32, op1_32, sum_32;
|
|
|
|
op2_32 = i->Id;
|
|
|
|
/* op1_32 is a register or memory reference */
|
|
if (i->mod == 0xc0) {
|
|
op1_32 = BX_READ_32BIT_REG(i->rm);
|
|
}
|
|
else {
|
|
/* pointer, segment address pair */
|
|
read_RMW_virtual_dword(i->seg, i->rm_addr, &op1_32);
|
|
}
|
|
|
|
sum_32 = op1_32 + op2_32 + temp_CF;
|
|
|
|
/* now write sum back to destination */
|
|
if (i->mod == 0xc0) {
|
|
BX_WRITE_32BIT_REG(i->rm, sum_32);
|
|
}
|
|
else {
|
|
Write_RMW_virtual_dword(sum_32);
|
|
}
|
|
|
|
SET_FLAGS_OSZAPC_32_CF(op1_32, op2_32, sum_32, BX_INSTR_ADC32,
|
|
temp_CF);
|
|
}
|
|
|
|
|
|
void
|
|
BX_CPU_C::SUB_EdId(BxInstruction_t *i)
|
|
{
|
|
/* for 32 bit operand size mode */
|
|
Bit32u op2_32, op1_32, diff_32;
|
|
|
|
op2_32 = i->Id;
|
|
|
|
/* op1_32 is a register or memory reference */
|
|
if (i->mod == 0xc0) {
|
|
op1_32 = BX_READ_32BIT_REG(i->rm);
|
|
}
|
|
else {
|
|
/* pointer, segment address pair */
|
|
read_RMW_virtual_dword(i->seg, i->rm_addr, &op1_32);
|
|
}
|
|
|
|
diff_32 = op1_32 - op2_32;
|
|
|
|
/* now write diff back to destination */
|
|
if (i->mod == 0xc0) {
|
|
BX_WRITE_32BIT_REG(i->rm, diff_32);
|
|
}
|
|
else {
|
|
Write_RMW_virtual_dword(diff_32);
|
|
}
|
|
|
|
SET_FLAGS_OSZAPC_32(op1_32, op2_32, diff_32, BX_INSTR_SUB32);
|
|
}
|
|
|
|
void
|
|
BX_CPU_C::CMP_EdId(BxInstruction_t *i)
|
|
{
|
|
/* for 32 bit operand size mode */
|
|
Bit32u op2_32, op1_32, diff_32;
|
|
|
|
op2_32 = i->Id;
|
|
|
|
/* op1_32 is a register or memory reference */
|
|
if (i->mod == 0xc0) {
|
|
op1_32 = BX_READ_32BIT_REG(i->rm);
|
|
}
|
|
else {
|
|
/* pointer, segment address pair */
|
|
read_virtual_dword(i->seg, i->rm_addr, &op1_32);
|
|
}
|
|
|
|
diff_32 = op1_32 - op2_32;
|
|
|
|
SET_FLAGS_OSZAPC_32(op1_32, op2_32, diff_32, BX_INSTR_CMP32);
|
|
}
|
|
|
|
|
|
|
|
|
|
void
|
|
BX_CPU_C::NEG_Ed(BxInstruction_t *i)
|
|
{
|
|
/* for 32 bit operand size mode */
|
|
Bit32u op1_32, diff_32;
|
|
|
|
/* op1_32 is a register or memory reference */
|
|
if (i->mod == 0xc0) {
|
|
op1_32 = BX_READ_32BIT_REG(i->rm);
|
|
}
|
|
else {
|
|
/* pointer, segment address pair */
|
|
read_RMW_virtual_dword(i->seg, i->rm_addr, &op1_32);
|
|
}
|
|
|
|
diff_32 = 0 - op1_32;
|
|
|
|
/* now write diff back to destination */
|
|
if (i->mod == 0xc0) {
|
|
BX_WRITE_32BIT_REG(i->rm, diff_32);
|
|
}
|
|
else {
|
|
Write_RMW_virtual_dword(diff_32);
|
|
}
|
|
|
|
SET_FLAGS_OSZAPC_32(op1_32, 0, diff_32, BX_INSTR_NEG32);
|
|
}
|
|
|
|
|
|
void
|
|
BX_CPU_C::INC_Ed(BxInstruction_t *i)
|
|
{
|
|
Bit32u op1_32;
|
|
|
|
/* op1_32 is a register or memory reference */
|
|
if (i->mod == 0xc0) {
|
|
op1_32 = BX_READ_32BIT_REG(i->rm);
|
|
}
|
|
else {
|
|
/* pointer, segment address pair */
|
|
read_RMW_virtual_dword(i->seg, i->rm_addr, &op1_32);
|
|
}
|
|
|
|
op1_32++;
|
|
|
|
/* now write sum back to destination */
|
|
if (i->mod == 0xc0) {
|
|
BX_WRITE_32BIT_REG(i->rm, op1_32);
|
|
}
|
|
else {
|
|
Write_RMW_virtual_dword(op1_32);
|
|
}
|
|
|
|
SET_FLAGS_OSZAP_32(0, 0, op1_32, BX_INSTR_INC32);
|
|
}
|
|
|
|
|
|
void
|
|
BX_CPU_C::DEC_Ed(BxInstruction_t *i)
|
|
{
|
|
Bit32u op1_32;
|
|
|
|
/* op1_32 is a register or memory reference */
|
|
if (i->mod == 0xc0) {
|
|
op1_32 = BX_READ_32BIT_REG(i->rm);
|
|
}
|
|
else {
|
|
/* pointer, segment address pair */
|
|
read_RMW_virtual_dword(i->seg, i->rm_addr, &op1_32);
|
|
}
|
|
|
|
op1_32--;
|
|
|
|
/* now write sum back to destination */
|
|
if (i->mod == 0xc0) {
|
|
BX_WRITE_32BIT_REG(i->rm, op1_32);
|
|
}
|
|
else {
|
|
Write_RMW_virtual_dword(op1_32);
|
|
}
|
|
|
|
SET_FLAGS_OSZAP_32(0, 0, op1_32, BX_INSTR_DEC32);
|
|
}
|
|
|
|
|
|
void
|
|
BX_CPU_C::CMPXCHG_EdGd(BxInstruction_t *i)
|
|
{
|
|
#if (BX_CPU_LEVEL >= 4) || (BX_CPU_LEVEL_HACKED >= 4)
|
|
|
|
Bit32u op2_32, op1_32, diff_32;
|
|
|
|
/* op1_32 is a register or memory reference */
|
|
if (i->mod == 0xc0) {
|
|
op1_32 = BX_READ_32BIT_REG(i->rm);
|
|
}
|
|
else {
|
|
/* pointer, segment address pair */
|
|
read_RMW_virtual_dword(i->seg, i->rm_addr, &op1_32);
|
|
}
|
|
|
|
diff_32 = EAX - op1_32;
|
|
|
|
SET_FLAGS_OSZAPC_32(EAX, op1_32, diff_32, BX_INSTR_CMP32);
|
|
|
|
if (diff_32 == 0) { // if accumulator == dest
|
|
// ZF = 1
|
|
set_ZF(1);
|
|
// dest <-- src
|
|
op2_32 = BX_READ_32BIT_REG(i->nnn);
|
|
|
|
if (i->mod == 0xc0) {
|
|
BX_WRITE_32BIT_REG(i->rm, op2_32);
|
|
}
|
|
else {
|
|
Write_RMW_virtual_dword(op2_32);
|
|
}
|
|
}
|
|
else {
|
|
// ZF = 0
|
|
set_ZF(0);
|
|
// accumulator <-- dest
|
|
EAX = op1_32;
|
|
}
|
|
#else
|
|
BX_PANIC(("CMPXCHG_EdGd:"));
|
|
#endif
|
|
}
|
|
|
|
void
|
|
BX_CPU_C::CMPXCHG8B(BxInstruction_t *i)
|
|
{
|
|
#if (BX_CPU_LEVEL >= 5) || (BX_CPU_LEVEL_HACKED >= 5)
|
|
|
|
Bit32u op1_64_lo, op1_64_hi, diff;
|
|
|
|
if (i->mod == 0xc0) {
|
|
BX_INFO(("CMPXCHG8B: dest is reg: #UD"));
|
|
UndefinedOpcode(i);
|
|
}
|
|
|
|
/* pointer, segment address pair */
|
|
read_virtual_dword(i->seg, i->rm_addr, &op1_64_lo);
|
|
read_RMW_virtual_dword(i->seg, i->rm_addr + 4, &op1_64_hi);
|
|
|
|
diff = EAX - op1_64_lo;
|
|
diff |= EDX - op1_64_hi;
|
|
|
|
// SET_FLAGS_OSZAPC_32(EAX, op1_32, diff_32, BX_INSTR_CMP32);
|
|
|
|
if (diff == 0) { // if accumulator == dest
|
|
// ZF = 1
|
|
set_ZF(1);
|
|
// dest <-- src
|
|
Write_RMW_virtual_dword(ECX);
|
|
write_virtual_dword(i->seg, i->rm_addr, &EBX);
|
|
}
|
|
else {
|
|
// ZF = 0
|
|
set_ZF(0);
|
|
// accumulator <-- dest
|
|
EAX = op1_64_lo;
|
|
EDX = op1_64_hi;
|
|
}
|
|
|
|
#else
|
|
BX_INFO(("CMPXCHG8B: not implemented yet"));
|
|
UndefinedOpcode(i);
|
|
#endif
|
|
}
|