414 lines
11 KiB
C++
Executable File
414 lines
11 KiB
C++
Executable File
/////////////////////////////////////////////////////////////////////////
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// $Id:
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/////////////////////////////////////////////////////////////////////////
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//
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// Copyright (C) 2001 MandrakeSoft S.A.
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//
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// MandrakeSoft S.A.
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// 43, rue d'Aboukir
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// 75002 Paris - France
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// http://www.linux-mandrake.com/
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// http://www.mandrakesoft.com/
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//
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// This library is free software; you can redistribute it and/or
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// modify it under the terms of the GNU Lesser General Public
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// License as published by the Free Software Foundation; either
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// version 2 of the License, or (at your option) any later version.
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//
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// This library is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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// Lesser General Public License for more details.
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//
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// You should have received a copy of the GNU Lesser General Public
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// License along with this library; if not, write to the Free Software
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// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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//
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/////////////////////////////////////////////////////////////////////////
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#define NEED_CPU_REG_SHORTCUTS 1
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#include "bochs.h"
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#define LOG_THIS BX_CPU_THIS_PTR
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#if BX_SUPPORT_X86_64==0
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// Make life easier for merging code.
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#define RAX EAX
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#define RBX EBX
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#define RCX ECX
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#define RDX EDX
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#endif
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/* Get CPU version information. */
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Bit32u BX_CPU_C::get_cpu_version_information()
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{
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Bit32u family = 0, model = 0, stepping = 0;
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Bit32u extended_model = 0;
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Bit32u extended_family = 0;
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/* ****** */
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/* i486 */
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/* ****** */
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#if BX_CPU_LEVEL == 4
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family = 4;
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#if BX_SUPPORT_FPU
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model = 1; // 486dx
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stepping = 3;
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#else
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model = 2; // 486sx
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stepping = 3;
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#endif
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/* **************** */
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/* i586 (Pentium) */
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/* **************** */
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#elif BX_CPU_LEVEL == 5
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family = 5;
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#if BX_SUPPORT_MMX
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model = 4; // Pentium MMX
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#else
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model = 1; // Pentium 60/66
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#endif
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stepping = 3;
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/* ****** */
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/* i686 */
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/* ****** */
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#elif BX_CPU_LEVEL == 6
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#if BX_SUPPORT_SSE >= 2 // Pentium 4 processor
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/*
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The model, family, and processor type for the first
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processor in the Intel Pentium 4 family is as follows:
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* Model-0000B
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* Family-1111B
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* Processor Type-00B (OEM)
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* Stepping-0B
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*/
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model = 0;
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family = 0xf;
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stepping = 0;
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#if BX_SUPPORT_X86_64
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model = 2; // Hammer returns what?
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#endif
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#else // Pentium Pro/Pentium II/Pentium III processor
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family = 6;
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model = 8;
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stepping = 3;
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#endif
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#else
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BX_PANIC(("CPUID family ID not implemented for CPU LEVEL > 6"));
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#endif
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return (extended_family << 20) |
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(extended_model << 16) |
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(family << 8) |
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(model<<4) | stepping;
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}
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/* Get CPU extended feature flags. */
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Bit32u BX_CPU_C::get_extended_cpuid_features()
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{
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Bit32u features = 0; // start with none
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#if BX_SUPPORT_PNI
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features |= 0x01; // report PNI
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#endif
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return features;
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}
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/* Get CPU feature flags. Returned by CPUID functions 1 and 80000001. */
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Bit32u BX_CPU_C::get_std_cpuid_features()
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{
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Bit32u features = 0; // start with none
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#if BX_SUPPORT_FPU
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features |= 0x01;
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#endif
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#if (BX_CPU_LEVEL >= 5)
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features |= (1<< 8); // Support CMPXCHG8B instruction
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features |= (1<< 4); // implement TSC
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features |= (1<< 5); // support RDMSR/WRMSR
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#if BX_SUPPORT_MMX
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features |= (1<<23); // support MMX
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#endif
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#endif
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#if (BX_CPU_LEVEL >= 6) || (BX_CPU_LEVEL_HACKED >= 6)
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features |= (1<<24); // Implement FSAVE/FXRSTOR instructions.
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#endif
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#if BX_CPU_LEVEL >= 6
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features |= (1<<15); // Implement CMOV instructions.
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#if BX_SUPPORT_APIC
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// if MSR_APICBASE APIC Global Enable bit has been cleared,
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// the CPUID feature flag for the APIC is set to 0.
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if (BX_CPU_THIS_PTR msr.apicbase & 0x800)
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features |= (1<< 9); // APIC on chip
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#endif
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#if BX_SUPPORT_SSE >= 1
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features |= (1<<25); // support SSE
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#endif
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#if BX_SUPPORT_SSE >= 2
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features |= (1<<26); // support SSE2
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#endif
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#endif
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#if BX_SUPPORT_4MEG_PAGES
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features |= (1<< 3); // Support Page-Size Extension (4M pages)
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#endif
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#if BX_SupportGlobalPages
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features |= (1<<13); // Support Global pages.
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#endif
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#if BX_SupportPAE
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features |= (1<< 6); // Support PAE.
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#endif
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#if BX_SUPPORT_SEP
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features |= (1<<11); // SYSENTER/SYSEXIT
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#endif
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return features;
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}
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void BX_CPU_C::CPUID(bxInstruction_c *i)
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{
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#if BX_SUPPORT_X86_64
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unsigned features;
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#endif
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#if BX_CPU_LEVEL >= 4
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switch (EAX) {
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case 0:
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// EAX: highest input value understood by CPUID
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#if BX_CPU_LEVEL <= 5
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RAX = 1; // 486 and Pentium processors
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#else
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RAX = 1; // for Pentium Pro, Pentium II, Pentium 4 processors
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// should be 2, still not implemented
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#endif
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// EBX: vendor ID string
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// EDX: vendor ID string
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// ECX: vendor ID string
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#if BX_SUPPORT_X86_64
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RBX = 0x68747541; // "Auth"
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RDX = 0x69746e65; // "enti"
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RCX = 0x444d4163; // "cAMD"
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#else
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RBX = 0x756e6547; // "Genu"
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RDX = 0x49656e69; // "ineI"
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RCX = 0x6c65746e; // "ntel"
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#endif
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break;
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case 1:
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// EAX: CPU Version Information
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// [3:0] Stepping ID
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// [7:4] Model: starts at 1
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// [11:8] Family: 4=486, 5=Pentium, 6=PPro, ...
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// [13:12] Type: 0=OEM, 1=overdrive, 2=dual cpu, 3=reserved
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// [31:14] Reserved
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// EBX:
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// [7:0] Brand ID
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// [15:8] CFLUSH cache line size (value*8 = cache line size in bytes)
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// [23:16] Number of logical processors in one physical processor
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// [31:24] Local Apic ID
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// ECX: Feature Flags::Extended
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// [0:0] PNI
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// [2:1] Reserved
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// [3:3] MONITOR/MWAIT
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// [4:4] CPL qualified debug store available
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// [6:5] Reserved
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// [7:7] Enchanced Intel Speedstep Technology
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// [8:8] TM2: Thermal Monitor 2
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// [12:9] Reserved
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// [13:13] CMPXCHG16B
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// [31:14] Reserved
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// EDX: Feature Flags
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// [0:0] FPU on chip
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// [1:1] VME: Virtual-8086 Mode enhancements
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// [2:2] DE: Debug Extensions (I/O breakpoints)
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// [3:3] PSE: Page Size Extensions
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// [4:4] TSC: Time Stamp Counter
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// [5:5] MSR: RDMSR and WRMSR support
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// [6:6] PAE: Physical Address Extensions
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// [7:7] MCE: Machine Check Exception
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// [8:8] CXS: CMPXCHG8B instruction
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// [9:9] APIC: APIC on Chip
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// [10:10] Reserved
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// [11:11] SYSENTER/SYSEXIT support
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// [12:12] MTRR: Memory Type Range Reg
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// [13:13] PGE/PTE Global Bit
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// [14:14] MCA: Machine Check Architecture
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// [15:15] CMOV: Cond Mov/Cmp Instructions
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// [16:16] PAT: Page Attribute Table
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// [17:17] PSE: Page-Size Extensions
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// [18:18] Reserved
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// [19:19] CLFLUSH: CLFLUSH Instruction support
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// [22:20] Reserved
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// [23:23] MMX Technology
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// [24] FXSR: FXSAVE/FXRSTOR (also indicates CR4.OSFXSR is available)
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// [25] SSE: SSE Extensions
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// [26] SSE2: SSE2 Extensions
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// [27] Reserved
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// [28] Hyper Threading Technology
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// [29] TM: Thermal Monitor
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// [31:30] Reserved
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RAX = get_cpu_version_information();
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#if BX_SUPPORT_APIC
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RBX = (BX_CPU_THIS_PTR local_apic.get_id() << 24);
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#else
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RBX = 0;
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#endif
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RCX = get_extended_cpuid_features ();
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RDX = get_std_cpuid_features ();
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break;
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#if BX_CPU_LEVEL >= 6 && BX_SUPPORT_SSE >= 2
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#if BX_SUPPORT_X86_64
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// Extended information for AMD Athlon processor
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// x86-64 functions
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case 0x80000000:
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// max function supported.
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RAX = 0x80000008;
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RBX = 0x68747541; // "Auth"
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RDX = 0x69746e65; // "enti"
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RCX = 0x444d4163; // "cAMD"
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break;
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case 0x80000001:
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// long mode supported.
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features = get_std_cpuid_features ();
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RAX = features;
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// Many of the bits in EDX are the same as EAX [*]
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// [*] [0:0] FPU on chip
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// [*] [1:1] VME: Virtual-8086 Mode enhancements
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// [*] [2:2] DE: Debug Extensions (I/O breakpoints)
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// [*] [3:3] PSE: Page Size Extensions
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// [*] [4:4] TSC: Time Stamp Counter
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// [*] [5:5] MSR: RDMSR and WRMSR support
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// [*] [6:6] PAE: Physical Address Extensions
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// [*] [7:7] MCE: Machine Check Exception
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// [*] [8:8] CXS: CMPXCHG8B instruction
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// [*] [9:9] APIC: APIC on Chip
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// [*] [10:10] Reserved
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// [11:11] SYSCALL/SYSRET support
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// [*] [12:12] MTRR: Memory Type Range Reg
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// [*] [13:13] PGE/PTE Global Bit
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// [*] [14:14] MCA: Machine Check Architecture
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// [*] [15:15] CMOV: Cond Mov/Cmp Instructions
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// [*] [16:16] PAT: Page Attribute Table
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// [*] [17:17] PSE: Page-Size Extensions
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// [18:19] Reserved
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// [20:20] No-Execute page protection
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// [21:21] Reserved
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// [22:22] AMD MMX Extensions
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// [25:25] Fast FXSAVE/FXRSTOR mode support
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// [25:28] Reserved
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// [29:29] Long Mode
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// [30:30] AMD 3DNow! Extensions
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// [31:31] AMD 3DNow! Instructions
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features = features & 0x00003F3FF;
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RDX = features | (1 << 29) | (1 << 25) | (1 << 22) | (1 << 20) | (1 << 11);
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RBX = 0;
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RCX = 0;
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break;
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// Processor Brand String, use the value given
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// in AMD manuals.
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case 0x80000002:
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RAX = 0x20444D41; // "AMD "
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RBX = 0x6C687441; // "Athl"
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RCX = 0x74286E6F; // "on(t"
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RDX = 0x7020296D; // "m) p"
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break;
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case 0x80000003:
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RAX = 0x65636F72; // "roce"
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RBX = 0x726F7373; // "ssor"
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RCX = 0x00000000;
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RDX = 0x00000000;
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break;
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case 0x80000004:
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RAX = 0x00000000;
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RBX = 0x00000000;
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RCX = 0x00000000;
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RDX = 0x00000000;
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break;
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case 0x80000008:
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// virtual & phys address size in low 2 bytes.
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RAX = 0x00003020; // 48-bit virtual address and 32 bit physical
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RBX = 0;
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RCX = 0;
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RDX = 0; // Reserved, undefined
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break;
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#else
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// Extended information for Intel P4 processor
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case 0x80000000:
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// max function supported.
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RAX = 0x80000004;
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RBX = 0;
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RCX = 0;
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RDX = 0;
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break;
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case 0x80000001: // Reserved
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RAX = 0;
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RBX = 0;
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RCX = 0;
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RDX = 0;
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break;
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// Processor Brand String, use the value that is returned
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// by the first processor in the Pentium 4 family
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// (according to Intel manual)
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case 0x80000002:
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RAX = 0x20202020; // " "
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RBX = 0x20202020; // " "
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RCX = 0x20202020; // " "
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RDX = 0x6E492020; // " In"
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break;
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case 0x80000003:
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RAX = 0x286C6574; // "tel("
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RBX = 0x50202952; // "R) P"
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RCX = 0x69746E65; // "enti"
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RDX = 0x52286D75; // "um(R"
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break;
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case 0x80000004:
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RAX = 0x20342029; // ") 4 "
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RBX = 0x20555043; // "CPU "
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RCX = 0x20202020; // " "
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RDX = 0x00202020; // " "
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break;
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#endif
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#endif
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default:
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RAX = 0;
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RBX = 0;
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RCX = 0;
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RDX = 0; // Reserved, undefined
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break;
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}
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#else
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BX_INFO(("CPUID: not available on < late 486"));
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UndefinedOpcode(i);
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#endif
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}
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