447 lines
11 KiB
C++
447 lines
11 KiB
C++
/////////////////////////////////////////////////////////////////////////
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// $Id: ctrl_xfer32.cc,v 1.41 2005-05-20 20:06:50 sshwarts Exp $
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/////////////////////////////////////////////////////////////////////////
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//
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// Copyright (C) 2001 MandrakeSoft S.A.
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//
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// MandrakeSoft S.A.
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// 43, rue d'Aboukir
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// 75002 Paris - France
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// http://www.linux-mandrake.com/
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// http://www.mandrakesoft.com/
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//
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// This library is free software; you can redistribute it and/or
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// modify it under the terms of the GNU Lesser General Public
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// License as published by the Free Software Foundation; either
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// version 2 of the License, or (at your option) any later version.
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//
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// This library is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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// Lesser General Public License for more details.
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//
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// You should have received a copy of the GNU Lesser General Public
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// License along with this library; if not, write to the Free Software
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// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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#define NEED_CPU_REG_SHORTCUTS 1
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#include "bochs.h"
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#define LOG_THIS BX_CPU_THIS_PTR
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#if BX_CPU_LEVEL >= 3
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void BX_CPU_C::RETnear32_Iw(bxInstruction_c *i)
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{
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Bit32u return_EIP;
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#if BX_DEBUGGER
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BX_CPU_THIS_PTR show_flag |= Flag_ret;
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#endif
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Bit16u imm16 = i->Iw();
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pop_32(&return_EIP);
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branch_near32(return_EIP); // includes revalidate_prefetch_q()
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if (BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].cache.u.segment.d_b)
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ESP += imm16;
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else
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SP += imm16;
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BX_INSTR_UCNEAR_BRANCH(BX_CPU_ID, BX_INSTR_IS_RET, EIP);
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}
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void BX_CPU_C::RETnear32(bxInstruction_c *i)
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{
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Bit32u return_EIP;
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#if BX_DEBUGGER
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BX_CPU_THIS_PTR show_flag |= Flag_ret;
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#endif
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pop_32(&return_EIP);
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branch_near32(return_EIP); // includes revalidate_prefetch_q()
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BX_INSTR_UCNEAR_BRANCH(BX_CPU_ID, BX_INSTR_IS_RET, EIP);
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}
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void BX_CPU_C::RETfar32_Iw(bxInstruction_c *i)
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{
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Bit32u eip, ecs_raw;
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invalidate_prefetch_q();
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#if BX_DEBUGGER
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BX_CPU_THIS_PTR show_flag |= Flag_ret;
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#endif
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Bit16u imm16 = i->Iw();
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if (protected_mode()) {
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BX_CPU_THIS_PTR return_protected(i, imm16);
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goto done;
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}
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pop_32(&eip);
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pop_32(&ecs_raw);
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EIP = eip;
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load_seg_reg(&BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS], (Bit16u) ecs_raw);
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if (BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].cache.u.segment.d_b)
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ESP += imm16;
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else
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SP += imm16;
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done:
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BX_INSTR_FAR_BRANCH(BX_CPU_ID, BX_INSTR_IS_RET,
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BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].selector.value, EIP);
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}
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void BX_CPU_C::RETfar32(bxInstruction_c *i)
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{
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Bit32u eip, ecs_raw;
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invalidate_prefetch_q();
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#if BX_DEBUGGER
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BX_CPU_THIS_PTR show_flag |= Flag_ret;
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#endif
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if ( protected_mode() ) {
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BX_CPU_THIS_PTR return_protected(i, 0);
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goto done;
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}
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pop_32(&eip);
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pop_32(&ecs_raw); /* 32bit pop, MSW discarded */
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EIP = eip;
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load_seg_reg(&BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS], (Bit16u) ecs_raw);
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done:
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BX_INSTR_FAR_BRANCH(BX_CPU_ID, BX_INSTR_IS_RET,
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BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].selector.value, EIP);
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}
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void BX_CPU_C::CALL_Ad(bxInstruction_c *i)
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{
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BailBigRSP("CALL_Ad");
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#if BX_DEBUGGER
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BX_CPU_THIS_PTR show_flag |= Flag_call;
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#endif
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Bit32u new_EIP = EIP + i->Id();
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if ( new_EIP > BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.u.segment.limit_scaled ) {
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BX_ERROR(("CALL_Ad: offset outside of CS limits"));
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exception(BX_GP_EXCEPTION, 0, 0);
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}
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/* push 32 bit EA of next instruction */
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push_32(EIP);
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EIP = new_EIP;
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BX_INSTR_UCNEAR_BRANCH(BX_CPU_ID, BX_INSTR_IS_CALL, EIP);
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}
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void BX_CPU_C::CALL32_Ap(bxInstruction_c *i)
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{
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Bit16u cs_raw;
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Bit32u disp32;
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invalidate_prefetch_q();
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#if BX_DEBUGGER
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BX_CPU_THIS_PTR show_flag |= Flag_call;
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#endif
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disp32 = i->Id();
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cs_raw = i->Iw2();
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if (protected_mode()) {
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BX_CPU_THIS_PTR call_protected(i, cs_raw, disp32);
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goto done;
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}
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push_32(BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].selector.value);
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push_32(EIP);
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EIP = disp32;
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load_seg_reg(&BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS], cs_raw);
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done:
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BX_INSTR_FAR_BRANCH(BX_CPU_ID, BX_INSTR_IS_CALL,
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BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].selector.value, EIP);
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}
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void BX_CPU_C::CALL_Ed(bxInstruction_c *i)
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{
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Bit32u op1_32;
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#if BX_DEBUGGER
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BX_CPU_THIS_PTR show_flag |= Flag_call;
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#endif
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if (i->modC0()) {
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op1_32 = BX_READ_32BIT_REG(i->rm());
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}
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else {
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read_virtual_dword(i->seg(), RMAddr(i), &op1_32);
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}
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if (op1_32 > BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.u.segment.limit_scaled)
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{
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BX_ERROR(("CALL_Ed: EIP out of CS limits!"));
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exception(BX_GP_EXCEPTION, 0, 0);
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}
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push_32(EIP);
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EIP = op1_32;
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BX_INSTR_UCNEAR_BRANCH(BX_CPU_ID, BX_INSTR_IS_CALL, EIP);
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}
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void BX_CPU_C::CALL32_Ep(bxInstruction_c *i)
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{
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Bit16u cs_raw;
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Bit32u op1_32;
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invalidate_prefetch_q();
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#if BX_DEBUGGER
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BX_CPU_THIS_PTR show_flag |= Flag_call;
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#endif
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/* op1_32 is a register or memory reference */
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if (i->modC0()) {
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BX_INFO(("CALL_Ep: op1 is a register"));
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exception(BX_UD_EXCEPTION, 0, 0);
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}
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/* pointer, segment address pair */
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read_virtual_dword(i->seg(), RMAddr(i), &op1_32);
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read_virtual_word(i->seg(), RMAddr(i)+4, &cs_raw);
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if ( protected_mode() ) {
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BX_CPU_THIS_PTR call_protected(i, cs_raw, op1_32);
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goto done;
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}
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push_32(BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].selector.value);
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push_32(EIP);
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EIP = op1_32;
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load_seg_reg(&BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS], cs_raw);
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done:
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BX_INSTR_FAR_BRANCH(BX_CPU_ID, BX_INSTR_IS_CALL,
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BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].selector.value, EIP);
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}
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void BX_CPU_C::JMP_Jd(bxInstruction_c *i)
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{
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Bit32u new_EIP = EIP + (Bit32s) i->Id();
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branch_near32(new_EIP); // includes revalidate_prefetch_q()
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BX_INSTR_UCNEAR_BRANCH(BX_CPU_ID, BX_INSTR_IS_JMP, new_EIP);
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}
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void BX_CPU_C::JCC_Jd(bxInstruction_c *i)
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{
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bx_bool condition;
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switch (i->b1() & 0x0f) {
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case 0x00: /* JO */ condition = get_OF(); break;
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case 0x01: /* JNO */ condition = !get_OF(); break;
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case 0x02: /* JB */ condition = get_CF(); break;
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case 0x03: /* JNB */ condition = !get_CF(); break;
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case 0x04: /* JZ */ condition = get_ZF(); break;
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case 0x05: /* JNZ */ condition = !get_ZF(); break;
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case 0x06: /* JBE */ condition = get_CF() || get_ZF(); break;
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case 0x07: /* JNBE */ condition = !get_CF() && !get_ZF(); break;
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case 0x08: /* JS */ condition = get_SF(); break;
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case 0x09: /* JNS */ condition = !get_SF(); break;
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case 0x0A: /* JP */ condition = get_PF(); break;
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case 0x0B: /* JNP */ condition = !get_PF(); break;
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case 0x0C: /* JL */ condition = getB_SF() != getB_OF(); break;
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case 0x0D: /* JNL */ condition = getB_SF() == getB_OF(); break;
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case 0x0E: /* JLE */ condition = get_ZF() || (getB_SF() != getB_OF());
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break;
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case 0x0F: /* JNLE */ condition = (getB_SF() == getB_OF()) &&
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!get_ZF();
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break;
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default:
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condition = 0; // For compiler...all targets should set condition.
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break;
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}
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if (condition) {
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Bit32u new_EIP = EIP + (Bit32s) i->Id();
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branch_near32(new_EIP); // includes revalidate_prefetch_q()
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BX_INSTR_CNEAR_BRANCH_TAKEN(BX_CPU_ID, new_EIP);
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}
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#if BX_INSTRUMENTATION
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else {
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BX_INSTR_CNEAR_BRANCH_NOT_TAKEN(BX_CPU_ID);
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}
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#endif
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}
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void BX_CPU_C::JZ_Jd(bxInstruction_c *i)
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{
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if (get_ZF()) {
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Bit32u new_EIP = EIP + (Bit32s) i->Id();
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branch_near32(new_EIP); // includes revalidate_prefetch_q()
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BX_INSTR_CNEAR_BRANCH_TAKEN(BX_CPU_ID, new_EIP);
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}
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#if BX_INSTRUMENTATION
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else {
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BX_INSTR_CNEAR_BRANCH_NOT_TAKEN(BX_CPU_ID);
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}
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#endif
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}
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void BX_CPU_C::JNZ_Jd(bxInstruction_c *i)
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{
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if (!get_ZF()) {
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Bit32u new_EIP = EIP + (Bit32s) i->Id();
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branch_near32(new_EIP); // includes revalidate_prefetch_q()
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BX_INSTR_CNEAR_BRANCH_TAKEN(BX_CPU_ID, new_EIP);
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}
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#if BX_INSTRUMENTATION
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else {
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BX_INSTR_CNEAR_BRANCH_NOT_TAKEN(BX_CPU_ID);
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}
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#endif
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}
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void BX_CPU_C::JMP_Ap(bxInstruction_c *i)
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{
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Bit32u disp32;
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Bit16u cs_raw;
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invalidate_prefetch_q();
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if (i->os32L()) {
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disp32 = i->Id();
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}
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else {
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disp32 = i->Iw();
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}
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cs_raw = i->Iw2();
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if (protected_mode()) {
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BX_CPU_THIS_PTR jump_protected(i, cs_raw, disp32);
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goto done;
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}
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load_seg_reg(&BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS], cs_raw);
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EIP = disp32;
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done:
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BX_INSTR_FAR_BRANCH(BX_CPU_ID, BX_INSTR_IS_JMP,
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BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].selector.value, EIP);
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}
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void BX_CPU_C::JMP_Ed(bxInstruction_c *i)
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{
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Bit32u new_EIP;
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/* op1_32 is a register or memory reference */
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if (i->modC0()) {
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new_EIP = BX_READ_32BIT_REG(i->rm());
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}
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else {
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/* pointer, segment address pair */
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read_virtual_dword(i->seg(), RMAddr(i), &new_EIP);
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}
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branch_near32(new_EIP); // includes revalidate_prefetch_q()
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BX_INSTR_UCNEAR_BRANCH(BX_CPU_ID, BX_INSTR_IS_JMP, new_EIP);
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}
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/* Far indirect jump */
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void BX_CPU_C::JMP32_Ep(bxInstruction_c *i)
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{
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Bit16u cs_raw;
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Bit32u op1_32;
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invalidate_prefetch_q();
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/* op1_32 is a register or memory reference */
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if (i->modC0()) {
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/* far indirect must specify a memory address */
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BX_INFO(("JMP_Ep(): op1 is a register"));
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exception(BX_UD_EXCEPTION, 0, 0);
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}
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/* pointer, segment address pair */
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read_virtual_dword(i->seg(), RMAddr(i), &op1_32);
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read_virtual_word(i->seg(), RMAddr(i)+4, &cs_raw);
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if ( protected_mode() ) {
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BX_CPU_THIS_PTR jump_protected(i, cs_raw, op1_32);
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goto done;
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}
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EIP = op1_32;
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load_seg_reg(&BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS], cs_raw);
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done:
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BX_INSTR_FAR_BRANCH(BX_CPU_ID, BX_INSTR_IS_JMP,
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BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].selector.value, EIP);
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}
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void BX_CPU_C::IRET32(bxInstruction_c *i)
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{
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invalidate_prefetch_q();
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#if BX_DEBUGGER
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BX_CPU_THIS_PTR show_flag |= Flag_iret;
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BX_CPU_THIS_PTR show_eip = EIP;
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#endif
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if (v8086_mode()) {
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// IOPL check in stack_return_from_v86()
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stack_return_from_v86(i);
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goto done;
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}
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if (protected_mode()) {
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iret_protected(i);
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goto done;
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}
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Bit32u eip, ecs, eflags;
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if (! can_pop(12)) {
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BX_PANIC(("IRETD: to 12 bytes of stack not within stack limits"));
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exception(BX_SS_EXCEPTION, 0, 0);
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}
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access_linear(BX_CPU_THIS_PTR get_segment_base(BX_SEG_REG_SS) + ESP,
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4, CPL == 3, BX_READ, &eip);
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// still need to be validated !
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if (eip > 0xffff) {
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BX_PANIC(("IRETD: instruction pointer not within code segment limits"));
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exception(BX_GP_EXCEPTION, 0, 0);
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}
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pop_32(&eip);
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pop_32(&ecs);
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pop_32(&eflags);
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ecs &= 0xffff;
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eflags = (eflags & 0x257fd5) | (read_eflags() & 0x1a0000);
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load_seg_reg(&BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS], (Bit16u)ecs);
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EIP = eip;
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writeEFlags(eflags, 0xffffffff);
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done:
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BX_INSTR_FAR_BRANCH(BX_CPU_ID, BX_INSTR_IS_IRET,
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BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].selector.value, EIP);
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}
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#endif
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