838 lines
29 KiB
C++
838 lines
29 KiB
C++
/////////////////////////////////////////////////////////////////////////
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// $Id$
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/////////////////////////////////////////////////////////////////////////
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//
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// Copyright (C) 2002-2009 The Bochs Project
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//
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// This library is free software; you can redistribute it and/or
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// modify it under the terms of the GNU Lesser General Public
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// License as published by the Free Software Foundation; either
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// version 2 of the License, or (at your option) any later version.
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//
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// This library is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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// Lesser General Public License for more details.
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//
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// You should have received a copy of the GNU Lesser General Public
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// License along with this library; if not, write to the Free Software
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// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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//
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/////////////////////////////////////////////////////////////////////////
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// Define BX_PLUGGABLE in files that can be compiled into plugins. For
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// platforms that require a special tag on exported symbols, BX_PLUGGABLE
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// is used to know when we are exporting symbols and when we are importing.
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#define BX_PLUGGABLE
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#include "iodev.h"
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#include "dma.h"
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#define LOG_THIS theDmaDevice->
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#define DMA_MODE_DEMAND 0
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#define DMA_MODE_SINGLE 1
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#define DMA_MODE_BLOCK 2
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#define DMA_MODE_CASCADE 3
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bx_dma_c *theDmaDevice = NULL;
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int libdma_LTX_plugin_init(plugin_t *plugin, plugintype_t type, int argc, char *argv[])
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{
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if (type == PLUGTYPE_CORE) {
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theDmaDevice = new bx_dma_c ();
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bx_devices.pluginDmaDevice = theDmaDevice;
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BX_REGISTER_DEVICE_DEVMODEL(plugin, type, theDmaDevice, BX_PLUGIN_DMA);
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return 0; // Success
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} else {
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return -1;
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}
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}
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void libdma_LTX_plugin_fini(void)
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{
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delete theDmaDevice;
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}
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bx_dma_c::bx_dma_c()
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{
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put("DMA");
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memset(&s, 0, sizeof(s));
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}
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bx_dma_c::~bx_dma_c()
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{
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SIM->get_bochs_root()->remove("dma");
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BX_DEBUG(("Exit"));
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}
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unsigned bx_dma_c::registerDMA8Channel(unsigned channel,
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Bit16u (* dmaRead)(Bit8u *data_byte, Bit16u maxlen),
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Bit16u (* dmaWrite)(Bit8u *data_byte, Bit16u maxlen),
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const char *name)
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{
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if (channel > 3) {
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BX_PANIC(("registerDMA8Channel: invalid channel number(%u).", channel));
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return 0; // Fail
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}
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if (BX_DMA_THIS s[0].chan[channel].used) {
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BX_PANIC(("registerDMA8Channel: channel(%u) already in use.", channel));
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return 0; // Fail
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}
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BX_INFO(("channel %u used by %s", channel, name));
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BX_DMA_THIS h[channel].dmaRead8 = dmaRead;
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BX_DMA_THIS h[channel].dmaWrite8 = dmaWrite;
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BX_DMA_THIS s[0].chan[channel].used = 1;
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return 1; // OK
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}
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unsigned bx_dma_c::registerDMA16Channel(unsigned channel,
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Bit16u (* dmaRead)(Bit16u *data_word, Bit16u maxlen),
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Bit16u (* dmaWrite)(Bit16u *data_word, Bit16u maxlen),
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const char *name)
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{
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if ((channel < 4) || (channel > 7)) {
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BX_PANIC(("registerDMA16Channel: invalid channel number(%u).", channel));
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return 0; // Fail
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}
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if (BX_DMA_THIS s[1].chan[channel & 0x03].used) {
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BX_PANIC(("registerDMA16Channel: channel(%u) already in use.", channel));
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return 0; // Fail
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}
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BX_INFO(("channel %u used by %s", channel, name));
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channel &= 0x03;
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BX_DMA_THIS h[channel].dmaRead16 = dmaRead;
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BX_DMA_THIS h[channel].dmaWrite16 = dmaWrite;
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BX_DMA_THIS s[1].chan[channel].used = 1;
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return 1; // OK
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}
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unsigned bx_dma_c::unregisterDMAChannel(unsigned channel)
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{
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bx_bool ma_sl = (channel > 3);
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BX_DMA_THIS s[ma_sl].chan[channel & 0x03].used = 0;
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BX_INFO(("channel %u no longer used", channel));
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return 1;
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}
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unsigned bx_dma_c::get_TC(void)
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{
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return BX_DMA_THIS TC;
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}
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void bx_dma_c::init(void)
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{
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unsigned c, i, j;
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BX_DEBUG(("Init $Id$"));
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/* 8237 DMA controller */
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for (i=0; i < 2; i++) {
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for (j=0; j < 4; j++) {
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BX_DMA_THIS s[i].DRQ[j] = 0;
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BX_DMA_THIS s[i].DACK[j] = 0;
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}
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}
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BX_DMA_THIS HLDA = 0;
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BX_DMA_THIS TC = 0;
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// 0000..000F
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for (i=0x0000; i<=0x000F; i++) {
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DEV_register_ioread_handler(this, read_handler, i, "DMA controller", 1);
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DEV_register_iowrite_handler(this, write_handler, i, "DMA controller", 3);
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}
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// 00080..008F
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for (i=0x0080; i<=0x008F; i++) {
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DEV_register_ioread_handler(this, read_handler, i, "DMA controller", 1);
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DEV_register_iowrite_handler(this, write_handler, i, "DMA controller", 3);
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}
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// 000C0..00DE
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for (i=0x00C0; i<=0x00DE; i+=2) {
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DEV_register_ioread_handler(this, read_handler, i, "DMA controller", 1);
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DEV_register_iowrite_handler(this, write_handler, i, "DMA controller", 3);
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}
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for (i=0; i<2; i++) {
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for (c=0; c<4; c++) {
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BX_DMA_THIS s[i].chan[c].mode.mode_type = 0; // demand mode
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BX_DMA_THIS s[i].chan[c].mode.address_decrement = 0; // address increment
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BX_DMA_THIS s[i].chan[c].mode.autoinit_enable = 0; // autoinit disable
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BX_DMA_THIS s[i].chan[c].mode.transfer_type = 0; // verify
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BX_DMA_THIS s[i].chan[c].base_address = 0;
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BX_DMA_THIS s[i].chan[c].current_address = 0;
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BX_DMA_THIS s[i].chan[c].base_count = 0;
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BX_DMA_THIS s[i].chan[c].current_count = 0;
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BX_DMA_THIS s[i].chan[c].page_reg = 0;
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BX_DMA_THIS s[i].chan[c].used = 0;
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}
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}
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memset(&BX_DMA_THIS ext_page_reg[0], 0, 16);
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BX_DMA_THIS s[1].chan[0].used = 1; // cascade channel in use
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BX_INFO(("channel 4 used by cascade"));
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#if BX_DEBUGGER
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// register device for the 'info device' command (calls debug_dump())
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bx_dbg_register_debug_info("dma", this);
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#endif
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}
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void bx_dma_c::reset(unsigned type)
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{
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reset_controller(0);
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reset_controller(1);
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}
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void bx_dma_c::reset_controller(unsigned num)
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{
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BX_DMA_THIS s[num].mask[0] = 1;
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BX_DMA_THIS s[num].mask[1] = 1;
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BX_DMA_THIS s[num].mask[2] = 1;
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BX_DMA_THIS s[num].mask[3] = 1;
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BX_DMA_THIS s[num].ctrl_disabled = 0;
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BX_DMA_THIS s[num].command_reg = 0;
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BX_DMA_THIS s[num].status_reg = 0;
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BX_DMA_THIS s[num].flip_flop = 0;
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}
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void bx_dma_c::register_state(void)
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{
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unsigned i, c;
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char name[6];
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bx_list_c *list = new bx_list_c(SIM->get_bochs_root(), "dma", "DMA State");
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for (i=0; i<2; i++) {
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sprintf(name, "%d", i);
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bx_list_c *ctrl = new bx_list_c(list, name);
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BXRS_PARAM_BOOL(ctrl, flip_flop, BX_DMA_THIS s[i].flip_flop);
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BXRS_HEX_PARAM_FIELD(ctrl, status_reg, BX_DMA_THIS s[i].status_reg);
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BXRS_HEX_PARAM_FIELD(ctrl, command_reg, BX_DMA_THIS s[i].command_reg);
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BXRS_PARAM_BOOL(ctrl, ctrl_disabled, BX_DMA_THIS s[i].ctrl_disabled);
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for (c=0; c<4; c++) {
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sprintf(name, "%d", c);
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bx_list_c *chan = new bx_list_c(ctrl, name);
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BXRS_PARAM_BOOL(chan, DRQ, BX_DMA_THIS s[i].DRQ[c]);
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BXRS_PARAM_BOOL(chan, DACK, BX_DMA_THIS s[i].DACK[c]);
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BXRS_PARAM_BOOL(chan, mask, BX_DMA_THIS s[i].mask[c]);
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BXRS_DEC_PARAM_FIELD(chan, mode_type, BX_DMA_THIS s[i].chan[c].mode.mode_type);
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BXRS_PARAM_BOOL(chan, address_decrement, BX_DMA_THIS s[i].chan[c].mode.address_decrement);
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BXRS_PARAM_BOOL(chan, autoinit_enable, BX_DMA_THIS s[i].chan[c].mode.autoinit_enable);
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BXRS_DEC_PARAM_FIELD(chan, transfer_type, BX_DMA_THIS s[i].chan[c].mode.transfer_type);
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BXRS_HEX_PARAM_FIELD(chan, base_address, BX_DMA_THIS s[i].chan[c].base_address);
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BXRS_HEX_PARAM_FIELD(chan, current_address, BX_DMA_THIS s[i].chan[c].current_address);
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BXRS_HEX_PARAM_FIELD(chan, base_count, BX_DMA_THIS s[i].chan[c].base_count);
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BXRS_HEX_PARAM_FIELD(chan, current_count, BX_DMA_THIS s[i].chan[c].current_count);
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BXRS_HEX_PARAM_FIELD(chan, page_reg, BX_DMA_THIS s[i].chan[c].page_reg);
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}
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}
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bx_list_c *extpg = new bx_list_c(list, "ext_page");
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for (i=0; i<16; i++) {
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sprintf(name, "0x%02x", 0x80+i);
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new bx_shadow_num_c(extpg, name, &BX_DMA_THIS ext_page_reg[i], BASE_HEX);
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}
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}
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// index to find channel from register number (only [0],[1],[2],[6] used)
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Bit8u channelindex[7] = {2, 3, 1, 0, 0, 0, 0};
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// static IO port read callback handler
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// redirects to non-static class handler to avoid virtual functions
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Bit32u bx_dma_c::read_handler(void *this_ptr, Bit32u address, unsigned io_len)
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{
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#if !BX_USE_DMA_SMF
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bx_dma_c *class_ptr = (bx_dma_c *) this_ptr;
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return class_ptr->read(address, io_len);
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}
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/* 8237 DMA controller */
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Bit32u BX_CPP_AttrRegparmN(2)
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bx_dma_c::read(Bit32u address, unsigned io_len)
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{
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#else
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UNUSED(this_ptr);
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#endif // !BX_USE_DMA_SMF
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Bit8u retval;
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Bit8u channel;
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BX_DEBUG(("read addr=%04x", (unsigned) address));
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#if BX_DMA_FLOPPY_IO < 1
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/* if we're not supporting DMA/floppy IO just return a bogus value */
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return(0xff);
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#endif
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bx_bool ma_sl = (address >= 0xc0);
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switch (address) {
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case 0x00: /* DMA-1 current address, channel 0 */
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case 0x02: /* DMA-1 current address, channel 1 */
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case 0x04: /* DMA-1 current address, channel 2 */
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case 0x06: /* DMA-1 current address, channel 3 */
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case 0xc0: /* DMA-2 current address, channel 0 */
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case 0xc4: /* DMA-2 current address, channel 1 */
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case 0xc8: /* DMA-2 current address, channel 2 */
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case 0xcc: /* DMA-2 current address, channel 3 */
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channel = (address >> (1 + ma_sl)) & 0x03;
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if (BX_DMA_THIS s[ma_sl].flip_flop==0) {
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BX_DMA_THIS s[ma_sl].flip_flop = !BX_DMA_THIS s[ma_sl].flip_flop;
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return (BX_DMA_THIS s[ma_sl].chan[channel].current_address & 0xff);
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} else {
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BX_DMA_THIS s[ma_sl].flip_flop = !BX_DMA_THIS s[ma_sl].flip_flop;
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return (BX_DMA_THIS s[ma_sl].chan[channel].current_address >> 8);
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}
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case 0x01: /* DMA-1 current count, channel 0 */
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case 0x03: /* DMA-1 current count, channel 1 */
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case 0x05: /* DMA-1 current count, channel 2 */
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case 0x07: /* DMA-1 current count, channel 3 */
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case 0xc2: /* DMA-2 current count, channel 0 */
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case 0xc6: /* DMA-2 current count, channel 1 */
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case 0xca: /* DMA-2 current count, channel 2 */
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case 0xce: /* DMA-2 current count, channel 3 */
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channel = (address >> (1 + ma_sl)) & 0x03;
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if (BX_DMA_THIS s[ma_sl].flip_flop==0) {
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BX_DMA_THIS s[ma_sl].flip_flop = !BX_DMA_THIS s[ma_sl].flip_flop;
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return (BX_DMA_THIS s[ma_sl].chan[channel].current_count & 0xff);
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} else {
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BX_DMA_THIS s[ma_sl].flip_flop = !BX_DMA_THIS s[ma_sl].flip_flop;
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return (BX_DMA_THIS s[ma_sl].chan[channel].current_count >> 8);
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}
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case 0x08: // DMA-1 Status Register
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case 0xd0: // DMA-2 Status Register
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// bit 7: 1 = channel 3 request
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// bit 6: 1 = channel 2 request
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// bit 5: 1 = channel 1 request
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// bit 4: 1 = channel 0 request
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// bit 3: 1 = channel 3 has reached terminal count
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// bit 2: 1 = channel 2 has reached terminal count
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// bit 1: 1 = channel 1 has reached terminal count
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// bit 0: 1 = channel 0 has reached terminal count
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// reading this register clears lower 4 bits (hold flags)
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retval = BX_DMA_THIS s[ma_sl].status_reg;
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BX_DMA_THIS s[ma_sl].status_reg &= 0xf0;
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return retval;
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case 0x0d: // DMA-1: temporary register
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case 0xda: // DMA-2: temporary register
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// only used for memory-to-memory transfers
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// write to 0x0d / 0xda clears temporary register
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BX_ERROR(("DMA-%d: read of temporary register always returns 0", ma_sl+1));
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return 0;
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case 0x0081: // DMA-1 page register, channel 2
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case 0x0082: // DMA-1 page register, channel 3
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case 0x0083: // DMA-1 page register, channel 1
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case 0x0087: // DMA-1 page register, channel 0
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channel = channelindex[address - 0x81];
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return BX_DMA_THIS s[0].chan[channel].page_reg;
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case 0x0089: // DMA-2 page register, channel 2
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case 0x008a: // DMA-2 page register, channel 3
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case 0x008b: // DMA-2 page register, channel 1
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case 0x008f: // DMA-2 page register, channel 0
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channel = channelindex[address - 0x89];
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return BX_DMA_THIS s[1].chan[channel].page_reg;
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case 0x0080:
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case 0x0084:
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case 0x0085:
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case 0x0086:
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case 0x0088:
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case 0x008c:
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case 0x008d:
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case 0x008e:
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BX_DEBUG(("read: extra page register 0x%04x (unused)", (unsigned) address));
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return BX_DMA_THIS ext_page_reg[address & 0x0f];
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case 0x0f: // DMA-1: undocumented: read all mask bits
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case 0xde: // DMA-2: undocumented: read all mask bits
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retval = BX_DMA_THIS s[ma_sl].mask[0] |
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(BX_DMA_THIS s[ma_sl].mask[1] << 1) |
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(BX_DMA_THIS s[ma_sl].mask[2] << 2) |
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(BX_DMA_THIS s[ma_sl].mask[3] << 3);
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return (0xf0 | retval);
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default:
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BX_ERROR(("read: unsupported address=%04x", (unsigned) address));
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return 0;
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}
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}
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// static IO port write callback handler
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// redirects to non-static class handler to avoid virtual functions
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void bx_dma_c::write_handler(void *this_ptr, Bit32u address, Bit32u value, unsigned io_len)
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{
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#if !BX_USE_DMA_SMF
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bx_dma_c *class_ptr = (bx_dma_c *) this_ptr;
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class_ptr->write(address, value, io_len);
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}
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/* 8237 DMA controller */
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void BX_CPP_AttrRegparmN(3)
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bx_dma_c::write(Bit32u address, Bit32u value, unsigned io_len)
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{
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#else
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UNUSED(this_ptr);
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#endif // !BX_USE_DMA_SMF
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Bit8u set_mask_bit;
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Bit8u channel;
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if (io_len > 1) {
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if ((io_len == 2) && (address == 0x0b)) {
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#if BX_USE_DMA_SMF
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BX_DMA_THIS write_handler(NULL, address, value & 0xff, 1);
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BX_DMA_THIS write_handler(NULL, address+1, value >> 8, 1);
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#else
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BX_DMA_THIS write(address, value & 0xff, 1);
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BX_DMA_THIS write(address+1, value >> 8, 1);
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#endif
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return;
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}
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BX_ERROR(("io write to address %08x, len=%u",
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(unsigned) address, (unsigned) io_len));
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return;
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}
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BX_DEBUG(("write: address=%04x value=%02x",
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(unsigned) address, (unsigned) value));
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#if BX_DMA_FLOPPY_IO < 1
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/* if we're not supporting DMA/floppy IO just return */
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return;
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#endif
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bx_bool ma_sl = (address >= 0xc0);
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switch (address) {
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case 0x00:
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case 0x02:
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case 0x04:
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case 0x06:
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case 0xc0:
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case 0xc4:
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case 0xc8:
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case 0xcc:
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channel = (address >> (1 + ma_sl)) & 0x03;
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BX_DEBUG((" DMA-%d base and current address, channel %d", ma_sl+1, channel));
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if (BX_DMA_THIS s[ma_sl].flip_flop==0) { /* 1st byte */
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BX_DMA_THIS s[ma_sl].chan[channel].base_address = value;
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BX_DMA_THIS s[ma_sl].chan[channel].current_address = value;
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} else { /* 2nd byte */
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BX_DMA_THIS s[ma_sl].chan[channel].base_address |= (value << 8);
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BX_DMA_THIS s[ma_sl].chan[channel].current_address |= (value << 8);
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BX_DEBUG((" base = %04x", BX_DMA_THIS s[ma_sl].chan[channel].base_address));
|
|
BX_DEBUG((" curr = %04x", BX_DMA_THIS s[ma_sl].chan[channel].current_address));
|
|
}
|
|
BX_DMA_THIS s[ma_sl].flip_flop = !BX_DMA_THIS s[ma_sl].flip_flop;
|
|
break;
|
|
|
|
case 0x01:
|
|
case 0x03:
|
|
case 0x05:
|
|
case 0x07:
|
|
case 0xc2:
|
|
case 0xc6:
|
|
case 0xca:
|
|
case 0xce:
|
|
channel = (address >> (1 + ma_sl)) & 0x03;
|
|
BX_DEBUG((" DMA-%d base and current count, channel %d", ma_sl+1, channel));
|
|
if (BX_DMA_THIS s[ma_sl].flip_flop==0) { /* 1st byte */
|
|
BX_DMA_THIS s[ma_sl].chan[channel].base_count = value;
|
|
BX_DMA_THIS s[ma_sl].chan[channel].current_count = value;
|
|
} else { /* 2nd byte */
|
|
BX_DMA_THIS s[ma_sl].chan[channel].base_count |= (value << 8);
|
|
BX_DMA_THIS s[ma_sl].chan[channel].current_count |= (value << 8);
|
|
BX_DEBUG((" base = %04x", BX_DMA_THIS s[ma_sl].chan[channel].base_count));
|
|
BX_DEBUG((" curr = %04x", BX_DMA_THIS s[ma_sl].chan[channel].current_count));
|
|
}
|
|
BX_DMA_THIS s[ma_sl].flip_flop = !BX_DMA_THIS s[ma_sl].flip_flop;
|
|
break;
|
|
|
|
case 0x08: /* DMA-1: command register */
|
|
case 0xd0: /* DMA-2: command register */
|
|
if ((value & 0xfb) != 0x00)
|
|
BX_ERROR(("write to command register: value 0x%02x not supported",
|
|
(unsigned) value));
|
|
BX_DMA_THIS s[ma_sl].command_reg = value;
|
|
BX_DMA_THIS s[ma_sl].ctrl_disabled = (value >> 2) & 0x01;
|
|
control_HRQ(ma_sl);
|
|
break;
|
|
|
|
case 0x09: // DMA-1: request register
|
|
case 0xd2: // DMA-2: request register
|
|
channel = value & 0x03;
|
|
// note: write to 0x0d / 0xda clears this register
|
|
if (value & 0x04) {
|
|
// set request bit
|
|
BX_DMA_THIS s[ma_sl].status_reg |= (1 << (channel+4));
|
|
BX_DEBUG(("DMA-%d: set request bit for channel %u", ma_sl+1, channel));
|
|
} else {
|
|
// clear request bit
|
|
BX_DMA_THIS s[ma_sl].status_reg &= ~(1 << (channel+4));
|
|
BX_DEBUG(("DMA-%d: cleared request bit for channel %u", ma_sl+1, channel));
|
|
}
|
|
control_HRQ(ma_sl);
|
|
break;
|
|
|
|
case 0x0a:
|
|
case 0xd4:
|
|
set_mask_bit = value & 0x04;
|
|
channel = value & 0x03;
|
|
BX_DMA_THIS s[ma_sl].mask[channel] = (set_mask_bit > 0);
|
|
BX_DEBUG(("DMA-%d: set_mask_bit=%u, channel=%u, mask now=%02xh", ma_sl+1,
|
|
set_mask_bit, channel, BX_DMA_THIS s[ma_sl].mask[channel]));
|
|
control_HRQ(ma_sl);
|
|
break;
|
|
|
|
case 0x0b: /* DMA-1 mode register */
|
|
case 0xd6: /* DMA-2 mode register */
|
|
channel = value & 0x03;
|
|
BX_DMA_THIS s[ma_sl].chan[channel].mode.mode_type = (value >> 6) & 0x03;
|
|
BX_DMA_THIS s[ma_sl].chan[channel].mode.address_decrement = (value >> 5) & 0x01;
|
|
BX_DMA_THIS s[ma_sl].chan[channel].mode.autoinit_enable = (value >> 4) & 0x01;
|
|
BX_DMA_THIS s[ma_sl].chan[channel].mode.transfer_type = (value >> 2) & 0x03;
|
|
BX_DEBUG(("DMA-%d: mode register[%u] = %02x", ma_sl+1, channel, (unsigned) value));
|
|
break;
|
|
|
|
case 0x0c: /* DMA-1 clear byte flip/flop */
|
|
case 0xd8: /* DMA-2 clear byte flip/flop */
|
|
BX_DEBUG(("DMA-%d: clear flip/flop", ma_sl+1));
|
|
BX_DMA_THIS s[ma_sl].flip_flop = 0;
|
|
break;
|
|
|
|
case 0x0d: // DMA-1: master clear
|
|
case 0xda: // DMA-2: master clear
|
|
BX_DEBUG(("DMA-%d: master clear", ma_sl+1));
|
|
// writing any value to this port resets DMA controller 1 / 2
|
|
// same action as a hardware reset
|
|
// mask register is set (chan 0..3 disabled)
|
|
// command, status, request, temporary, and byte flip-flop are all cleared
|
|
reset_controller(ma_sl);
|
|
break;
|
|
|
|
case 0x0e: // DMA-1: clear mask register
|
|
case 0xdc: // DMA-2: clear mask register
|
|
BX_DEBUG(("DMA-%d: clear mask register", ma_sl+1));
|
|
BX_DMA_THIS s[ma_sl].mask[0] = 0;
|
|
BX_DMA_THIS s[ma_sl].mask[1] = 0;
|
|
BX_DMA_THIS s[ma_sl].mask[2] = 0;
|
|
BX_DMA_THIS s[ma_sl].mask[3] = 0;
|
|
control_HRQ(ma_sl);
|
|
break;
|
|
|
|
case 0x0f: // DMA-1: write all mask bits
|
|
case 0xde: // DMA-2: write all mask bits
|
|
BX_DEBUG(("DMA-%d: write all mask bits", ma_sl+1));
|
|
BX_DMA_THIS s[ma_sl].mask[0] = value & 0x01; value >>= 1;
|
|
BX_DMA_THIS s[ma_sl].mask[1] = value & 0x01; value >>= 1;
|
|
BX_DMA_THIS s[ma_sl].mask[2] = value & 0x01; value >>= 1;
|
|
BX_DMA_THIS s[ma_sl].mask[3] = value & 0x01;
|
|
control_HRQ(ma_sl);
|
|
break;
|
|
|
|
case 0x81: /* DMA-1 page register, channel 2 */
|
|
case 0x82: /* DMA-1 page register, channel 3 */
|
|
case 0x83: /* DMA-1 page register, channel 1 */
|
|
case 0x87: /* DMA-1 page register, channel 0 */
|
|
/* address bits A16-A23 for DMA channel */
|
|
channel = channelindex[address - 0x81];
|
|
BX_DMA_THIS s[0].chan[channel].page_reg = value;
|
|
BX_DEBUG(("DMA-1: page register %d = %02x", channel, (unsigned) value));
|
|
break;
|
|
|
|
case 0x89: /* DMA-2 page register, channel 2 */
|
|
case 0x8a: /* DMA-2 page register, channel 3 */
|
|
case 0x8b: /* DMA-2 page register, channel 1 */
|
|
case 0x8f: /* DMA-2 page register, channel 0 */
|
|
/* address bits A16-A23 for DMA channel */
|
|
channel = channelindex[address - 0x89];
|
|
BX_DMA_THIS s[1].chan[channel].page_reg = value;
|
|
BX_DEBUG(("DMA-2: page register %d = %02x", channel + 4, (unsigned) value));
|
|
break;
|
|
|
|
case 0x0080:
|
|
case 0x0084:
|
|
case 0x0085:
|
|
case 0x0086:
|
|
case 0x0088:
|
|
case 0x008c:
|
|
case 0x008d:
|
|
case 0x008e:
|
|
BX_DEBUG(("write: extra page register 0x%04x (unused)", (unsigned) address));
|
|
BX_DMA_THIS ext_page_reg[address & 0x0f] = value;
|
|
break;
|
|
|
|
default:
|
|
BX_ERROR(("write ignored: %04xh = %02xh",
|
|
(unsigned) address, (unsigned) value));
|
|
}
|
|
}
|
|
|
|
void bx_dma_c::set_DRQ(unsigned channel, bx_bool val)
|
|
{
|
|
Bit32u dma_base, dma_roof;
|
|
bx_bool ma_sl;
|
|
|
|
if (channel > 7) {
|
|
BX_PANIC(("set_DRQ() channel > 7"));
|
|
return;
|
|
}
|
|
ma_sl = (channel > 3);
|
|
BX_DMA_THIS s[ma_sl].DRQ[channel & 0x03] = val;
|
|
if (!BX_DMA_THIS s[ma_sl].chan[channel & 0x03].used) {
|
|
BX_PANIC(("set_DRQ(): channel %d not connected to device", channel));
|
|
return;
|
|
}
|
|
channel &= 0x03;
|
|
if (!val) {
|
|
// clear bit in status reg
|
|
BX_DMA_THIS s[ma_sl].status_reg &= ~(1 << (channel+4));
|
|
|
|
control_HRQ(ma_sl);
|
|
return;
|
|
}
|
|
|
|
BX_DMA_THIS s[ma_sl].status_reg |= (1 << (channel+4));
|
|
|
|
if ((BX_DMA_THIS s[ma_sl].chan[channel].mode.mode_type != DMA_MODE_SINGLE) &&
|
|
(BX_DMA_THIS s[ma_sl].chan[channel].mode.mode_type != DMA_MODE_DEMAND) &&
|
|
(BX_DMA_THIS s[ma_sl].chan[channel].mode.mode_type != DMA_MODE_CASCADE))
|
|
{
|
|
BX_PANIC(("set_DRQ: mode_type(%02x) not handled",
|
|
BX_DMA_THIS s[ma_sl].chan[channel].mode.mode_type));
|
|
}
|
|
|
|
dma_base = (BX_DMA_THIS s[ma_sl].chan[channel].page_reg << 16) |
|
|
(BX_DMA_THIS s[ma_sl].chan[channel].base_address << ma_sl);
|
|
if (BX_DMA_THIS s[ma_sl].chan[channel].mode.address_decrement==0) {
|
|
dma_roof = dma_base + (BX_DMA_THIS s[ma_sl].chan[channel].base_count << ma_sl);
|
|
} else {
|
|
dma_roof = dma_base - (BX_DMA_THIS s[ma_sl].chan[channel].base_count << ma_sl);
|
|
}
|
|
if ((dma_base & (0x7fff0000 << ma_sl)) != (dma_roof & (0x7fff0000 << ma_sl))) {
|
|
BX_INFO(("dma_base = 0x%08x", dma_base));
|
|
BX_INFO(("dma_base_count = 0x%08x", BX_DMA_THIS s[ma_sl].chan[channel].base_count));
|
|
BX_INFO(("dma_roof = 0x%08x", dma_roof));
|
|
BX_PANIC(("request outside %dk boundary", 64 << ma_sl));
|
|
}
|
|
|
|
control_HRQ(ma_sl);
|
|
}
|
|
|
|
void bx_dma_c::control_HRQ(bx_bool ma_sl)
|
|
{
|
|
unsigned channel;
|
|
|
|
// do nothing if controller is disabled
|
|
if (BX_DMA_THIS s[ma_sl].ctrl_disabled)
|
|
return;
|
|
|
|
// deassert HRQ if no DRQ is pending
|
|
if ((BX_DMA_THIS s[ma_sl].status_reg & 0xf0) == 0) {
|
|
if (ma_sl) {
|
|
bx_pc_system.set_HRQ(0);
|
|
} else {
|
|
BX_DMA_THIS set_DRQ(4, 0);
|
|
}
|
|
return;
|
|
}
|
|
// find highest priority channel
|
|
for (channel=0; channel<4; channel++) {
|
|
if ((BX_DMA_THIS s[ma_sl].status_reg & (1 << (channel+4))) &&
|
|
(BX_DMA_THIS s[ma_sl].mask[channel]==0)) {
|
|
if (ma_sl) {
|
|
// assert Hold ReQuest line to CPU
|
|
bx_pc_system.set_HRQ(1);
|
|
} else {
|
|
// send DRQ to cascade channel of the master
|
|
BX_DMA_THIS set_DRQ(4, 1);
|
|
}
|
|
break;
|
|
}
|
|
}
|
|
}
|
|
|
|
void bx_dma_c::raise_HLDA(void)
|
|
{
|
|
unsigned channel;
|
|
bx_phy_address phy_addr;
|
|
bx_bool ma_sl = 0;
|
|
Bit16u maxlen, len = 1;
|
|
Bit8u buffer[BX_DMA_BUFFER_SIZE];
|
|
|
|
BX_DMA_THIS HLDA = 1;
|
|
// find highest priority channel
|
|
for (channel=0; channel<4; channel++) {
|
|
if ((BX_DMA_THIS s[1].status_reg & (1 << (channel+4))) &&
|
|
(BX_DMA_THIS s[1].mask[channel]==0)) {
|
|
ma_sl = 1;
|
|
break;
|
|
}
|
|
}
|
|
if (channel == 0) { // master cascade channel
|
|
BX_DMA_THIS s[1].DACK[0] = 1;
|
|
for (channel=0; channel<4; channel++) {
|
|
if ((BX_DMA_THIS s[0].status_reg & (1 << (channel+4))) &&
|
|
(BX_DMA_THIS s[0].mask[channel]==0)) {
|
|
ma_sl = 0;
|
|
break;
|
|
}
|
|
}
|
|
}
|
|
if (channel >= 4) {
|
|
// wait till they're unmasked
|
|
return;
|
|
}
|
|
|
|
phy_addr = (BX_DMA_THIS s[ma_sl].chan[channel].page_reg << 16) |
|
|
(BX_DMA_THIS s[ma_sl].chan[channel].current_address << ma_sl);
|
|
|
|
if (!BX_DMA_THIS s[ma_sl].chan[channel].mode.address_decrement) {
|
|
maxlen = (BX_DMA_THIS s[ma_sl].chan[channel].current_count + 1) << ma_sl;
|
|
BX_DMA_THIS TC = (maxlen <= BX_DMA_BUFFER_SIZE);
|
|
if (maxlen > BX_DMA_BUFFER_SIZE) {
|
|
maxlen = BX_DMA_BUFFER_SIZE;
|
|
}
|
|
} else {
|
|
BX_DMA_THIS TC = (BX_DMA_THIS s[ma_sl].chan[channel].current_count == 0);
|
|
maxlen = 1 << ma_sl;
|
|
}
|
|
|
|
if (BX_DMA_THIS s[ma_sl].chan[channel].mode.transfer_type == 1) { // write
|
|
// DMA controlled xfer of bytes from I/O to Memory
|
|
|
|
if (!ma_sl) {
|
|
if (BX_DMA_THIS h[channel].dmaWrite8)
|
|
len = BX_DMA_THIS h[channel].dmaWrite8(buffer, maxlen);
|
|
else
|
|
BX_PANIC(("no dmaWrite handler for channel %u.", channel));
|
|
|
|
DEV_MEM_WRITE_PHYSICAL_DMA(phy_addr, len, buffer);
|
|
|
|
BX_DBG_DMA_REPORT(phy_addr, len, BX_WRITE, buffer[0]); // FIXME
|
|
} else {
|
|
if (BX_DMA_THIS h[channel].dmaWrite16)
|
|
len = BX_DMA_THIS h[channel].dmaWrite16((Bit16u*)buffer, maxlen / 2);
|
|
else
|
|
BX_PANIC(("no dmaWrite handler for channel %u.", channel));
|
|
|
|
DEV_MEM_WRITE_PHYSICAL_DMA(phy_addr, len, buffer);
|
|
|
|
BX_DBG_DMA_REPORT(phy_addr, len * 2, BX_WRITE, buffer[0] | (buffer[1] << 16)); // FIXME
|
|
}
|
|
} else if (BX_DMA_THIS s[ma_sl].chan[channel].mode.transfer_type == 2) { // read
|
|
// DMA controlled xfer of bytes from Memory to I/O
|
|
|
|
if (!ma_sl) {
|
|
DEV_MEM_READ_PHYSICAL_DMA(phy_addr, maxlen, buffer);
|
|
|
|
if (BX_DMA_THIS h[channel].dmaRead8)
|
|
len = BX_DMA_THIS h[channel].dmaRead8(buffer, maxlen);
|
|
|
|
BX_DBG_DMA_REPORT(phy_addr, len, BX_READ, buffer[0]); // FIXME
|
|
} else {
|
|
DEV_MEM_READ_PHYSICAL_DMA(phy_addr, maxlen, buffer);
|
|
|
|
if (BX_DMA_THIS h[channel].dmaRead16)
|
|
len = BX_DMA_THIS h[channel].dmaRead16((Bit16u*)buffer, maxlen / 2);
|
|
|
|
BX_DBG_DMA_REPORT(phy_addr, len * 2, BX_READ, buffer[0] | (buffer[1] << 16)); // FIXME
|
|
}
|
|
} else if (BX_DMA_THIS s[ma_sl].chan[channel].mode.transfer_type == 0) {
|
|
// verify
|
|
|
|
if (!ma_sl) {
|
|
if (BX_DMA_THIS h[channel].dmaWrite8)
|
|
len = BX_DMA_THIS h[channel].dmaWrite8(buffer, 1);
|
|
else
|
|
BX_PANIC(("no dmaWrite handler for channel %u.", channel));
|
|
} else {
|
|
if (BX_DMA_THIS h[channel].dmaWrite16)
|
|
len = BX_DMA_THIS h[channel].dmaWrite16((Bit16u*)buffer, 1);
|
|
else
|
|
BX_PANIC(("no dmaWrite handler for channel %u.", channel));
|
|
}
|
|
} else {
|
|
BX_PANIC(("hlda: transfer_type 3 is undefined"));
|
|
}
|
|
|
|
BX_DMA_THIS s[ma_sl].DACK[channel] = 1;
|
|
// check for expiration of count, so we can signal TC and DACK(n)
|
|
// at the same time.
|
|
if (!BX_DMA_THIS s[ma_sl].chan[channel].mode.address_decrement)
|
|
BX_DMA_THIS s[ma_sl].chan[channel].current_address += len;
|
|
else
|
|
BX_DMA_THIS s[ma_sl].chan[channel].current_address--;
|
|
BX_DMA_THIS s[ma_sl].chan[channel].current_count -= len;
|
|
if (BX_DMA_THIS s[ma_sl].chan[channel].current_count == 0xffff) {
|
|
// count expired, done with transfer
|
|
// assert TC, deassert HRQ & DACK(n) lines
|
|
BX_DMA_THIS s[ma_sl].status_reg |= (1 << channel); // hold TC in status reg
|
|
if (BX_DMA_THIS s[ma_sl].chan[channel].mode.autoinit_enable == 0) {
|
|
// set mask bit if not in autoinit mode
|
|
BX_DMA_THIS s[ma_sl].mask[channel] = 1;
|
|
} else {
|
|
// count expired, but in autoinit mode
|
|
// reload count and base address
|
|
BX_DMA_THIS s[ma_sl].chan[channel].current_address =
|
|
BX_DMA_THIS s[ma_sl].chan[channel].base_address;
|
|
BX_DMA_THIS s[ma_sl].chan[channel].current_count =
|
|
BX_DMA_THIS s[ma_sl].chan[channel].base_count;
|
|
}
|
|
BX_DMA_THIS TC = 0; // clear TC, adapter card already notified
|
|
BX_DMA_THIS HLDA = 0;
|
|
bx_pc_system.set_HRQ(0); // clear HRQ to CPU
|
|
BX_DMA_THIS s[ma_sl].DACK[channel] = 0; // clear DACK to adapter card
|
|
if (!ma_sl) {
|
|
BX_DMA_THIS set_DRQ(4, 0); // clear DRQ to cascade
|
|
BX_DMA_THIS s[1].DACK[0] = 0; // clear DACK to cascade
|
|
}
|
|
}
|
|
}
|
|
|
|
#if BX_DEBUGGER
|
|
void bx_dma_c::debug_dump(int argc, char **argv)
|
|
{
|
|
int ch, i, j;
|
|
|
|
dbg_printf("i8237A DMA controller\n\n");
|
|
for (i = 0; i < 2; i++) {
|
|
for (j = 0; j < 4; j++) {
|
|
if (BX_DMA_THIS s[i].chan[j].used) {
|
|
ch = i * 4 + j;
|
|
dbg_printf("DMA channel %d", ch);
|
|
if (ch == 4) {
|
|
dbg_printf(" (cascade)\n");
|
|
} else if (BX_DMA_THIS s[i].DRQ[j] && !BX_DMA_THIS s[i].mask[j]) {
|
|
dbg_printf(" (active)\n");
|
|
dbg_printf(" address: base=0x%04x, current=0x%04x\n", BX_DMA_THIS s[i].chan[j].base_address,
|
|
BX_DMA_THIS s[i].chan[j].current_address);
|
|
dbg_printf(" count: base=0x%04x, current=0x%04x\n", BX_DMA_THIS s[i].chan[j].base_count,
|
|
BX_DMA_THIS s[i].chan[j].current_count);
|
|
dbg_printf(" page: 0x%02x\n", BX_DMA_THIS s[i].chan[j].page_reg);
|
|
dbg_printf(" mask: %u\n", BX_DMA_THIS s[i].mask[j]);
|
|
dbg_printf(" flip_flop: %u\n", BX_DMA_THIS s[i].flip_flop);
|
|
dbg_printf(" status_reg: 0x%02x\n", BX_DMA_THIS s[i].status_reg);
|
|
dbg_printf(" mode_type: %u\n", BX_DMA_THIS s[i].chan[j].mode.mode_type);
|
|
dbg_printf(" address_decrement: %u\n", BX_DMA_THIS s[i].chan[j].mode.address_decrement);
|
|
dbg_printf(" autoinit_enable: %u\n", BX_DMA_THIS s[i].chan[j].mode.autoinit_enable);
|
|
dbg_printf(" transfer_type: %u\n", BX_DMA_THIS s[i].chan[j].mode.transfer_type);
|
|
} else {
|
|
dbg_printf(" (not active: DRQ=%u, mask=%u)\n", BX_DMA_THIS s[i].DRQ[j],
|
|
BX_DMA_THIS s[i].mask[j]);
|
|
}
|
|
}
|
|
}
|
|
}
|
|
if (argc > 0) {
|
|
dbg_printf("\nAdditional options not supported\n");
|
|
}
|
|
}
|
|
#endif
|