448 lines
17 KiB
C++
448 lines
17 KiB
C++
/////////////////////////////////////////////////////////////////////////
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// $Id: debugstuff.cc,v 1.91 2008-02-01 13:25:23 sshwarts Exp $
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/////////////////////////////////////////////////////////////////////////
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//
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// Copyright (C) 2001 MandrakeSoft S.A.
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//
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// MandrakeSoft S.A.
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// 43, rue d'Aboukir
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// 75002 Paris - France
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// http://www.linux-mandrake.com/
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// http://www.mandrakesoft.com/
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//
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// This library is free software; you can redistribute it and/or
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// modify it under the terms of the GNU Lesser General Public
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// License as published by the Free Software Foundation; either
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// version 2 of the License, or (at your option) any later version.
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//
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// This library is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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// Lesser General Public License for more details.
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//
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// You should have received a copy of the GNU Lesser General Public
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// License along with this library; if not, write to the Free Software
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// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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//
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/////////////////////////////////////////////////////////////////////////
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#define NEED_CPU_REG_SHORTCUTS 1
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#include "bochs.h"
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#include "cpu.h"
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#define LOG_THIS BX_CPU_THIS_PTR
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#if BX_DISASM
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void BX_CPU_C::debug_disasm_instruction(bx_address offset)
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{
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#if BX_DEBUGGER
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bx_dbg_disassemble_current(BX_CPU_ID, 1); // only one cpu, print time stamp
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#else
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bx_phy_address phy_addr;
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Bit8u instr_buf[16];
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char char_buf[512];
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size_t i=0;
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static char letters[] = "0123456789ABCDEF";
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static disassembler bx_disassemble;
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unsigned remainsInPage = 0x1000 - PAGE_OFFSET(offset);
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bx_bool valid = dbg_xlate_linear2phy(BX_CPU_THIS_PTR get_segment_base(BX_SEG_REG_CS) + offset, &phy_addr);
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if (valid && BX_CPU_THIS_PTR mem!=NULL) {
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BX_CPU_THIS_PTR mem->dbg_fetch_mem(BX_CPU_THIS, phy_addr, 16, instr_buf);
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unsigned isize = bx_disassemble.disasm(
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BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.u.segment.d_b,
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BX_CPU_THIS_PTR cpu_mode == BX_MODE_LONG_64,
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BX_CPU_THIS_PTR get_segment_base(BX_SEG_REG_CS), offset,
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instr_buf, char_buf+i);
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if (isize <= remainsInPage) {
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i=strlen(char_buf);
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char_buf[i++] = ' ';
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char_buf[i++] = ':';
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char_buf[i++] = ' ';
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for (unsigned j=0; j<isize; j++) {
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char_buf[i++] = letters[(instr_buf[j] >> 4) & 0xf];
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char_buf[i++] = letters[(instr_buf[j] >> 0) & 0xf];
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}
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char_buf[i] = 0;
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BX_INFO((">> %s", char_buf));
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}
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else {
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BX_INFO(("(instruction unavailable) page split instruction"));
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}
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}
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else {
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BX_INFO(("(instruction unavailable) page not present"));
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}
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#endif // #if BX_DEBUGGER
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}
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#endif // #if BX_DISASM
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const char* cpu_mode_string(unsigned cpu_mode)
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{
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static const char *cpu_mode_name[] = {
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"real mode",
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"v8086 mode",
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"protected mode",
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"compatibility mode",
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"long mode",
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"unknown mode"
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};
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if(cpu_mode >= 5) cpu_mode = 5;
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return cpu_mode_name[cpu_mode];
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}
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const char* cpu_state_string(Bit32u debug_trap)
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{
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unsigned cpu_state = 5; // unknown state
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static const char *cpu_state_name[] = {
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"active",
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"executing mwait",
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"waiting for SIPI",
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"in shutdown",
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"halted",
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"unknown state"
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};
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if(debug_trap & BX_DEBUG_TRAP_HALT) cpu_state = 4;
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else if (debug_trap & BX_DEBUG_TRAP_SHUTDOWN) cpu_state = 3;
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else if (debug_trap & BX_DEBUG_TRAP_WAIT_FOR_SIPI) cpu_state = 2;
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else if (debug_trap & BX_DEBUG_TRAP_MWAIT) cpu_state = 1;
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else if (debug_trap & BX_DEBUG_TRAP_SPECIAL) cpu_state = 5;
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else cpu_state = 0;
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return cpu_state_name[cpu_state];
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}
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void BX_CPU_C::debug(bx_address offset)
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{
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BX_INFO(("CPU is in %s (%s)", cpu_mode_string(BX_CPU_THIS_PTR get_cpu_mode()),
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cpu_state_string(BX_CPU_THIS_PTR debug_trap)));
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BX_INFO(("CS.d_b = %u bit",
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BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.u.segment.d_b ? 32 : 16));
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BX_INFO(("SS.d_b = %u bit",
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BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].cache.u.segment.d_b ? 32 : 16));
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#if BX_SUPPORT_X86_64
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BX_INFO(("EFER = 0x%08x", BX_CPU_THIS_PTR get_EFER()));
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BX_INFO(("| RAX=%08x%08x RBX=%08x%08x",
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(unsigned) (RAX >> 32), (unsigned) EAX,
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(unsigned) (RBX >> 32), (unsigned) EBX));
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BX_INFO(("| RCX=%08x%08x RDX=%08x%08x",
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(unsigned) (RCX >> 32), (unsigned) ECX,
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(unsigned) (RDX >> 32), (unsigned) EDX));
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BX_INFO(("| RSP=%08x%08x RBP=%08x%08x",
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(unsigned) (RSP >> 32), (unsigned) ESP,
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(unsigned) (RBP >> 32), (unsigned) EBP));
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BX_INFO(("| RSI=%08x%08x RDI=%08x%08x",
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(unsigned) (RSI >> 32), (unsigned) ESI,
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(unsigned) (RDI >> 32), (unsigned) EDI));
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BX_INFO(("| R8=%08x%08x R9=%08x%08x",
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(unsigned) (R8 >> 32), (unsigned) (R8 & 0xFFFFFFFF),
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(unsigned) (R9 >> 32), (unsigned) (R9 & 0xFFFFFFFF)));
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BX_INFO(("| R10=%08x%08x R11=%08x%08x",
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(unsigned) (R10 >> 32), (unsigned) (R10 & 0xFFFFFFFF),
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(unsigned) (R11 >> 32), (unsigned) (R11 & 0xFFFFFFFF)));
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BX_INFO(("| R12=%08x%08x R13=%08x%08x",
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(unsigned) (R12 >> 32), (unsigned) (R12 & 0xFFFFFFFF),
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(unsigned) (R13 >> 32), (unsigned) (R13 & 0xFFFFFFFF)));
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BX_INFO(("| R14=%08x%08x R15=%08x%08x",
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(unsigned) (R14 >> 32), (unsigned) (R14 & 0xFFFFFFFF),
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(unsigned) (R15 >> 32), (unsigned) (R15 & 0xFFFFFFFF)));
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#else
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BX_INFO(("| EAX=%08x EBX=%08x ECX=%08x EDX=%08x",
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(unsigned) EAX, (unsigned) EBX, (unsigned) ECX, (unsigned) EDX));
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BX_INFO(("| ESP=%08x EBP=%08x ESI=%08x EDI=%08x",
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(unsigned) ESP, (unsigned) EBP, (unsigned) ESI, (unsigned) EDI));
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#endif
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BX_INFO(("| IOPL=%1u %s %s %s %s %s %s %s %s %s %s %s %s %s %s %s %s",
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BX_CPU_THIS_PTR get_IOPL(),
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BX_CPU_THIS_PTR get_ID() ? "ID" : "id",
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BX_CPU_THIS_PTR get_VIP() ? "VIP" : "vip",
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BX_CPU_THIS_PTR get_VIF() ? "VIF" : "vif",
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BX_CPU_THIS_PTR get_AC() ? "AC" : "ac",
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BX_CPU_THIS_PTR get_VM() ? "VM" : "vm",
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BX_CPU_THIS_PTR get_RF() ? "RF" : "rf",
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BX_CPU_THIS_PTR get_NT() ? "NT" : "nt",
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BX_CPU_THIS_PTR get_OF() ? "OF" : "of",
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BX_CPU_THIS_PTR get_DF() ? "DF" : "df",
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BX_CPU_THIS_PTR get_IF() ? "IF" : "if",
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BX_CPU_THIS_PTR get_TF() ? "TF" : "tf",
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BX_CPU_THIS_PTR get_SF() ? "SF" : "sf",
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BX_CPU_THIS_PTR get_ZF() ? "ZF" : "zf",
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BX_CPU_THIS_PTR get_AF() ? "AF" : "af",
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BX_CPU_THIS_PTR get_PF() ? "PF" : "pf",
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BX_CPU_THIS_PTR get_CF() ? "CF" : "cf"));
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BX_INFO(("| SEG selector base limit G D"));
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BX_INFO(("| SEG sltr(index|ti|rpl) base limit G D"));
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BX_INFO(("| CS:%04x( %04x| %01u| %1u) %08x %08x %1u %1u",
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(unsigned) BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].selector.value,
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(unsigned) BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].selector.index,
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(unsigned) BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].selector.ti,
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(unsigned) BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].selector.rpl,
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(unsigned) BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.u.segment.base,
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(unsigned) BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.u.segment.limit,
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(unsigned) BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.u.segment.g,
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(unsigned) BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.u.segment.d_b));
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BX_INFO(("| DS:%04x( %04x| %01u| %1u) %08x %08x %1u %1u",
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(unsigned) BX_CPU_THIS_PTR sregs[BX_SEG_REG_DS].selector.value,
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(unsigned) BX_CPU_THIS_PTR sregs[BX_SEG_REG_DS].selector.index,
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(unsigned) BX_CPU_THIS_PTR sregs[BX_SEG_REG_DS].selector.ti,
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(unsigned) BX_CPU_THIS_PTR sregs[BX_SEG_REG_DS].selector.rpl,
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(unsigned) BX_CPU_THIS_PTR sregs[BX_SEG_REG_DS].cache.u.segment.base,
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(unsigned) BX_CPU_THIS_PTR sregs[BX_SEG_REG_DS].cache.u.segment.limit,
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(unsigned) BX_CPU_THIS_PTR sregs[BX_SEG_REG_DS].cache.u.segment.g,
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(unsigned) BX_CPU_THIS_PTR sregs[BX_SEG_REG_DS].cache.u.segment.d_b));
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BX_INFO(("| SS:%04x( %04x| %01u| %1u) %08x %08x %1u %1u",
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(unsigned) BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].selector.value,
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(unsigned) BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].selector.index,
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(unsigned) BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].selector.ti,
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(unsigned) BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].selector.rpl,
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(unsigned) BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].cache.u.segment.base,
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(unsigned) BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].cache.u.segment.limit,
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(unsigned) BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].cache.u.segment.g,
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(unsigned) BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].cache.u.segment.d_b));
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BX_INFO(("| ES:%04x( %04x| %01u| %1u) %08x %08x %1u %1u",
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(unsigned) BX_CPU_THIS_PTR sregs[BX_SEG_REG_ES].selector.value,
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(unsigned) BX_CPU_THIS_PTR sregs[BX_SEG_REG_ES].selector.index,
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(unsigned) BX_CPU_THIS_PTR sregs[BX_SEG_REG_ES].selector.ti,
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(unsigned) BX_CPU_THIS_PTR sregs[BX_SEG_REG_ES].selector.rpl,
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(unsigned) BX_CPU_THIS_PTR sregs[BX_SEG_REG_ES].cache.u.segment.base,
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(unsigned) BX_CPU_THIS_PTR sregs[BX_SEG_REG_ES].cache.u.segment.limit,
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(unsigned) BX_CPU_THIS_PTR sregs[BX_SEG_REG_ES].cache.u.segment.g,
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(unsigned) BX_CPU_THIS_PTR sregs[BX_SEG_REG_ES].cache.u.segment.d_b));
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BX_INFO(("| FS:%04x( %04x| %01u| %1u) %08x %08x %1u %1u",
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(unsigned) BX_CPU_THIS_PTR sregs[BX_SEG_REG_FS].selector.value,
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(unsigned) BX_CPU_THIS_PTR sregs[BX_SEG_REG_FS].selector.index,
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(unsigned) BX_CPU_THIS_PTR sregs[BX_SEG_REG_FS].selector.ti,
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(unsigned) BX_CPU_THIS_PTR sregs[BX_SEG_REG_FS].selector.rpl,
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(unsigned) BX_CPU_THIS_PTR sregs[BX_SEG_REG_FS].cache.u.segment.base,
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(unsigned) BX_CPU_THIS_PTR sregs[BX_SEG_REG_FS].cache.u.segment.limit,
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(unsigned) BX_CPU_THIS_PTR sregs[BX_SEG_REG_FS].cache.u.segment.g,
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(unsigned) BX_CPU_THIS_PTR sregs[BX_SEG_REG_FS].cache.u.segment.d_b));
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BX_INFO(("| GS:%04x( %04x| %01u| %1u) %08x %08x %1u %1u",
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(unsigned) BX_CPU_THIS_PTR sregs[BX_SEG_REG_GS].selector.value,
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(unsigned) BX_CPU_THIS_PTR sregs[BX_SEG_REG_GS].selector.index,
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(unsigned) BX_CPU_THIS_PTR sregs[BX_SEG_REG_GS].selector.ti,
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(unsigned) BX_CPU_THIS_PTR sregs[BX_SEG_REG_GS].selector.rpl,
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(unsigned) BX_CPU_THIS_PTR sregs[BX_SEG_REG_GS].cache.u.segment.base,
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(unsigned) BX_CPU_THIS_PTR sregs[BX_SEG_REG_GS].cache.u.segment.limit,
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(unsigned) BX_CPU_THIS_PTR sregs[BX_SEG_REG_GS].cache.u.segment.g,
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(unsigned) BX_CPU_THIS_PTR sregs[BX_SEG_REG_GS].cache.u.segment.d_b));
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#if BX_SUPPORT_X86_64
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BX_INFO(("| MSR_FS_BASE:%08x%08x",
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(unsigned) (MSR_FSBASE >> 32), (unsigned) (MSR_FSBASE & 0xFFFFFFFF)));
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BX_INFO(("| MSR_GS_BASE:%08x%08x",
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(unsigned) (MSR_GSBASE >> 32), (unsigned) (MSR_GSBASE & 0xFFFFFFFF)));
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#endif
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#if BX_SUPPORT_X86_64
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BX_INFO(("| RIP=%08x%08x (%08x%08x)",
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(unsigned) BX_CPU_THIS_PTR eip_reg.dword.rip_upper, (unsigned) EIP,
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(unsigned) (BX_CPU_THIS_PTR prev_rip >> 32),
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(unsigned) (BX_CPU_THIS_PTR prev_rip & 0xffffffff)));
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BX_INFO(("| CR0=0x%08x CR1=0x%x CR2=0x%08x%08x",
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(unsigned) (BX_CPU_THIS_PTR cr0.val32), 0,
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(unsigned) (BX_CPU_THIS_PTR cr2 >> 32),
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(unsigned) (BX_CPU_THIS_PTR cr2 & 0xffffffff)));
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BX_INFO(("| CR3=0x%08x CR4=0x%08x",
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(unsigned) BX_CPU_THIS_PTR cr3, BX_CPU_THIS_PTR cr4.getRegister()));
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#else
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BX_INFO(("| EIP=%08x (%08x)", (unsigned) EIP,
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(unsigned) BX_CPU_THIS_PTR prev_rip));
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#if BX_CPU_LEVEL >= 2 && BX_CPU_LEVEL < 4
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BX_INFO(("| CR0=0x%08x CR1=%x CR2=0x%08x CR3=0x%08x",
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BX_CPU_THIS_PTR cr0.val32, 0,
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BX_CPU_THIS_PTR cr2,
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BX_CPU_THIS_PTR cr3));
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#elif BX_CPU_LEVEL >= 4
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BX_INFO(("| CR0=0x%08x CR1=%x CR2=0x%08x",
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BX_CPU_THIS_PTR cr0.val32, 0,
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BX_CPU_THIS_PTR cr2));
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BX_INFO(("| CR3=0x%08x CR4=0x%08x",
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BX_CPU_THIS_PTR cr3,
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BX_CPU_THIS_PTR cr4.getRegister()));
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#endif
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#endif // BX_SUPPORT_X86_64
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#if BX_DISASM
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debug_disasm_instruction(offset);
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#endif // #if BX_DISASM
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}
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#if BX_DEBUGGER
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Bit32u BX_CPU_C::dbg_get_reg(unsigned reg)
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{
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Bit32u return_val32;
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switch (reg) {
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case BX_DBG_REG_EIP: return(EIP);
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case BX_DBG_REG_EFLAGS:
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return_val32 = BX_CPU_THIS_PTR read_eflags();
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return(return_val32);
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case BX_DBG_REG_CS: return(BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].selector.value);
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case BX_DBG_REG_SS: return(BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].selector.value);
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case BX_DBG_REG_DS: return(BX_CPU_THIS_PTR sregs[BX_SEG_REG_DS].selector.value);
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case BX_DBG_REG_ES: return(BX_CPU_THIS_PTR sregs[BX_SEG_REG_ES].selector.value);
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case BX_DBG_REG_FS: return(BX_CPU_THIS_PTR sregs[BX_SEG_REG_FS].selector.value);
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case BX_DBG_REG_GS: return(BX_CPU_THIS_PTR sregs[BX_SEG_REG_GS].selector.value);
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case BX_DBG_REG_CR0:
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return BX_CPU_THIS_PTR cr0.val32;
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case BX_DBG_REG_CR2:
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return BX_CPU_THIS_PTR cr2;
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case BX_DBG_REG_CR3:
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return BX_CPU_THIS_PTR cr3;
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#if BX_CPU_LEVEL >= 4
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case BX_DBG_REG_CR4:
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return BX_CPU_THIS_PTR cr4.getRegister();
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#endif
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default:
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BX_PANIC(("get_reg: request for unknown register"));
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return(0);
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}
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}
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bx_bool BX_CPU_C::dbg_set_reg(unsigned reg, Bit32u val)
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{
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// returns 1=OK, 0=can't change
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bx_segment_reg_t *seg;
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Bit32u current_sys_bits;
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switch (reg) {
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case BX_DBG_REG_EIP: EIP = val; return(1);
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case BX_DBG_REG_EFLAGS:
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BX_INFO(("dbg_set_reg: can not handle eflags yet."));
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if (val & 0xffff0000) {
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BX_INFO(("dbg_set_reg: can not set upper 16 bits of eflags."));
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return(0);
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}
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// make sure none of the system bits are being changed
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current_sys_bits = ((BX_CPU_THIS_PTR getB_NT()) << 14) |
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(BX_CPU_THIS_PTR get_IOPL () << 12) |
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((BX_CPU_THIS_PTR getB_TF()) << 8);
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if (current_sys_bits != (val & 0x0000f100)) {
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BX_INFO(("dbg_set_reg: can not modify NT, IOPL, or TF."));
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return(0);
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}
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BX_CPU_THIS_PTR set_CF(val & 0x01); val >>= 2;
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BX_CPU_THIS_PTR set_PF(val & 0x01); val >>= 2;
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BX_CPU_THIS_PTR set_AF(val & 0x01); val >>= 2;
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BX_CPU_THIS_PTR set_ZF(val & 0x01); val >>= 1;
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BX_CPU_THIS_PTR set_SF(val & 0x01); val >>= 2;
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BX_CPU_THIS_PTR set_IF(val & 0x01); val >>= 1;
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BX_CPU_THIS_PTR set_DF(val & 0x01); val >>= 1;
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BX_CPU_THIS_PTR set_OF(val & 0x01);
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if (BX_CPU_THIS_PTR get_IF())
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BX_CPU_THIS_PTR async_event = 1;
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return(1);
|
|
case BX_DBG_REG_CS:
|
|
seg = &BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS];
|
|
break;
|
|
case BX_DBG_REG_SS:
|
|
seg = &BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS];
|
|
break;
|
|
case BX_DBG_REG_DS:
|
|
seg = &BX_CPU_THIS_PTR sregs[BX_SEG_REG_DS];
|
|
break;
|
|
case BX_DBG_REG_ES:
|
|
seg = &BX_CPU_THIS_PTR sregs[BX_SEG_REG_ES];
|
|
break;
|
|
case BX_DBG_REG_FS:
|
|
seg = &BX_CPU_THIS_PTR sregs[BX_SEG_REG_FS];
|
|
break;
|
|
case BX_DBG_REG_GS:
|
|
seg = &BX_CPU_THIS_PTR sregs[BX_SEG_REG_GS];
|
|
break;
|
|
default:
|
|
BX_PANIC(("dbg_set_reg: unrecognized register ID (%u)", reg));
|
|
return(0);
|
|
}
|
|
|
|
if (real_mode()) {
|
|
seg->selector.value = val;
|
|
seg->cache.valid = 1;
|
|
seg->cache.p = 1;
|
|
seg->cache.dpl = 0;
|
|
seg->cache.segment = 1; // regular segment
|
|
if (reg == BX_DBG_REG_CS)
|
|
seg->cache.type = BX_CODE_EXEC_READ_ACCESSED;
|
|
else
|
|
seg->cache.type = BX_DATA_READ_WRITE_ACCESSED;
|
|
seg->cache.u.segment.base = val << 4;
|
|
seg->cache.u.segment.limit = 0xffff;
|
|
seg->cache.u.segment.limit_scaled = 0xffff;
|
|
seg->cache.u.segment.g = 0; // byte granular
|
|
seg->cache.u.segment.d_b = 0; // default 16bit size
|
|
seg->cache.u.segment.avl = 0;
|
|
return(1); // ok
|
|
}
|
|
|
|
return(0); // can't change when not in real mode
|
|
}
|
|
|
|
unsigned BX_CPU_C::dbg_query_pending(void)
|
|
{
|
|
unsigned ret = 0;
|
|
|
|
if (BX_HRQ) { // DMA Hold Request
|
|
ret |= BX_DBG_PENDING_DMA;
|
|
}
|
|
|
|
if (BX_CPU_THIS_PTR INTR && BX_CPU_THIS_PTR get_IF()) {
|
|
ret |= BX_DBG_PENDING_IRQ;
|
|
}
|
|
|
|
return(ret);
|
|
}
|
|
|
|
bx_bool BX_CPU_C::dbg_get_sreg(bx_dbg_sreg_t *sreg, unsigned sreg_no)
|
|
{
|
|
if (sreg_no > 5)
|
|
return(0);
|
|
sreg->sel = BX_CPU_THIS_PTR sregs[sreg_no].selector.value;
|
|
sreg->des_l = get_descriptor_l(&BX_CPU_THIS_PTR sregs[sreg_no].cache);
|
|
sreg->des_h = get_descriptor_h(&BX_CPU_THIS_PTR sregs[sreg_no].cache);
|
|
sreg->valid = BX_CPU_THIS_PTR sregs[sreg_no].cache.valid;
|
|
return(1);
|
|
}
|
|
|
|
void BX_CPU_C::dbg_get_tr(bx_dbg_sreg_t *sreg)
|
|
{
|
|
sreg->sel = BX_CPU_THIS_PTR tr.selector.value;
|
|
sreg->des_l = get_descriptor_l(&BX_CPU_THIS_PTR tr.cache);
|
|
sreg->des_h = get_descriptor_h(&BX_CPU_THIS_PTR tr.cache);
|
|
sreg->valid = BX_CPU_THIS_PTR tr.cache.valid;
|
|
}
|
|
|
|
void BX_CPU_C::dbg_get_ldtr(bx_dbg_sreg_t *sreg)
|
|
{
|
|
sreg->sel = BX_CPU_THIS_PTR ldtr.selector.value;
|
|
sreg->des_l = get_descriptor_l(&BX_CPU_THIS_PTR ldtr.cache);
|
|
sreg->des_h = get_descriptor_h(&BX_CPU_THIS_PTR ldtr.cache);
|
|
sreg->valid = BX_CPU_THIS_PTR ldtr.cache.valid;
|
|
}
|
|
|
|
void BX_CPU_C::dbg_get_gdtr(bx_dbg_global_sreg_t *sreg)
|
|
{
|
|
sreg->base = BX_CPU_THIS_PTR gdtr.base;
|
|
sreg->limit = BX_CPU_THIS_PTR gdtr.limit;
|
|
}
|
|
|
|
void BX_CPU_C::dbg_get_idtr(bx_dbg_global_sreg_t *sreg)
|
|
{
|
|
sreg->base = BX_CPU_THIS_PTR idtr.base;
|
|
sreg->limit = BX_CPU_THIS_PTR idtr.limit;
|
|
}
|
|
|
|
#endif // #if BX_DEBUGGER
|
|
|
|
void BX_CPU_C::atexit(void)
|
|
{
|
|
debug(BX_CPU_THIS_PTR prev_rip);
|
|
}
|